picor corporation ? www.picorpower.com qpi-9 data sheet rev. 1.3 page 1 of 8 hot-swap sip with v ? i chip emi filter qpi-9 quietpower ? features ? >50 db cm attenuation at 1 mhz ? >70 db dm attenuation at 1 mhz ? 40 vdc (max input) ? 100 vdc surge 100 msec ? 707 v hipot hold off to shield ? 6 a breaker with delay plus 12 a limiter ? 25 x 25 x 4.5 mm sip (system in package) ? low profile lga package ? -40 to +100c pcb temperature (see fig. 5) ? hot-swap & filter combined saves pcb space ? efficiency >98% ? connects between or?ing diodes & power conversion input hold-up capacitance ? patents pending applications ? industrial and military cots figure 1 ? block diagram figure 2 ? typical attenuation description the qpi-9 includes the total hot-swap function along with an emi filter for v ? i chip applications. the emi filter is designed to attenuate the conducted common-mode (cm) and differential-mode (dm) noise generated by the higher switching frequencies of the v ? i chips. the qpi-9 is designed for use on a 24 vdc bus. the in-rush current limit and circuit breaker are designed to deliver over 140 w of power with an input voltage of 24 v on the converter. the qpi-9's internal fault timer allows it to operate safely in the event of a short across its output. the qpi-9 enters a retry mode where it will attempt to restart until the short condition is removed. the under and over voltage thresholds can be trimmed separately via the uven and ov inputs using external series resistors. the qpi-9 provides two power good signals, pwrgd1 referenced to the input ground and pwrgd2 to the output ground, which can be used to enable other circuits along with the v ? i chip converter. ?
picor corporation ? www.picorpower.com qpi-9 data sheet rev. 1.3 page 2 of 8 absolute maximum ratings ? exceeding these parameters may result in permanent damage to the product. pins parameter notes min typ max units bus+, sw, pwrgd1, input voltage continuous -0.5 40 vdc pwrgd2 to bus- bus+, sw, pwrgd1, input voltage 100 msec transient 100 vdc pwrgd2 to bus- bus+/bus- to shield bus inputs to shield hipot +/-707 vdc qpi+ to qpi- input to output current pulsed limit @ 25c 12 adc package power dissipation vbus = 24 v, 6 adc, 25c 3.0 w package operating temperature pcb to qpi interface -40 100 c package thermal resistance free air 50 c/w package junction temperature tb = 100 c pd = 3 w @15 c/w 145 c package thermal resistance pcb layout dependent (1) 15 c/w package storage temperature -40 125 c package re-flow temperature 20 s exposure @ (2) 212 c all pins esd hbm +/-2 kv note 1: refer to figure 15 and 16 for critical pcb layout guidelines to achieve this thermal resistance when reflowed onto the pcb. note 2: rohs compliant product maximum peak temperature is 245c for 20 seconds. qpi-9 sip package (bottom view) 9 10 11 12 4 3 2 1 8 7 6 5 13 14 15 16 pwrgd2 pwrgd1 ov bus+ shield sw bus- qpi+ qpi- bus+ uven sw bus- pad description pin number name description 1, 16 bus- negative bus potential 2, 3, 15 sw negative rail controlled by hot insertion function. 4 shield shield connects to the filter's shield pad and the chassis's common pin 5, 6 qpi- negative input to the converter 7, 8 qpi+ positive input to the converter 10 pwrgd1 open drain, referenced to bus-, that asserts low when power is not good 9 pwrgd2 open drain, referenced to qpi-, that asserts low when power is not good 12, 13 bus+ positive bus potential 14 uven highside of uv resistor divider 11 ov highside of ov resistor divider electrical characteristics ? parameter limits apply over the operating pcb temperature range unless otherwise noted symbol parameter notes min typ max units vb+b- bus+ to bus- input range measured at 5 a (3) uv 38 vdc v+oi bus+ to qpi+ voltage drop measured at 5 a (3) 110 mvdc v-oi bus- to qpi- voltage drop measured at 5 a (3) -380 mvdc cmil common-mode insertion loss vbus = 48 v frequency =1 mhz 50 db dmil differential-mode insertion loss vbus = 48 v frequency =1 mhz 70 db i bus + to bus- input bias current at 80 v input current from bus+ to bus- 10 ma ipg qpi+ to qpi- load current prior to pwrgd critical maximum dc load 25 ma uv undervoltage threshold - rising controller disabled to enabled 18 v uvhys undervoltage hysteresis - falling controller enabled to disabled uv - 2 v v ov overvoltage threshold - rising controller enabled to disabled 38 v ovhys overvoltage hysteresis - falling controller disabled to enabled ov - 2 v v pwrgd1sat power good low voltage ipwg = 1 ma, referenced to bus- 0.2 0.6 mv pwrgd2sat power good low voltage ipwg = 1 ma, referenced to qpi- 0.2 0.6 mv pwglk power good high leakage vpwg = 40 v 1 a note 3: refer to figure 5 for current derating curve.
picor corporation ? www.picorpower.com qpi-9 data sheet rev. 1.3 page 3 of 8 applications information the qpi-9 is an emi filter especially designed for v?i chip products, providing conducted common-mode and differential-mode attenuation from 150 khz to 30 mhz. designed for the industrial and military bus range, the qpi supports the filtering of system boards using vicor's v?i chip technology to the en55022 class b limit. the resulting plot in figure 4 shows the qpi-9 is effective in reducing the v ? i chip total noise spectrum to well below the en55022 class b quasi-peak detection limit. the plot in figure 4 was taken using the standard 50/50 h lisn and measurement conditions, with the peak detection mode of the spectrum analyzer, for a conducted emi test. the results are compared to the cispr22 en55022 class b quasi-peak detection limit and show the total noise spectrum for v ? i chip combination using mp028f036m12al & mv036f120m010 with qpi-9 connected, as shown in figure 3. figure 3 ? standard lisn test setup, 100 w load. figure 4 ? conducted emi profile of v?i chip with qpi-9 with a 100 w load.
picor corporation ? www.picorpower.com qpi-9 data sheet rev. 1.3 page 4 of 8 applications information ? hot-swap the qpi-9's high-temperature rating of 6 amps provides filtering for up to 144 w of power from a 24 v bus with a 70c pcb temperature. the 1.0" x1.0" x 0.2" surface mount lga package provides ease of manufacturing by eliminating thru-hole assembly. the current derating curve, shown in figure 5, should be used when the pcb temperature that the qpi-9 is mounted to exceeds 70c. the hot-swap feature is created with an internal switch that controls the current path between bus- and sw pins. the state of the switch can be on, off or in a current control mode depending on the state of the control function. the qpi-9 has two signal pins that can be used to indicate the power-up status of the qpi-9. both are active-low when power is not good. pwrgd1 is an open-drain that is referenced to the bus- rail of the qpi-9. pwrgd2 is an open-drain that is referenced to the qpi- rail, allowing it to directly control the enable pin of the v ? i chip converter, without any kind of signal translation required. an example circuit of both options can be seen in figures 9a and 9b. the qpi-9 is designed to have an under-voltage range of 16 v to 18 v set point when the uven pin is tied directly to the bus+ pin. the qpi-9 becomes enabled when the input voltage exceeds 18 v and continues to work down to 16 v before being disabled. the qpi-9 over-voltage range is designed to be 36 v to 38 v when the ov pin is tied directly to the bus+ pin. the qpi-9 remains functioning until the input voltage surpasses 38 v, where the qpi-9 will shutdown until the input voltage falls below 36 v. external resistors can be added to trim the uv and ov trip points higher. the graph in figure 6 shows the trimming effect for a range of external series resistors. the equations in figure 7 can be used to calculate the required series resistor for increasing the preprogrammed trip points. figure 8 shows a 5 ms, zero-volt bus transient event with a 40 w load and 4700 f of capacitance on the qpi-9's output. the external capacitor ce, shown in figures 9a and 9b, will provide the required hold-up filtering during the transient event. this filtering will enable the power-good state of the qpi-9 to remain unchanged during this transient, provided there is enough input energy to maintain the power converter's operation. without this capacitor, the qpi-9 would detect an under-voltage fault and shut off its internal pass switch. the fault would also initiate a re-start of the hot-swap control and would require up to 45 ms to turn back on its internal switch. note: when using ce in this manner, ruven should be used qpi-9 current derating curve 0 2 4 6 8 0 102030405060708090100 pcb to qpi interface temperature (c) qpi differential current (amps) figure 5 ? qpi-9 current derating curve over temperature. figure 8 ? 5 ms transient with 40 w load. figure 7 ? uven and ov resistor equations. uven lo = 2.5 v(ruven + 118,700) 18700 uven hi = 2.5 v + (ruven + 100,000)(154 a) ov lo = 2.5 v + (rov + 102,000)(350 a) ov hi = 2.5 v(rov + 109,150) 7150 uv/ov trim 0.00 10.00 20.00 30.00 40.00 50.00 0 5000 10000 15000 20000 25000 30000 series resistor voltage ov-high ov-low uv-high uv-low figure 6 ? trimming uv/ov with an external series resistor.
picor corporation ? www.picorpower.com qpi-9 data sheet rev. 1.3 page 5 of 8 figure 9a ? typical atca system with qpi-9 and high enable converter. figure 9b ? typical atca system with qpi-9 and high enable converter.
picor corporation ? www.picorpower.com qpi-9 data sheet rev. 1.3 page 6 of 8 start-up the following oscilloscope pictures show the hot swap bus- current, qpi- to bus- voltage and pwrgd to bus- output voltage of the qpi-9 during operation. figures 10 and 11 are the qpi-9's in-rush characteristics under two load capacitance conditions. in figure 10 a 470 f capacitor required roughly 330 ms to completely charge from a 24 v bus voltage. the qpi-9 can drive large amounts of bulk capacitance to maintain converter operation during a 0v bus transient event, as shown in figure 11 with a 4700 f load capacitance. under this condition the pwrgd takes about 2.9 seconds to go high after the uven input is pulled high upon the complete insertion of the board into the shelf. figure 11's time-scale is too long to show the current pulses that charge the bulk capacitance. after insertion, when the uven voltage exceeds 18 v the uv detection fault is cleared, the qpi-9 goes through a delay cycle (~45 ms) to allow for system stabilization and de-bounce. after this time, the qpi- to bus- path is turned on and current is allowed to pass, monitored by the current sense function. initially the current level exceeds the 6 a circuit breaker limit, the event timer starts and the power good state is not valid. the sense function and linear control loop will allow twice the circuit breaker current to pass. if the current does not drop below the circuit breaker level prior to reaching the timer limit, typically 800 s, the qpi- to bus- path will open. the effective duty cycle under the current limit condition is approximately 1%. once the load capacitors are fully charged to the input bus potential, the load condition falls below 6 a and the pwrgd pin is asserted high, providing that the bus supply is still within the uv and ov range. transient protection and recovery figures 12 and 13 show the qpi-9's ability to handle low resistance shorts (< 2) at the load terminals to emulate fast and slow blown fuse events. in figure 12, the transient short is 2 seconds long and the qpi- to bus- path is opened within 1 ms of this occurrence. figure 13 demonstrates the qpi-9's performance with a short circuit on its output, where it remains in a low duty cycle mode until the short is removed, then restarts normally. figure 10 ? 470 f capacitor @ 24 v. figure 12 ? 2 seconds short-circuit. figure 13 ? start-up into short circuit. figure 11 ? 4700 f capacitor @ 24 v.
picor corporation ? www.picorpower.com qpi-9 data sheet rev. 1.3 page 7 of 8 qpi-9 pcb layout recommendations the filtering performance of the qpi-9 and ?10 is sensitive to capacitive coupling between its input and output pins. parasitic plane capacitance must be kept below 1 pico-farad between inputs and outputs using the layout shown above and the recommendations described below to achieve maximum conducted emi performance. to avoid capacitive coupling between input and output pins, there should not be any planes or large traces that run under both input and output pins, such as a ground plane or power plane. for example, if there are two signal planes or large traces where one trace runs under the input pins, and the other under the output pins, and both planes over-lap in another area, they will cause capacitive coupling between input and output pins. also, planes that run under both input and outputs pins, but do not cross, can cause capacitive coupling if they are capacitively by-passed together. figure 17 shows the recommended pcb layout on a 2 layer board. here, the top layer planes are duplicated on the bottom layer so that there can be no over- lapping of input and output planes. this method can be used for boards of greater layer count. figure 14 ? sip package mechanicals; lga pad, package height and pad location dimensions ? inches. figure 16 ? recommended pcb receiving footprint. figure 17 ? recommended pcb layout on a 2 layer board figure 15 ? recommended pcb receiving pattern. mechanical & layout information ordering information part number description qpi-9lz qpi-9 lga package, rohs compliant QPI-9LZ-01 qpi-9 lga, rohs compliant open frame package picor lidded qp sips are not hermetically sealed and must not be exposed to liquid, including but not limited to cleaning solvents, aqueous washing solutions or pressurized sprays. when soldering, it is recommended that no-clean flux solder be used, as this will insure that potentially corrosive mobile ions will not remain on, around, or under the module following the soldering process. for applications requiring water wash compatibility the ??01? open frame version should be used. post solder cleaning
picor corporation ? www.picorpower.com ? qpi-10 data sheet rev. 1.3 10/08 vicor?s comprehensive line of power solutions includes high-density ac-dc & dc-dc modules and accessory components, fully configurable ac-dc & dc-dc power supplies, and complete custom power systems. information furnished by vicor is believed to be accurate and reliable. however, no responsibility is assumed by vicor for its use. no license is granted by implication or otherwise under any patent or patent rights of vicor. vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. all sales are subject to vicor?s terms and conditions of sale, which are available upon request. specifications are subject to change without notice. vicor corporation 25 frontage road, andover, ma, usa 01810 tel: 800-735-6200 fax: 978-475-6715 email sales support: vicorexp@vicorpower.com technical support: apps@vicorpower.com
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