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| 1 ae1e fujitsu semiconductor data sheet memory cmos 8 x 256k x 32 bit, fcram tm core based double data rate sdram MB81P643287-50/-60 cmos 8-bank x 262,144-word x 32 bit, fcram core based synchronous dynamic random access memory with double data rate n description the fujitsu MB81P643287 is a cmos synchronous dynamic random access memory (sdram) with fujitsu advanced fcram (fast cycle random access memory) core technology, containing 67,108,864 memory cells accessible in an 32-bit format. the MB81P643287 features a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the MB81P643287 is designed to reduce the complexity of using a standard dynamic ram (dram) which requires many control signal timing constraints. the MB81P643287 uses double data rate (ddr) where data bandwidth is twice of fast speed compared with regular sdrams. the MB81P643287 is ideally suited for digital visual systems, high performance graphic adapters, hardware accelerators, buffers, and other applications where large memory density and high effective bandwidth are required and where a simple interface is needed. the MB81P643287 adopts new i/o interface circuitry, sstl_2 interface, which is capable of extremely fast data transfer of quality under either terminated or point to point bus environment. n product line notice : fcram is a trademark of fujitsu limited, japan. parameter MB81P643287 -50 -60 clock frequency cl = 3 200 mhz max 167 mhz max cl = 2 133 mhz max 111 mhz max burst mode cycle time cl = 3 2.5 ns min 3.0 ns min cl = 2 3.75 ns min 4.5 ns min random address cycle time 30 ns min 36 ns min dqs access time from clock 0.1*t ck + 0.2 ns max 0.1*t ck + 0.2 ns max operating current 460 ma max 405 ma max power down current 35 ma max
2 MB81P643287-50/-60 preliminary (ae1e) n features n pac k ag e ? 4096 auto-refresh cycles in 32 ms ? sstl_2 (class 2) for all signals ?v dd : +2.5v supply 0.2v tolerance ?v ddq : +2.5v supply 0.2v tolerance ? double data rate ? bi-directional data strobe signal ? eight bank operation ? burst read/write operation ? programmable burst length and cas latency ? byte write control by dm 0 to dm 3 ? standby power down mode package and ordering information C 86-pin plastic (400 mil) tsop-ii, order as MB81P643287-xxfn plastic tsop(ii) package (fpt-86p-m01) (normal bend) 3 MB81P643287-50/-60 preliminary (ae1e) n pin assignments and descriptions 86-pin tsop(ii) (top view) 74 73 72 71 70 69 68 67 66 86 85 84 83 82 81 80 79 78 77 1 2 3 4 5 9 10 6 7 8 13 14 15 16 17 18 19 20 21 22 76 75 11 12 65 64 63 62 61 60 23 24 25 26 27 58 57 56 55 54 53 52 51 50 29 30 31 32 33 34 35 36 37 38 59 28 49 48 47 46 45 44 39 40 41 42 43 v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq dq 7 dqs 0 v dd dm 0 we cas ras cs ba 2 ba 0 ba 1 a 10 /ap a 0 a 1 a 2 dm 2 v dd dqs 2 dq 16 v ssq dq 17 dq 18 v ddq dq 19 dq 20 v ssq dq 21 dq 22 v ddq dq 23 v dd v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq dq 8 dqs 1 v ss dm 1 v ref clk clk cke a 9 a 8 a 7 a 6 a 5 a 4 a 3 dm 3 v ss dqs 3 dq 31 v ddq dq 30 dq 29 v ssq dq 28 dq 27 v ddq dq 26 dq 25 v ssq dq 24 v ss pin number symbol function 1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81 v dd , v ddq supply voltage 6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86 v ss , v ssq ground 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 dq 0 to dq 31 data i/o ? byte 0 : dq 0 to dq 7 ? byte 1 : dq 8 to dq 15 ? byte 2 : dq 16 to dq 23 ? byte 3 : dq 24 to dq 31 14, 30, 57, 73 dqs 0 to dqs 3 data strobe ?dqs 0 : for dq 0 to dq 7 ?dqs 1 : for dq 8 to dq 15 ?dqs 2 : for dq 16 to dq 23 ?dqs 3 : for dq 24 to dq 31 16, 28, 59, 71 dm 0 to dm 3 input mask 17 we write enable 18 cas column address strobe 19 ras row address strobe 20 cs chip select 21, 22, 23 ba 2 , ba 1 , ba 0 bank select (bank address) 24 ap auto precharge enable 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 a 0 to a 10 address input ? row: a 0 to a 10 ? column: a 0 to a 6 67 cke power down 68 clk clock input 69 clk clock input 70 v ref input reference voltage 4 MB81P643287-50/-60 preliminary (ae1e) n block diagram fig. 1 C MB81P643287 block diagram clk clk a 0 to a 10 ba 0 ,ba 1 ,ba 2 dq 0 to dq 31 ras cas we cs bank-1 v dd clock buffer control signal latch mode register column address counter ras cas we dram core (2048 x 128 x 32) column address bank-0 i/o row address to each block v ref command decoder address buffer/ register i/o data buffer/ register & dqs genera- tor dm 0 to dm 3 v ss / v ssq bank-7 ap dqs 0 to dqs 3 32 enable v ddq , v ssq cke dll clock buffer 11 7 . . . . . . . . . 5 MB81P643287-50/-60 preliminary (ae1e) n function truth table note *1 command truth table note *2, and *3 notes: *1. v = valid, l = logic low, h = logic high, x = either l or h, hi-z = high impedance. *2. all commands are assumed to be valid state transitions. *3. all inputs for command are latched on the rising edge of clock(clk). *4. nop and desl commands have the same effect on the part. unless specifically noted, nop will represent both nop and desl command in later descriptions. *5. bst is effective after read command is issued. *6. read, reada, writ and writa commands should only be issued after the corresponding bank has been activated (actv command). refer to state diagram in page 18. *7. actv command should only be issued after corresponding bank has been page closed by pre or pall command. *8. either pre or pall command and mrs or emrs command are required after power up. *9. mrs or emrs command should only be issued after all banks have been page closed (pre or pall command), and dqs are in hi-z. refer to state diagram. *10. refer to mode register table. function notes symbol cke cs ras cas we ap ba 2-0 a 10 a 9 a 8-7 a 6-0 device deselect *4 desl h h x x x x x x x x x no operation *4 nop h l h h h x x x x x x burst stop *5 bst h l h h l x x x x x x read *6 read h l h l h l v x x x v read with auto-precharge *6 reada h l h l h h v x x x v write *6 writ h l h l l l v x x x v write with auto-precharge *6 writa h l h l l h v x x x v bank active (ras )*7actvhllhhxvvvvv precharge single bank *8 pre h l l h l l v x x x v precharge all banks *8 pall h l l h l h v x x x v mode register set/ extended mode register set *8,9,10 mrs/ emrs hll lll vlvvv 6 MB81P643287-50/-60 preliminary (ae1e) n function truth table (continued) dm truth table (effective during write mode) cke truth table notes:*11. the ref and self commands should only be issued after all banks have been precharged (pre or pall command). in case of self command, it should also be issued after the last read data have been appeared on dq. refer to state diagram. *12. cke must bring to low level together with ref command. *13. the pden command should only be issued after the last read data have been appeared on dq and after the l dpl is satisfied from last write data input. function command cke dm 0 dm 1 dm 2 dm 3 (n - 1) (n) data mask for dq 0 to dq 7 mask0 h x h x x x data mask for dq 8 to dq 15 mask1 h x x h x x data mask for dq 16 to dq 23 mask2 h x x x h x data mask for dq 24 to dq 31 mask3hxxxxh current state function notes command cke cs ras cas we ap ba 0-2 a 10-0 dq 0-31 (n-1) (n) idle auto-refresh *11 ref h h l l l h x x x idle self-refresh entry *11 *12 self hlll lhxxxhi-z self- refresh self-refresh continue l l x x x x x x x hi-z self- refresh self-refresh exit selfx lhlhhhxxxhi-z lhhxxxxxxhi-z idle power down entry *13 pden hllhhhxxxhi-z hlhxxxxxxhi-z power down power down continue l l x x x x x x x hi-z power down power down exit pdex lhlhhhxxxhi-z lhhxxxxxxhi-z 7 MB81P643287-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (applicable to single bank) note *13 current state cs ras cas we address command function notes idle hxxx x desl nop lhhh x nop nop lhhl x bst nop *15 l h l h ba, ca, ap read/reada illegal *16 l h l l ba, ca, ap writ/writa illegal *16 l l h h ba, ra actv bank active after l rcd l l h l ba, ap pre nop l l h l ba, ap pall nop *15 l l l h x ref/self auto-refresh or self-refresh *17 llll mode mrs mode register set (idle after l mrd ) *17 bank active h x x x x desl nop lhhh x nop nop lhhl x bst nop *15 l h l h ba, ca, ap read/reada begin read; determine ap l h l l ba, ca, ap writ/writa begin write; determine ap l l h h ba, ra actv illegal *16 l l h l ba, ap pre precharge l l h l ba, ap pall precharge *15 lllh x ref/selfillegal llll mode mrs illegal 8 MB81P643287-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (continued) current state cs ras cas we address command function notes read hxxx x desl nop (continue burst to end -> bank active) lhhh x nop nop (continue burst to end -> bank active) l h h l x bst terminate burst -> bank active l h l h ba, ca, ap read/reada terminate burst, new read; determine ap l h l l ba, ca, ap writ/writa illegal l l h h ba, ra actv illegal *16 l l h l ba, ap pre terminate burst, precharge l l h l ba, ap pall terminate burst, precharge *15 lllh x ref/selfillegal llll mode mrs illegal write hxxx x desl nop (continue burst to end -> write recovering) lhhh x nop nop (continue burst to end -> write recovering) l h h l x bst illegal l h l h ba, ca, ap read/reada terminate burst, start read; determine ap *20 l h l l ba, ca, ap writ/writa terminate burst, new write; determine ap l l h h ba, ra actv illegal *16 l l h l ba, ap pre terminate burst, precharge *18 l l h l ba, ap pall terminate burst, precharge *15, *18 lllh x ref/selfillegal llll mode mrs illegal 9 MB81P643287-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (continued) current state cs ras cas we address command function notes read with auto- precharge hxxx x desl nop (continue burst to end -> precharge) lhhh x nop nop (continue burst to end -> precharge) l h h l x bst illegal l h l h ba, ca, ap read/reada illegal *16 l h l l ba, ca, ap writ/writa illegal l l h h ba, ra actv illegal *16 l l h l ba, ap pre illegal *16 l l h l ba, ap pall illegal lllh x ref/selfillegal llll mode mrs illegal write with auto precharge hxxx x desl nop (continue burst to end -> write recovering with precharge) lhhh x nop nop (continue burst to end -> write recovering with precharge) l h h l x bst illegal l h l h ba, ca, ap read/reada illegal l h l l ba, ca, ap writ/writa illegal *16 l l h h ba, ra actv illegal *16 l l h l ba, ap pre illegal *16 l l h l ba, ap pall illegal lllh x ref/selfillegal llll mode mrs illegal 10 MB81P643287-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (continued) current state cs ras cas we address command function notes precharging h x x x x desl nop (idle after l rp ) l h h h x nop nop (idle after l rp ) l h h l x bst nop (idle after l rp )*15 l h l h ba, ca, ap read/reada illegal *16 l h l l ba, ca, ap writ/writa illegal *16 l l h h ba, ra actv illegal *16 l l h l ba, ap pre nop *16 l l h l ba, ap pall nop *15 lllh x ref/selfillegal llll mode mrs illegal bank activating h x x x x desl nop (bank active after l rcd ) l h h h x nop nop (bank active after l rcd ) l h h l x bst nop (bank active after l rcd )*15 l h l h ba, ca, ap read/reada illegal *16 l h l l ba, ca, ap writ/writa illegal *16 l l h h ba, ra actv illegal *19 l l h l ba, ap pre illegal *16 l l h l ba, ap pall illegal lllh x ref/selfillegal llll mode mrs illegal 11 MB81P643287-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (continued) current state cs ras cas we address command function notes write recovering h x x x x desl nop (bank active after l wrd ) l h h h x nop nop (bank active after l wrd ) l h h l x bst nop (bank active after l wrd )*15 l h l h ba, ca, ap read/reada illegal *16 l h l l ba, ca, ap writ/writa new write; determine ap l l h h ba, ra actv illegal *16 l l h l ba, ap pre illegal *16 l l h l ba, ap pall illegal lllh x ref/selfillegal llll mode mrs illegal write recovering with auto- precharge h x x x x desl nop (idle after l wal ) l h h h x nop nop (idle after l wal ) l h h l x bst illegal l h l h ba, ca, ap read/reada illegal *16 l h l l ba, ca, ap writ/writa illegal *16 l l h h ba, ra actv illegal *16 l l h l ba, ap pre illegal *16 l l h l ba, ap pall illegal lllh x ref/selfillegal llll mode mrs illegal refreshing h x x x x desl nop (idle after l rfc ) l h h x x nop/bst nop (idle after l rfc ) lhlx x read/reada/ writ/writa illegal llhx x actv/ pre/pall illegal lllx x ref/self/ mrs illegal 12 MB81P643287-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (continued) abbreviations: ra = row address ba = bank address ca = column address ap = auto precharge notes:*14. all entries assume the cke was high during the proceeding clock cycle and the current clock cycle. *15. entry may affect other banks. *16. illegal to bank in specified state; entry may be legal in the bank specified by ba, depending on the state of that bank. *17. illegal if any bank is not idle. *18. must mask preceding data that dont satisfy l dpl . *19. legal if other bank specified in ba is idle state and l rrd is satisfied for that bank. *20. must mask preceding data that dont satisfy l wrd . current state cs ras cas we address command function notes mode register setting h x x x x desl nop (idle after l mrd ) l h h h x nop nop (idle after l mrd ) l h h l x bst illegal lhlx x read/reada/ writ/writa illegal llxx x actv/pre/ pall/ref/ self/mrs illegal 13 MB81P643287-50/-60 preliminary (ae1e) n function truth table (continued) command truth table for cke current state cke (n-1) cke (n) cs ras cas we address function notes self- refresh hxxxxx xinvalid lhhxxx x exit self-refresh (self-refresh recovery -> idle after t pdex + l scd or l xsnr ) lhlhhh x exit self-refresh (self-refresh recovery -> idle after t pdex + l scd or l xsnr ) lhlhhl xillegal lhlhlx xillegal l h l l x x x illegal l lxxxx xnop (maintain self-refresh) self- refresh recovery lxxxxx xinvalid hhhxxx xidle after l scd or l xsnr hhlhhh xidle after l scd or l xsnr h h l h h l x illegal h h l h l x x illegal h h l l x x x illegal hlxxxx xillegal power down hxxxxx xinvalid lhhxxx x power down exit -> return to original state after t pdex lhlhhh x power down exit -> return to original state after t pdex lhlhhl xillegal lhlhlx xillegal l h l l x x x illegal l lxxxx xnop (maintain power down mode) 14 MB81P643287-50/-60 preliminary (ae1e) n function truth table (continued) command truth table for cke (continued) current state cke (n-1) cke (n) cs ras cas we address function notes all banks idle hhhxxx xnop h h l h x x v refer to the command truth table. h h l l h x v refer to the command truth table. h h l l l h x auto-refresh hhllll vmode register set *21 h l h x x x x power down entry *22 h l l h h h x power down entry *22 hllhhl xillegal h l l h l x x illegal hlllhx xillegal hllllh xself-refresh entry *22 hlllll xillegal lxxxxx xinvalid bank activehhxxxx xrefer to the command truth table. hlxxxx xillegal lhxxxx xinvalid l lxxxx xinvalid 15 MB81P643287-50/-60 preliminary (ae1e) n function truth table (continued) command truth table for cke (continued) notes:*21. refer to mode register table. *22. pden and self command should only be issued after the last read data have been appeared on dq. *23. the clock suspend mode is not supported on this device and it is illegal if cke is brought to low during the burst read or write mode. current state cke (n-1) cke (n) cs ras cas we address function notes bank activating, read, write, write recovering, precharging hhxxxx xrefer to the command truth table. hlxxxx xillegal *23 lhxxxx xinvalid l lxxxx xinvalid any state other than listed above lxxxxx xinvalid hhxxxx xrefer to the command truth table. hlxxxx xillegal *23 refresh hlhlll xillegal hl lhhh xillegal hllhhl xillegal h l l h l x x illegal hlllxx xillegal l lxxxx xinvalid lhxxxx xinvalid hhxxxx xrefer to the command truth table. 16 MB81P643287-50/-60 preliminary (ae1e) n state diagram minimum clock latency or delay time for single bank operation notes: *1. bl/2 = t ck * bl / 2. (example: in case of bl = 4, bl/2 means 2 clocks.) *2. assume pall command does not affect any operation on the other bank(s). *3. assume no i/o conflict. *4. l ras must be satisfied. *5. assume all outputs are in high-z state. *6. assume all other banks are in idle state. *7. l dpl and l wrd are specified from last data input and assumed preceding pair of write data are masked by dm 0-3 input. illegal command second command (same bank) mrs actv read reada writ writa bst pre pa l l ref self first command mrs l mrd l mrd l mrd l mrd l mrd l mrd l mrd actv l rcd *4 l rcd l rcd *4 l rcd 1l ras l ras read 1 * 4 1 * 3 l rwd *3, 4 l rwd 1 *4 1 *4 1 reada *5, 6 bl/2 + l rp bl/2 + l rp *4 bl/2 + l rp *4 bl/2 + l rp *6 bl/2 + l rp *5, 6 bl/2 + l rp writ *7 l wrd *4, 7 l wrd 1 * 4 1 *4,7 l dpl *4,7 l dpl writa *6 l wal l wal *4 l wal *4 l wal *6 l wal *6 l wal bst 11 *3 l bsnc *3 l bsnc 1 *4 1 *4 1 pre *5, 6 l rp l rp 1 1 *4 1 *6 l rp *5, 6 l rp pa l l *5 l rpa l rpa 1 11l rpa *5 l rpa ref l rfc l rfc l rfc l rfc l rfc l rfc l rfc selfx l xsnr l xsnr l xsnr l xsnr l xsnr l xsnr l xsnr *1 17 MB81P643287-50/-60 preliminary (ae1e) n state diagram (continued) minimum clock latency or delay time for multiple bank operation notes: *1. bl/2 = t ck * bl / 2. (example: in case of bl = 4, bl/2 means 2 clocks.) *2. assume pall command does not affect any operation on the other bank(s). *3. assume no i/o conflict. *4. l ras must be satisfied. *5. assume all outputs are in high-z state. *6. assume the other bank(s) is in idle state. *7. l dpl and l wrd are specified from last data input and assumed preceding pair of write data are masked by dm 0-3 input. *8. assume the other bank(s) is in active state and l rcd is satisfied. *9. assume the other bank(s) is in active state and l ras is satisfied. *10. second command have to follow the minimum clock latency or delay time of single bank operation in other bank (second command is asserted.) *11. assume other banks are not in reada/writa state. illegal command. second command (other bank) mrs actv read reada writ writa bst pre pa l l ref self first command mrs l mrd l mrd l mrd l mrd l mrd l mrd l mrd actv *6 l rrd *11 1 *11 1 *11 1 *11 1 *11 11l ras read *6 111 * 3 l rwd *3 l rwd 11 *4 1 reada *5, 6 bl/2 + l rp *6 1 *4 1 *4 1 * 3, 4 l rwd * 3, 4 l rwd 1 bl/2 + l rp *6 bl/2 + l rp *5, 6 bl/2 + l rp writ *6 1 *7 l wrd *7 l wrd 11 1 *4,7 l dpl writa *6 l wal *6 1 *4 bl/2 + l wrd *4 bl/2 + l wrd *4 1 *4 1 1l wal *6 l wal *6 l wal bst *6 1 *11 1 *11 1 *3, 11 l bsnc *3, 11 l bsnc 11 *4 1 pre *5, 6 l rp *6 1 *11 1 *11 1 *3, 11 1 *3, 11 1 *11 11 *4 1 *6 l rp *5, 6 l rp pa l l *5 l rpa l rpa 111l rpa *5 l rpa ref l rfc l rfc l rfc l rfc l rfc l rfc l rfc selfx l xsnr l xsnr l xsnr l xsnr l xsnr l xsnr l xsnr *9 *2, 9 *10 *8 *8 *8 *8 18 MB81P643287-50/-60 preliminary (ae1e) n state diagram (continued) mode register set self- refresh idle auto refresh power down fig. 2 C state diagram (simplified for single bank operation) write power on precharge read write with auto precharge read with auto precharge writ read read writ bst mrs self selfx ref actv pdex read writ reada writa pdex and 8 pre (or 1 pall) pre or pa l l power applied with pden definition of allows manual input automatic sequence writa reada pre or pa l l pre or pa l l pden reada writa bank active 19 MB81P643287-50/-60 preliminary (ae1e) n functional description ddr, double data rate function the regular sdram read and write cycle have only used the rising edge of external clock input. when clock signal goes to high from low at the read mode, the read out data will be available at every rising clock edge after the specified latency up to burst length. the MB81P643287 ddr fcram features a twice of data transfer rate within a same clock period by transferring data at every rising and falling clock edge. refer to figure 3 in page 24. fcram tm the MB81P643287 utilizes fcram core technology. the fcram is an acronym of fast cycle random access memory and provides very fast random cycle time, low latency and low power consumption than regular drams. clock (clk, clk ) the MB81P643287 adopts differential clock scheme. clk is a master clock and its rising edge is used to latch all command and address inputs. clk is a complementary clock input. the MB81P643287 implements delay locked loop (dll) circuit. this internal dll tracks the signal cross point between clk and clk and generate some clock cycle delay for the output buffer control at read mode. the internal dll circuit requires some lock-on time for the stable delay time generation. in order to stabilize the delay, a constant stable clock input for l pcd period is required during the power-up initialization and a constant stable clock input for l scd period is also required after self-refresh exit as specified l scd prior to the any command. power down (cke) cke is a synchronous input signal and enables power down mode. when all banks are in idle state, cke controls power down (pd) and self-refresh mode. the pd and self-refresh is entered when cke is brought to low and exited when it returns to high. during the power down and self-refresh mode, both clk and clk are disabled after specified time. cke does not have a clock suspend function unlike cke pin of regular sdrams, and it is illegal to bring cke into low if any read or write operation is being performed. for the detail, refer to timing diagrams. it is recommended to maintain cke to be low until v dd gets in the specified operating range in order to assure the power-up initialization. chip select (cs ) cs enables all commands inputs, ras , cas , and we , and address input. when cs is high, all command signals are negated but internal operation such as burst cycle will not be suspended. command inputs (ras , cas and we ) as well as regular sdrams, each combination of ras , cas and we input in conjunction with cs input at a rising edge of the clk determines sdram operation. refer to function truth table in page 5. 20 MB81P643287-50/-60 preliminary (ae1e) n functional description (continued) bank address (ba 0 to ba 2 ) the MB81P643287 has eight internal banks and each bank is organized as 256k words by 32-bit. bank selection by ba occurs at bank active command (actv) followed by read (read or reada), write (writ or writa), and precharge(pre) command. address inputs (a 0 to a 10 ) address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix within each bank. a total of twenty address input signals are required to decode such a matrix. ddr sdram adopts an address multiplexer in order to reduce the pin count of the address line. at a bank active command (actv), eleven row addresses are initially latched as well as three bank addresses and the remainder of seven column addresses are then latched by a column address strobe command of either a read command (read or reada) or write command (writ or writa). data strobe (dqs 0 to dqs 3 ) dqs 0 to dqs 3 are bi-directional signal and represent byte 0 to byte 3, respectively. during read operation, dqs 0 to dqs 3 provides the read data strobe signal that is intended to use input data strobe signal at the receiver circuit of the controller(s). it turns low before first data is coming out and toggle high to low or low to high till end of burst read. refer to figure 3 for the timing example. the cas latency is specified to the first low to high transition of these dqs 0 to dqs 3 output. during the write operation, dqs 0 to dqs 3 are used to latch write data and data mask signals. as well as the behavior of read data strobe, the first rising edge of dqs 0 to dqs 3 input latches first input data and following falling edge of dqs 0 to dqs 3 signal latches second input data. this sequence shall be continued till end of burst count. therefore, dqs 0 to dqs 3 must be provided from controller that drives write data. note that dqs 0 to dqs 3 input signal should not be tristated from high at the end of write mode. data inputs and outputs (dq 0 to dq 31 ) input data is latched by dqs 0 to dqs 3 input signal and written into memory at the clock following the write command input. output data is obtained together with dqs 0 to dqs 3 output signals at programmed read cas latency. the polarity of the output data is identical to that of the input. data is valid after dqs 0 to dqs 3 output signal transitions (t qsq ) as specified in data valid time (t dv ). write data mask (dm 0 to dm 3 ) dm 0 to dm 3 are active high enable inputs and represent byte 0 to byte 3 respectively. dm 0 to dm 3 have a data input mask function, and are also sampled by dqs 0 to dqs 3 input signal together with input data. during write cycle, dm 0 to dm 3 provide byte mask function. when dmx = high is latched by a dqs 0 to dqs 3 signal edge, data input at the same edge of dqs 0 to dqs 3 is masked. during read cycle, all dm 0 to dm 3 are inactive and do not have any effect on read operation. refer to dm 0 to dm 3 truth table in page 6. 21 MB81P643287-50/-60 preliminary (ae1e) n functional description (continued) burst mode operation and burst type the burst mode provides faster memory access and MB81P643287 read and write operations are burst oriented. the burst mode is implemented by keeping the same row address and by automatic strobing column address in every single clock edge till programmed burst length(bl). access time of burst mode is specified as t acc . the internal column address counter operation is determined by a mode register which defines burst type(bt) and burst count length(bl) of 2, 4 or 8 bits of boundary. in order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 2, the following combinations will be required. the burst type is sequential only. the sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to the least significant address(= 0). if the first access of column address is even (0), the next address will be odd (1), or vice-versa. current stage next stage method (assert the following command) burst read burst read read command burst read burst write 1st step burst stop command (bst) 2nd step write command after l bsnc burst write burst write write command burst write burst read 1st step data mask input 2nd step read command after l wrd from last data input burst read precharge precharge command burst write precharge 1st step data mask input 2nd step precharge command after l dpl from last data input burst length starting column address a 2 a 1 a 0 sequential mode 2 x x 0 0 C 1 x x 1 1 C 0 4 x 0 0 0 C 1 C 2 C 3 x 0 1 1 C 2 C 3 C 0 x 1 0 2 C 3 C 0 C 1 x 1 1 3 C 0 C 1 C 2 8 0 0 0 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 0 0 1 1 C 2 C 3 C 4 C 5 C 6 C 7 C 0 0 1 0 2 C 3 C 4 C 5 C 6 C 7 C 0 C 1 0 1 1 3 C 4 C 5 C 6 C 7 C 0 C 1 C 2 1 0 0 4 C 5 C 6 C 7 C 0 C 1 C 2 C 3 1 0 1 5 C 6 C 7 C 0 C 1 C 2 C 3 C 4 1 1 0 6 C 7 C 0 C 1 C 2 C 3 C 4 C 5 1 1 1 7 C 0 C 1 C 2 C 3 C 4 C 5 C 6 22 MB81P643287-50/-60 preliminary (ae1e) n functional description (continued) burst stop command (bst) the burst stop command (bst) terminates the burst read operation except for a case that auto-precharge option is asserted. when the bst command is issued during the burst read operation, the all output buffers, dqs and dqs 0 to dqs 3 , will turn to high-z state after some latencies that to be matched with programmed cas latency and internal bank state remains active state. in a case of terminating the burst write operation, the bst command should not be issued at any time during burst write operation . refer to previous page for the write interrupt and termination rule. precharge and precharge option (pre, pall) the ddr sdram memory core is the same as conventional drams, requiring precharge and refresh operations. precharge rewrites the bit line and to reset the internal row address line and is executed by the precharge operation (pre or pall). with the precharge operation, ddr sdram will automatically be in standby state after specified precharge time (l rp , l rpa ). the precharged bank is selected by combination of ap and bank address (ba) when precharge command is issued. if ap = high, all banks are precharged regardless of ba (pall command). if ap = low, a bank to be selected by ba is precharged (pre command). the auto-precharge enters precharge mode at the end of burst mode of read or write without precharge command issue. this auto-precharge is entered by ap = high when a read (read) or write (writ) command is issued. applying bst is illegal if the auto-precharge option is used. refer to function truth table. auto-refresh (ref) auto-refresh uses the internal refresh address counter. the MB81P643287 auto-refresh command (ref) automat- ically generates bank active and precharge command internally. all banks of sdram should be precharged prior to the auto-refresh command. the auto-refresh command should also be issued within every 8 m s period. self-refresh entry (self) self-refresh function provides automatic refresh by an internal timer as well as auto-refresh and will continue the refresh operation until cancelled by selfx. the self-refresh mode is entered by applying an auto-refresh command in conjunction with cke = low (self). once MB81P643287 enters the self-refresh mode, all inputs except for cke can be either logic high or low level state and outputs will be in a high-z state. during self-refresh mode, cke = low should be maintained. self command should only be issued after last read data has been appeared on dq. note: when the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted prior to the self-refresh mode entry. self-refresh exit (selfx) to exit self-refresh mode, cke must bring to high for at least 2 clock cycles together with nop condition. refer to timing diagram for the detail procedure. it is recommended to issue at least one auto-refresh command just after the l rfc period to avoid the violation of refresh period. warning:a stable clock for l scd period with a constant duty cycle must be supplied prior to applying any read command to insure the dll is locked against the latest device conditions. note: when the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted both before the self-refresh entry and after the self-refresh exit. 23 MB81P643287-50/-60 preliminary (ae1e) n functional description (continued) mode register set (mrs) the mode register of sdram provides a variety of different operations. the register consists of four operation fields; burst length, burst type, cas latency, and test mode entry (this test mode entry must not be used). refer to mode register table in page 25. the mode register can be programmed by the mode register set command (mrs). each field is set by the address line. once a mode register is programmed, the contents of the register will be held until re-programmed by another mrs command (or part loses power). mrs command should only be issued on condition that all banks are in idle state and all dqs are in high-z. the condition of the mode register is undefined after the power-up stage. it is required to set each field at power-up initialization. refer to power-up initialization below. note: the extended mode register set command (emrs) and its dll enable function of emrs field is only used at power-on sequence. power-up initialization the MB81P643287 internal condition at and after power-up will be undefined. it is required to follow the following power on sequence to execute read or write operation. 1. apply v dd voltage to all v dd pins before or at the same time as v ddq pins and attempt to maintain all input signals to be low state (or at least cke to be low state). 2. apply v dd voltage to all v ddq pins before or at the same time as v ref and v tt . 3. apply v ref and v tt . (v tt is applied to the system). 4. start clock after all power supplies reached in a specified operating range and maintain stable condition for a minimum of 200us. 5. after the minimum of 200us stable power and clock, apply nop condition and take cke to be high state. 6. issue precharge all banks (pall) command or precharge single bank (pre) command to every banks. 7. issue emrs to enable dll, de = low. 8. issue mode register set command (mrs) to reset dll, dr = high. an additional clock input for l pcd * 1 period is required to lock the dll. 9. apply minimum of two auto-refresh command (ref).* 2 10. program the mode register by mode register set command (mrs) with dr = low.* 2 notes: *1. the l pcd depends on operating clock period. the l pcd is counted from dll reset at step-8 to any command input at step-10. *2. the mode register set command (mrs) can be issued before two auto-refresh cycle. power-down the MB81P643287 uses multiple power supply voltage. it is required to follow the reversed sequence of above power on sequence. 1. take all input signals to be v ss or high-z. 2. deapply v ddq . 3. deapply v dd at the same time as v ddq . 24 MB81P643287-50/-60 preliminary (ae1e) n functional description (continued) fig. 3 C sdram read timing example (@ cl=2 & bl=2) clk (external) data command read 25 MB81P643287-50/-60 preliminary (ae1e) n mode register table mode register set address ba 2 ba 1 ba 0 a 10 a 9 a 8 a 7 a 6 - a 4 a 3 a 2 - a 0 register 0 *1 0 *1 0 *1 0 0 dr te cl bt bl a 6 a 5 a 4 cas latency (cl) 0 0 x reserved 010 2 011 3 100 reserved 101 reserved 110 reserved 111 reserved a 2 a 1 a 0 burst length (bl) 000 reserved 001 2 010 4 011 8 1 x x reserved a 7 test mode entry (te) 0 normal operation 1 test mode (used for supplier test mode) a 3 burst type (bt) 0 sequential (wrap round, binary up) 1 reserved a 8 dll reset (dr) 0 normal operation 1 reset dll extended mode register set (note *4) notes: *1. a combination of ba 2 = ba 1 = ba 0 = 0 (low) selects standard mode register. *2. a combination of ba 1-2 = 0 and ba 0 = 1 (high) selects extended mode register. *3. these reserved field in emrs must be set as 0. address ba 2 ba 1 ba 0 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 extended mode register 0 *2 0 *2 1 *2 reserved *3 de a 0 dll enable (de) 0 dll enable 1dll disable 26 MB81P643287-50/-60 preliminary (ae1e) n absolute maximum ratings (see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions (referenced to v ss ) parameter symbol value unit voltage of v dd supply relative to v ss v dd , v ddq C0.5 to +3.6 v voltage at any pin relative to v ss v in , v out C0.5 to +3.6 v short circuit output current i out 50 ma power dissipation p d 2.0 w storage temperature t stg C55 to +125 c parameter notes symbol min. typ. max. unit supply voltage v dd 2.3 2.5 2.7 v v ddq v dd v dd v dd v v ss , v ssq 000v input reference voltage *1 v ref v ddq * 0.49 v ddq * 0.5 v ddq * 0.51 v termination voltage *2 v tt v ref - 0.04 v ref v ref + 0.04 v single ended sstl dc level input high voltage *3 v ih (dc) v ref + 0.25 v ddq + 0.1 v single ended sstl dc level input low voltage *3 v il (dc) - 0.1 v ref - 0.25 v single ended sstl ac level input high voltage *3 v ih (ac) v ref + 0.35 v single ended sstl ac level input low voltage *3 v il (ac) v ref - 0.35 v differential dc level input voltage range *3 v in (dc) - 0.1 v ddq + 0.1 v differential dc level differential input voltage *3 v swing (dc) 0.5 v ddq + 0.2 v differential ac level differential input voltage *3 v swing (ac) 0.7 v differential ac level input crosspoint voltage *3 v x (ac) v ddq /2 - 0.2 v ddq /2 v ddq /2 + 0.2 v differential input signal offset voltage *4 v iso (ac) v ddq /2 - 0.2 v ddq /2 v ddq /2 + 0.2 v termination resistor (sstl i/os) *2 r t 50 w ambient temperature t a 070 o c note 6. v dd + 1.0v vih vil pulse width 4 ns note 5. 50% of pulse amplitude vih vil -1.0v 50% of pulse amplitude pulse width 4 ns vih min vil max 27 MB81P643287-50/-60 preliminary (ae1e) n recommended operating conditions (continued) notes: *1. v ref is expected to track variations in the dc level of v ddq of the transmitting device. peak-to-peak noise level on v ref may not exceed +/- 2% of the supplied dc value. *2. v tt is used for sstl_2 bus and is not applied to the device. v tt is expected to be set equal to v ref and must be track variations in the dc level of v ref . *3. applicable when signal(s) is terminated to the v tt of sstl_2 bus. *4. v iso means {v in(clk) + v in(clk ) } / 2. refer to differential input signal definition. *5. overshoot limit: v ih (max) = v dd + 1.0v for pulse width <= 4 ns acceptable, pulse width measured at 50% of pulse amplitude. *6. undershoot limit: v il (min) = v dd -1.0v for pulse width <= 4 ns acceptable, pulse width measured at 50%of pulse amplitude. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. differential input signal definition n capacitance (t a = 25 c, f = 1 mhz) parameter symbol min. typ. max. unit input capacitance, address & control c in1 2.5 3.5 pf input capacitance, clk & clk c in2 2.5 3.5 pf input capacitance, dm 0 to dm 3 c in3 4.0 5.5 pf i/o capacitance c i/o 4.0 5.5 pf fig. 4 C differential input signal offset voltage (for clock input) v iso (max.) v iso (min.) clk v swing(ac) v x clk v ss |v swing | 0v differential v iso v ss 28 MB81P643287-50/-60 preliminary (ae1e) n dc characteristics (at recommended operating conditions unless otherwise noted.) note *1,*2,*3 (continued) parameter symbol condition value unit min. max. output minimum source dc current i oh(dc) v ddq = 2.3v, v oh = v ddq -0.43v -15.2 ma output minimum sink dc current i ol(dc) v ddq = 2.3v, v ol = +0.35v 15.2 ma input leakage current (any input) i li 0 v v in v dd ; all other pins not under test = 0 v -10 10 ua output leakage current i lo 0 v v in v dd ; data out disabled -10 10 ua v ref current i ref -10 10 ua operating current (average power supply current) MB81P643287-50 i dd1s burst length = 2 t ck = min, one bank active, address change up to 3 times during l rc (min) 0 v v in v il (max), v ih (min) v in v dd 460 ma MB81P643287-60 405 standby current MB81P643287-50 i dd2n cke = v ih , t ck = min all banks idle, nop commands only, input signals (except to cmd) are changed one time during 20 ns 0 v v in v il (max), v ih (min) v in v dd 85 ma MB81P643287-60 75 power down current i dd2p cke = v il , t ck = min all banks idle, 0 v v in v dd 35ma active standby current (power supply current) MB81P643287-50 i dd3n cke = v ih , t ck = min all banks active, nop commands only, input signals (except to cmd) are changed one time during 20 ns 0 v v in v il (max), v ih (min) v in v dd 260 ma MB81P643287-60 225 29 MB81P643287-50/-60 preliminary (ae1e) (continued) notes: *1. all voltages referenced to v ss . *2. dc characteristics are measured after following the power-up initialization procedure. *3. i dd depends on the output termination or load conditions, clock cycle rate, and number of address and command change within certain period. the specified values are obtained with the output open. parameter symbol condition value unit min. max. bust read current (average power supply current) MB81P643287-50 i dd4r burst length = 4, cas latency = 3, all bank active, gapless data, t ck = min, 0 v v in v il (max), v ih (min) v in v dd 535 ma MB81P643287-60 460 bust write current (average power supply current) MB81P643287-50 i dd4w burst length = 4, cas latency = 3, all bank active, gapless data, t ck = min, 0 v v in v il (max), v ih (min) v in v dd 595 ma MB81P643287-60 505 auto-refresh current (average power supply current) MB81P643287-50 i dd5 auto-refresh; t ck = min, 0 v v in v il (max), v ih (min) v in v dd 320 ma MB81P643287-60 270 self-refresh current (average power supply current) i dd6 self-refresh; cke = v il , 0 v v in v dd 5ma 30 MB81P643287-50/-60 preliminary (ae1e) n ac characteristics (recommended operating conditions unless otherwise noted.) note *1,*2,*3 ac parameters (cas latency dependent) parameter symbol MB81P643287-50 MB81P643287-60 unit min. max. min. max. clock period t ck cl = 3 5.0 9.0 6.0 10.5 ns cl = 2 7.5 10.5 9.0 10.5 parameter notes symbol MB81P643287-50 MB81P643287-60 unit min. max. min. max. input setup time (except for dqs, dm and dqs) *4 t is 1.0 1.2 ns input hold time (except for dqs, dm and dqs) *4 t ih 1.0 1.2 ns dm and data input setup time *5 t ds 0.6 0.7 ns dm and data input hold time *5 t dh 0.6 0.7 ns dqs first input setup time (input preamble setup time) *6 t dspres 00ns last data output to cke high level hold time t qckeh 00ns input transition time *7 t t 0.1 0.8 0.1 0.9 ns precharge power down exit and self-refresh exit time *4 t pdex 3.0 3.6 ns time between refresh *8 t ref 3232ms time between auto-refresh command *8 t aref 8.0 8.0 us pause time after power-on t pause 200 200 us 31 MB81P643287-50/-60 preliminary (ae1e) n ac characteristics (continued) ac parameters (frequency dependant) note *9 parameter notes symbol min. max. unit clock high time *4 t ch 0.45 * t ck ns clock low time *4 t cl 0.45 * t ck ns dqs low to high input transition setup time from clk *4, *10 t dqss 0.75 * t ck 1.25 * t ck ns dqs low input pulse width t dsl 0.4 * t ck ns dqs high input pulse width t dsh 0.4 * t ck ns dqs first low input hold time (input preamble hold time) *4 t dspreh 0.25 * t ck ns dqs first low input pulse width (input preamble pulse width) t dspre 0.4 * t ck ns dqs last low input hold time (input postamble hold time) t dspst 0.4 * t ck ns dqs access time from clock *4 t qsck - 0.1 * t ck - 0.2 0.1 * t ck + 0.2 ns dqs output valid time t qsv 0.3 * t ck ns dqs output in low-z (output preamble setup time) *4, *11 t qslz - 0.1 * t ck - 0.2 ns dqs first low output hold time (output preamble hold time) *4 t qspre 0.9 * t ck - 0.2 1.1 * t ck + 0.2 ns dqs last low output hold time (output postamble hold time) *4, *12 t qspst 0.4 * t ck - 0.2 0.6 * t ck + 0.2 ns dqs last low output in high-z from clk or clk *12 t qshz 0.1 * t ck + 0.2 ns dq access time from clk & clk *4 t acc - 0.1 * t ck - 0.2 0.1 * t ck + 0.2 ns dq access time from dqs *5 t qsq - 0.1 * t ck 0.1 * t ck ns dq output data valid time from dqs t dv 0.3 * t ck ns dq output in low-z *4, *11 t lz - 0.1 * t ck - 0.2 ns dq output in high-z *4, *12 t hz - 0.1 * t ck - 0.2 0.1 * t ck + 0.2 ns dq & dm input pulse width t dipw 0.4 * t ck ns dqs falling edge to clock hold time t dsch 0.2 * t ck (1.5 ns min.) ns dqs falling edge to clock setup time t dscs 0.2 * t ck (1.5 ns min.) ns 32 MB81P643287-50/-60 preliminary (ae1e) n ac characteristics (continued) example of frequency dependant ac parameters (@ minimum t ck ) parameter symbol t ck = 5ns t ck = 6ns t ck = 7.5ns t ck = 9ns t ck = 10.5ns unit min. max. min. max. min. max. min. max. min. max. clock high time t ch 2.3 2.7 3.4 4.1 4.8 ns clock low time t cl 2.3 2.7 3.4 4.1 4.8 ns dqs low to high input transition setup time from clk t dqss 3.8 6.3 4.5 7.5 5.7 9.4 6.8 11.3 7.9 13.2 ns dqs low input pulse width t dsl 2.0 2.4 3.0 3.6 4.2 ns dqs high input pulse width t dsh 2.0 2.4 3.0 3.6 4.2 ns dqs first low input hold time (input preamble hold time) t dspreh 1.3 1.5 1.9 2.3 2.7 ns dqs first low input pulse width (input preamble pulse width) t dspre 2.0 2.4 3.0 3.6 4.2 ns dqs last low input hold time (postamble hold time) t dspst 2.0 2.4 3.0 3.6 4.2 ns dqs access time from clock t qsck -0.7 0.7 -0.8 0.8 -1.0 1.0 -1.1 1.1 -1.3 1.3 ns dqs output valid time t qsv 1.5 1.8 2.3 2.7 3.2 ns dqs output in low-z (output preamble) t qslz -0.7 -0.8 -1.0 -1.1 -1.3 ns dqs first low output hold time (output preamble) t qspre 4.3 5.7 5.2 6.8 6.6 8.5 7.9 10.1 9.3 11.8 ns dqs last low output hold time (output postamble) t qspst 1.8 3.2 2.2 3.8 2.8 4.7 3.4 5.6 4.0 6.5 ns dqs last low output in high-z from clk or clk t qshz 0.70.81.01.1 1.3 ns dq output access time from clk & clk t acc -0.7 0.7 -0.8 0.8 -1.0 1.0 -1.1 1.1 -1.3 1.3 ns dq output access time from dqs t qsq -0.5 0.5 -0.6 0.6 -0.8 0.8 -0.9 0.9 -1.1 1.1 ns dq output data valid time from dqs t dv 1.5 1.8 2.3 2.7 3.2 ns dq output in low-z t lz -0.7 -0.8 -1.0 -1.1 -1.3 ns dq output in high-z t hz -0.7 0.7 -0.8 0.8 -1.0 1.0 -1.1 1.1 -1.3 1.3 ns dq & dm input pulse width t dipw 2.0 2.4 3.0 3.6 4.2 ns dqs falling edge to clock hold time t dsch 1.5 1.5 1.5 1.8 2.1 ns dqs falling edge to clock setup time t dscs 1.5 1.5 1.5 1.8 2.1 ns 33 MB81P643287-50/-60 preliminary (ae1e) n ac characteristics (continued) latency (the latency values on these parameters are fixed regardless of clock period.) parameter notes symbol MB81P643287-50 MB81P643287-60 unit min. max. min. max. ras cycle time *13 cl = 3 l rc 66t ck cl = 2 5 5 t ck ras active time cl = 3 l ras 4 11000 4 11000 t ck cl = 2 3 7333 3 7333 t ck ras precharge time l rp 22t ck ras to cas delay time cl = 3 l rcd 33t ck cl = 2 2 2 t ck ras to ras bank active delay time l rrd 11t ck precharge all bank to active cl = 3 l rpa 44t ck cl = 2 3 3 t ck read command to write command delay cl = 3 l rwd bl/2+3 bl/2+3 t ck cl = 2 bl/2+2 bl/2+2 t ck last input data to read command *14 delay l wrd 2.5 2.5 t ck last input data to precharge command lead time *14 l dpl 2.5 2.5 t ck write with auto precharge command to active command delay *14 l wal bl/2+3+l rp bl/2+3+l rp t ck mode register access to next command input delay l mrd 22t ck cas to cas delay l ccd 11t ck cas bank delay l cbd 11t ck precharge power down exit to next command input delay l pdexp 22t ck minimum stable clock input after self- *15 refresh exit before read command input l scd 400 400 t ck minimum stable clock input after self- refresh exit before non-read command input l xsnr 12 12 t ck minimum stable clock input for dll lock-on in power-up initialization sequence. *16 t ck 7.5ns l pcd 400 400 t ck t ck 10.5ns 630 630 t ck auto-refresh cycle time l rfc 12 12 t ck 34 MB81P643287-50/-60 preliminary (ae1e) n ac characteristics (continued) latency - fixed values (the latency values on these parameters are fixed regardless of clock period.) parameter notes symbol MB81P643287-50 MB81P643287-60 unit bst command to output in high-z cl = 3 l bsh 33t ck cl = 2 2 2 t ck bst command to new command input *17 cl = 3 l bsnc 33t ck cl = 2 2 2 t ck dm to input data delay l dqd 00t ck precharge to output in high-z cl = 3 l roh 33t ck cl = 2 2 2 t ck cke low to command/address input inactive l cke 11t ck 35 MB81P643287-50/-60 preliminary (ae1e) n ac characteristics (continued) notes: *1. ac characteristics are measured after following the power-up initialization procedure and stable clock input with constant clock period and with 50% duty cycle. *2. access times assume input slew rate of 1ns/volt between v ref +0.35v to v ref -0.35v, where v ref is v ddq /2, with sstl_2 output load conditions. refer to ac test load circuit in page 35. *3. v ref = 1.25v is a typical reference level for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) unless otherwise noted. refer to ac test conditions in page 35. *4. this parameter is measured from the cross point of clk and clk input. *5. this parameter is measured from signal transition point of dqs 0-3 input crossing v ref level. *6. the specific requirement is that dqs be valid (high or low) on or before this clk edge. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on t dss . *7. t t is defined as the transition time between v ih (ac) (min) and v il (ac) (max). *8. total of 4096 ref command must be issued within t ref (max). t aref is a reference value for distributed refresh and specifies the time between one ref command to next ref command except for a condition where cke = low during self-refresh mode. *9. frequency dependent ac parameters are scalable by actual clock period (t ck ) and affected by an abrupt change of duty cycle, jitters on clock input, t a and level of v dd and v ddq . the internal dll circuit can adjust delay time to change and following level change of v dd and v ddq , (change rate of t a 0.1 c / 20 ns, change rate of v dd and v ddq , 1mv / 10 ns. if change rate is bigger than these value, frequency dependent ac parameters affected by jitters causing by these change.) *10. more than 2 signal edge of dqs 0-3 should not be input within 1 clock (t ck ) cycle. *11. low-z (low impedance state) is specified and measured at v tt +/- 200mv. *12. t qspst , t qshz and t hz are specified where output buffer is no longer driven. *13. actual clock count of l rc will be sum of clock count of l ras and l rp . *14. assume t dqss = 1* t ck . if actual t dqss is within specified minimum and maximum range, those parameters can be assumed t dqss = 1* t ck . *15. applicable also if device operating conditions such as supply voltages, case temperature, and/or clock frequency (t ck difference must be 0.2 ns or less) is changed during any operation. *16. clock period must satisfy specified t ck and it must be stable. *17. assume bst is effective to read operation (issued prior to the end of burst read). 36 MB81P643287-50/-60 preliminary (ae1e) n ac characteristics (continued) ac test condition s v x means the actual cross point between clk and clk input. parameters symbol value unit single-end input input high level v ih v ref + 0.35 v input low level v il v ref - 0.35 v input reference level v ref v ddq / 2 v input slew rate slew 1.0 v/ns differential input (clk and clk ) input reference level vr v x (ac) v input level v swing 0.7 v input slew rate slew 1.0 v/ns output v ddq v ref device under te s t note: ac characteristics are measured in this condition. this load circuit is not applicable for dc test. fig. 5 C ac test load circuit (sstl_2, class ii) r t2 = 50 w cl = 20 pf v ref = 0.5 v ddq z 0 = 50 w output measure- ment point r s = 25 w r t1 = 50 w v tt = 0.5 v ddq v tt = 0.5 v ddq v ddq 0.5 v ddq v ss 37 MB81P643287-50/-60 preliminary (ae1e) n ac characteristics (continued) note: reference level for ac timings of clock are the cross point of clk and clk as specified in v x . fig. 6 C ac timing of clk & clk t cl t ck t ch clk v swing(ac) v x clk t is t ih input (controls & addresses) fig. 7 C ac timing of command input & address v ref input valid v ih (ac) v il (ac) t ck v x clk note: the cross point of clk and clk (v x ) is used for command and address input. the reference level of single ended input is v ref . clk input (data&dm) fig. 8 C ac timing of write mode (data strobe, write data and data mask input) t ds t dh t ds t dh v ref v il dqs input (@bl=4) input valid input valid t ck t ck clk clk t is t ih input (controls & addresses) v ref write command v ih (ac) v il (ac) t dsh t dsh v ref t ds t dh t ds t dh input valid input valid t dspst t dspres t dspreh t dsl t dqss t dspre t dqss t dscs t dsch t dipw t dipw t dipw t dipw 38 MB81P643287-50/-60 preliminary (ae1e) n ac characteristics (continued) note: dqs access time (t qsck ) is measured from the cross point of clock (v x ) and v ref . the end of t qspst and t qshz specification is defined at where output buffer is no longer driven. fig. 9 C ac timing of read mode (clock to dqs output delay time) t qshz v tt v tt - 0.2 v dqs output (@bl=4) t qsck (min) t qsv t ck v x clk clk t qspst t qspre t qsck (max) t qsv t qsv t qsck (min) t qsck (max) t qsck (min) t qsck (max) t qsck (min) t qsck (max) t ck t qslz (min) dq data output (@bl=4) v tt note: access time (t acc ) is measured from the cross point of clock (v x ) and v ref . the end of t hz specification is defined at where output buffer is no longer driven. fig. 10 C ac timing of read mode (clock to data output delay time) v tt + 0.2 v v tt - 0.2 v t ck v x clk clk t hz t acc (min) t lz (min) t acc (max) t ck t acc (min) t acc (max) t acc (min) t acc (max) t acc (min) t acc (max) dq data output (@bl=4) v tt note: dqs output edge to data output edge skew time (t qsq ) is measured from v tt to v tt . fig. 11 C ac timing of read mode (dqs output to data output delay time) v tt + 0.2 v v tt - 0.2 v v ref dqs output (@bl=4) t qsq (min) t dv t qsq (max) t qsq (min) t qsq (max) t qsq (min) t qsq (max) t qsq (min) t qsq (max) t dv t dv t dv 39 MB81P643287-50/-60 preliminary (ae1e) n ac characteristics (continued) fig. 12 C ac timing, pulse width l ras , l rp , l rpa , l rcd , l rrd , t ref , t aref clk input (controls & addresses) note: all parameters listed above are measured from the cross point at rising edge of the clk and falling edge of clk of one command input to next command input. command command clk v x v x cke clk t is command l pdexp (min) *2 nop actv fig. 13 C ac timing of precharge power down mode nop nop dont care t pdex l rc (min), t ref (max) clk notes: *1. minimum 2 clock cycles is required for complete power down on clock buffer. *2. if either any supply voltage or clock input condition is changed from the previous operating condition (other than pden and ref), l scd must be satisfied prior to any command input. v ref l cke nop nop self cke clk t is command l scd *3 or l xsnr actv fig. 14 C ac timing of self-refresh mode nop nop dont care t pdex clk notes: *1. minimum 2 clock cycles is required for complete power down on clock buffer. *2. cke must maintain high level and clock must be provided during the l scd period. l scd must be satisfied before read command input. *3. l scd must be satisfied before read command input. v ref note *1 l rfc (min) *2 l cke nop nop 40 MB81P643287-50/-60 preliminary (ae1e) n timing diagrams timing diagram C 1 : column address to column address input delay clk ras cas i ccd (min) note: l ccd , cas to cas address delay, is applicable to the same bank access and it can be one or more clock period. i ccd i ccd i ccd row address column address address column address column address column address column address l rcd (min) clk timing diagram C 2 : different bank address input delay i cbd i cbd ba 0,1 l rcd (min) l rrd (min) l rcd(min ) row address row address column address column address column address column address clk ras cas address clk bank 0 bank 1 bank 1 bank 2 bank 3 bank 0 i cbd i cbd (min) 41 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 3 : read (example @ bl = 4) command note: cas latency is defined from read command to first rising edge of dqs0-3 output. preamble is 1*t ck length and starts driving low level. read l ccd (min) clk clk read hi-z cas latency preamble cas latency q1 hi-z hi-z q2 q3 q4 q1 q2 cas latency preamble cas latency dqs (output) @cl=2 dq 0-31 (output) @cl=3 dqs (output) @cl=3 cke nop q1 hi-z q2 q3 q4 q1 q2 dq 0-31 (output) @cl=2 high 42 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 4 : write (example @ bl = 4) note: dqs setup time, t dqss , must be within a range of 0.75*t ck to 1.25*t ck from write command input. command writ clk clk writ d1 dq 0-31 (input) dqs (input) dont care d2 d3 d4 d1 d2 t dqss t dqss dont care dont care t dspre cke t dspres t dspreh l ccd (min) dont care nop high timing diagram C 5 : dm, write data mask (example @ bl = 4) note: dm are latched by dqs input together with data input after write command. command writ clk clk writ dq 0-31 (input) dqs (input) dont care masked t dqss t dqss l dqd = 0 dont care dont care l dqd = 0 d1 dm dont care d2 d3 d4 d1 - - d4 dont care dont care nop nop masked 43 MB81P643287-50/-60 preliminary (ae1e) actv l rp (min) timing diagram C 6 : read with auto-precharge (example @ cl = 2.0, bl = 4 applied to same bank) l ras (min) bl/2 * t ck + l rp (see note) command l rcd (min) clk clk dqs (output) hi-z reada q1 dq 0-31 (output) hi-z q2 actv cas latency q3 q4 note: internal precharge operation at read with auto-precharge command (reada) is started bl/2 clock later from reada command. if bl=2, the reada command should not be issued no earlier than 1 clock (bl/2 = 1) before l ras (min). if bl=4, the reada command should not be issued no earlier than 2 clock (bl/2=2) before l ras (min). l wal (min) timing diagram C 7 : write with auto-precharge (example @ cl = 2.0, bl = 4 applied to same bank) note: write with auto-precharge command (writa) must be issued after l rcd is satisfied and be considered to meet l ras requirement applied to end of burst length (bl) regardless of where it is masked or not. l ras (min) (see note) command l rcd (min) clk clk dqs (input) hi-z writa d1 dq 0-31 (input) hi-z d2 actv t dqss d3 d4 actv 44 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 8 : read interrupted by precharge (example @ cl = 2, bl = 8) note: l roh is the same as cas latency (cl). in case of cl =3, the l roh is 3 clock. clk clk nop command pre read dqs (output) hi-z q1 dq 0-31 (output) hi-z q2 l roh ( = cas latency) command pre read dqs (output) hi-z q1 dq 0-31 (output) hi-z q2 l roh ( = cas latency) q3 q4 command pre read hi-z q1 dq 0-31 (output) hi-z q2 l roh ( = cas latency) q3 q4 q5 q6 command pre read dqs (output) hi-z q1 dq 0-31 (output) hi-z q2 no effect (end of burst) q3 q4 q5 q6 q7 q8 nop nop nop nop nop nop dqs (output) 45 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 9 : read interrupted by burst stop (example @ cl = 2, bl = 8) note: l bsh is the same as cas latency (cl). in case of cl =3, the l bsh is 3 clock. clk clk nop command bst read dqs (output) hi-z q1 dq 0-31 (output) hi-z q2 l bsh ( = cas latency) command bst read dqs (output) hi-z q1 dq 0-31 (output) hi-z q2 l bsh ( = cas latency) q3 q4 command bst read dqs (output) hi-z q1 dq 0-31 (output) hi-z q2 l bsh ( = cas latency) q3 q4 q5 q6 command bst read hi-z q1 dq 0-31 (output) hi-z q2 no effect (end of burst) q3 q4 q5 q6 q7 q8 nop nop nop nop nop nop dqs (output) 46 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 10 : write interrupted by precharge (example @ cl = 2, bl = 8) note: 1. dqs input are not required from when precharge command is issued. 2. this pair of write data must be masked prior to precharge command. command writ clk clk pre dq 0-31 (input) dont care see note 2. l dpl (min) t dqss dont care dont care d1 dont care d2 - - dont care dont care nop see note 1. actv l rp (min) nop dm dqs (input) - - timing diagram C 11 : read to write (example @ cl = 2, bl = 4) note: l rwd defines a minimum delay from read to write command input applied to the same bank. command read clk clk writ dq 0-31 t dqss cl hi-z q1 hi-z q2 d3 d4 d1 d2 nop nop l rwd (min) i/o open for bus turn-around q3 q4 dm dqs dont care 47 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 12 : read to write (example @ cl = 2, bl = 4) note: dm are latched by dqs input after write command together with data input. command read clk clk writ dq 0-31 dqs t dqss l bsh hi-z q1 hi-z q2 d3 d4 d1 d2 nop nop bst l bsnc terminated dm dont care q1 q2 timing diagram C 13 : write to read (example @ cl = 2, bl = 8) note: read command must be issued after l wrd is satisfied and proceeding pair of data must be masked. command writ clk clk read dq 0-31 dqs terminated by read t dqss l wrd hi-z dm hi-z d1 d2 nop nop masked cl dont care 48 MB81P643287-50/-60 preliminary (ae1e) read l rp (min) timing diagram C 14 : read with auto-precharge (example @ cl = 2, bl = 4, multiple bank operation) note: back to back read with auto-precharge (reada) command to the different bank in active state is possible. however, any new command to the same bank applied reada command can only be issued after bl/2*t ck +l rp . l rcd (min) command l rrd (min) clk clk dqs (output) hi-z pre q1 dq 0-31 (output) hi-z q2 reada l cbd q3 q4 reada ba 0 , ba 1 reada actv actv q1 q2 q1 q2 q3 q4 l cbd l cbd l cbd cas latency bl/2 * t ck + l rp bank 0 bank 1 bank 1 bank 2 bank 3 bank 1 bank 0 l cbd l wal (min) timing diagram C 15 : write with auto-precharge (example @ cl = 2, bl = 4, multiple bank operation) note: back to back write with auto-precharge (writa) command to the different bank in active state is possible. however, any new command to the same bank applied writa command can only be issued after l wal . command l cbd (min) clk clk dqs (input) writa d1 dq 0-31 (input) d2 writa t dqss d3 d4 actv ba 0 , ba 1 bank 0 bank 1 bank 0 pre writa bank 2 bank 3 l cbd (min) l cbd (min) d1 d2 d3 d4 d1 d2 t dqss t dqss actv bank 2 l rp (min) l rrd (min) 49 MB81P643287-50/-60 preliminary (ae1e) l rfc (min) timing diagram C 16 : auto-refresh entry and exit command clk clk any nop ref cke clk t is command l xsnr or l scd * nop actv timing diagram C 17 : self-refresh entry and exit self nop nop dont care t pdex clk note: cke must maintain high level and stable clock must be provided during the l scd period. after self-refresh exit, l xsnr must be satisfied for at least specified period before any command (except for read) input. t qckeh dqs (output) hi-z dq 0-31 (output) hi-z q last data output l rfc (min) clk l mrd command nop timing diagram C 18 : mode register set mrs clk note: mrs command must be issued after the last data is appeared on each dq. nop any 50 MB81P643287-50/-60 preliminary (ae1e) n scitt test mode about scitt scitt (static component interconnection test technology) is an xnor circuit based test technology that is used for testing interconnection between sdram and sdram controller on the printed circuit boards. scitt provides inexpensive board level test mode in combination with boundary-scan. the basic idea is simple, consider all output of sdram as output of xnor circuit and each output pin has a unique mapping on the input of sdram. the ideal schematic block diagram is as shown below. it is static and provides easy test pattern that result in a high diagnostic resolution for detecting all open/short faults. m c asic sdram controller test control xaddress bus data bus sdram core xnor boundary scan test control : cas, cs , cke xaddress bus : a 0 to a 10 , ba 0 to ba 2 , ras , dm 0 to dm 3 , clk, clk , we data bus : dq 0 to dq 31 , dqs 0 to dqs 3 51 MB81P643287-50/-60 preliminary (ae1e) scitt test sequence the followings are the scitt test sequence. scitt test can be executed after power-on and prior to precharge command in power-up initialization. once precharge command is issued to sdram, it never get back to scitt test mode during regular operation for the purpose of a fail-safe way in get in and out of test mode. 1. apply v dd voltage to all v dd pins before or at the same time as v ddq pins and attempt to maintain all input signals to be low state (or at least cke to be low state). 2. apply v dd votage to all v ddq pins before or at the same time as v ref and v tt . 3. apply v ref and v tt (v tt is applied to the system). 4. maintain stable power for a minimum of 100 m s. 5. enter scitt test mode. 6. execute scitt test. 7. exit from scitt mode. it is required to follow power on sequence to execute read or write operation. 8. start clock after all power supplies reached in a specified operating range and maintain stable condition for a minimum of 200 m s. 9. after the minimum of 200 m s stable power and clock, apply nop condition and take cke to be high state. 10.issue precharge all banks (pall) command or precharge single bank (pre) command to every banks. 11.issue emrs to enable dll, de = low. 12.issue mode register set command (mrs) to reset dll, dr = high. an additional clock input for l pdc * 1 period is required to lock the dll. 13.apply minimum of two auto-refresh command (ref).* 2 14.program the mode register by mode register set command (mrs) with dr = low.* 2 the 5,6,7 steps define the scitt mode available. it is possible to skip these steps if necessary (refer to power- up initialization). notes: *1. the l pcd depends on operating clock period. the l pcd is counted from dll reset at step-8 to any command input at step-10. *2. the mode register set command (mrs) can be issued before two auto-refresh cycle. command truth table note *1 notes: *1. l = logic low, h = logic high, v = valid, x = either l or h *2. the scitt mode entry command assumes the first cas falling edge with cs and cke = l after power on. *3. the scitt mode exit command assumes the first cas rising edge after the test mode entry. *4. refer the test code table. *5. cs = h or cke = l is necessary to disable outputs in scitt mode exit. control input output cas cs pd we ras a 0 to a 10 , ba 0 to ba 2 dm 0 to dm 3 clk, clk dq 0 to dq 31 dqs 0 to dqs 3 scitt mode entry h ? l * 2 llxx x x xxx scitt mode exit l ? h * 3 h *5 l *5 xx x xxxx scitt mode output enable * 4 l lhvv v vvvv 52 MB81P643287-50/-60 preliminary (ae1e) test code table dq 0 to dq 31 and dqs 0 to dqs 3 output data is static and is determined by following logic during the scitt mode operation. dq 0 = ras xnor a 0 dq 1 = ras xnor a 1 dq 2 = ras xnor a 2 dq 3 = ras xnor a 3 dq 4 = ras xnor a 4 dq 5 = ras xnor a 5 dq 6 = ras xnor a 6 dq 7 = ras xnor a 7 dq 8 = ras xnor a 8 dq 9 = ras xnor a 9 dq 10 = ras xnor a 10 dq 11 = ras xnor ba 1 dq 12 = ras xnor ba 0 dq 13 = ras xnor ba 2 dq 14 = ras xnor dm 0 dq 15 = ras xnor dm 1 dq 16 = ras xnor dm 2 dq 17 = ras xnor dm 3 dq 18 = ras xnor clk dq 19 = ras xnor clk dq 20 = ras xnor we dq 21 = a 0 xnor a 1 dq 22 = a 0 xnor a 2 dq 23 = a 0 xnor a 3 dq 24 = a 0 xnor a 4 dq 25 = a 0 xnor a 5 dq 26 = a 0 xnor a 6 dq 27 = a 0 xnor a 7 dq 28 = a 0 xnor a 8 dq 29 = a 0 xnor a 9 dq 30 = a 0 xnor a 10 dq 31 = a 0 xnor ba 0 dqs 0 = a 0 xnor ba 1 dqs 1 = a 0 xnor ba 2 dqs 2 = a 0 xnor dm 0 dqs 3 = a 0 xnor dm 1 ? example of test code table input bus output bus 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 h l l h h h h h h h h h h h h h h h h h h h h l l h h h h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h h h h l l h h h h h h h h h h h h h h h h h h h h l h h h l l h h h h h h h h h h h h h h h h h h h h l l h h h h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h l h h h h h h ras a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 ba 0 ba 1 ba 2 dm 0 dm 1 dm 2 dm 3 clk clk we dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 dqs 0 dqs 1 dqs 2 dqs 3 0 = input low, 1 = input high, l = output low, h = output high 53 MB81P643287-50/-60 preliminary (ae1e) ac specification timing diagrams parameter description minimum maximum units t ts test mode entry set up time 10 ns t th test mode entry hold time 10 ns t epd test mode exit to power on sequence delay time 10 ns t tlz test mode output in low-z time 0 ns t thz test mode output in high-z time 0 20 ns t tca test mode access time from control signals (output enable & chip select) 40ns t tia test mode input access time 20 ns t toh test mode output hold time 0 ns t etd test mode entry to test delay time 10 ns t tih test mode input hold time 30 ns timing diagram C 1 : power-up timing diagram v dd cs cke cas *3 100 m s pause time test mode entry point notes: *1. scitt is enabled if cs = l, cke = l, cas = l at just power on. *2. all output buffers maintains in high-z state regardless of the state of control signals as long as the above timing is maintained. *3. cas must not be brought from high to low. *2 *1 54 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 2 : scitt test entry and exit *1 t ts v cc cas cs cke t th entry exit pause 100 m s l l next power on sequence and normal operation h ? l notes: *1. if entry and exit operation have not been done correctly, cas , cs , cke pins will have some problems. *2. pre or pall commands must not be asserted. test mode is disable by those commands. *3. outputs must be disabled by cs = h or cke = l before exit. *2 *3 test mode t epd 55 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 3 : output control (1) v dd cas cs cke t tlz entry dq turn to low-z at cs =l and cke=h dq 0 to dq 31 dqs 0 to dqs 3 t thz dq turn to high-z at cs =h cas must not brought from high to low high-z high-z high-z low-z time (a) time (b) time (c) memory device output buffer status this is not bus line level timing diagram C 4 : output control (2) v dd cas cs cke t tlz entry dq turn to low-z at cs =l and cke=h dq 0 to dq 31 dqs 0 to dqs 3 t thz cas must not brought from high to low high-z high-z high-z low-z time (a) time (b) time (c) memory device output buffer status this is not bus line level dq turn to high-z at cke=l 56 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 5 : test timing (1) cs cke t etd test mode entry command test mode entry dq becomes low-z at cs =l and cke=h t tca t tia t tia t tia t tlz t toh t toh valid valid valid a 0 a 1 a 2 dq 0 to dq 31 dqs 0 to dqs 3 under check pins under test cas 57 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 6 : test timing (2) cs -#1 cke test mode entry t tia t toh valid a 0 a 1 a 2 dq 0 to dq 31 dqs 0 to dqs 3 under check pins test mode exit under test cas cs -#2 valid valid valid valid t tia t tia t toh t thz t tlz t tia t tca t tih t tia t toh t tih t tih tested #1 device tested #2 device changed under test devices l l h 58 MB81P643287-50/-60 preliminary (ae1e) timing diagram C 7 : test timing (3) cs -#1 cke test mode entry t tia t toh valid a 0 a 1 a 2 dq 0 to dq 31 dqs 0 to dqs 3 under check pins test mode exit under test cas cs -#2 valid valid valid valid t tia t tia t toh t thz t tlz t tia t tca t tih t tia t toh t tih t tih tested #1 device tested #2 device changed under test devices l l h 59 MB81P643287-50/-60 preliminary (ae1e) n package dimensions c 1996 fujitsu limited f86001s-1c-1 0.45/0.75 (.018/.030) 0~8? 0.25(.010) details of "a" part 86 44 43 1 lead no. index .009 .002 +.002 0.04 +0.05 0.22 m 0.10(.004) 22.22 0.10(.875 .004) * 0.50(.020)typ 0.10(.004) 21.00(.827)ref 0.10 0.05 (.004 .002) (stand off) 1.20(.047)max .006 .001 +.002 0.03 +0.05 0.145 10.16 0.10(.400 .004) 11.76 0.20(.463 .008) "a" dimensions in mm (inches) (mounting height) 86-pin plastic tsop (ii) (fpt-86p-m01) 60 MB81P643287-50/-60 preliminary (ae1e) fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3753 fax: (044) 754-3332 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f0003 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applica- tions, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume respon- sibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and office equipment industrial, communications, and measurement equipment, personal or household devices, etc.). important note: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high lives of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. there is a slight risk of failure with all semiconductor devices. you must protect against injury, damage to loss from such failures by incorporating safety design measures into your facility and equipment such as redun- dancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if the products described in this document represent goods or technologies subject to restrictions based on the foreign exchange and foreign trade control low, you must obtain permission to export these products. |
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