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ba7078af multimedia ics synchronization signal processor for high definition displays ba7078af the ba7078af is a synchronization signal processing lsi chip designed for multiscan high-definition displays. it generates a synchronization signal and clamp pulse for three types of input signals: separate synchronization, composite synchronization, and synchronization on video. ! ! ! ! application crt displays ! ! ! ! features 1) operates on a single 5v power supply, with low power consumption. 2) synchronization signal existence and polarity detec-tion output. 3) adjustable clamp pulse width, allowing for the selec-tion of front or back editing. 4) vertical synchronization separation is based on hori-zontal frequency tracking, for separation starting at 1h. 5) minimal attached components. ! ! ! ! absolute maximum ratings (ta = 25 c) parameter symbol limits unit v cc pd v mw c c power supply voltage power dissipation storage temperature operating temperature 7.0 450 ? 25 ~ + 75 ? 55 ~ + 125 ? reduced by 4.5mw for each increase in ta of 1 c over 25 c. topr tstg ! ! ! ! recommended operating conditions (ta = 25 c) parameter symbol min. typ. max. unit power supply voltage v cc 4.5 5.0 5.5 v
ba7078af multimedia ics ! ! ! ! block diagram 1 2 3 4 6 5 7 8 9 18 17 16 15 14 13 12 11 10 h sync det. sync sepa. v sync sepa. v sync det. clamp pulse gen. hor. sync control hsctl c / hsync in video in vsepa vsync in cvpol cvexi cpsel gnd polh exih polv exiv vcc hdrv clamp vdrv cpwid
ba7078af multimedia ics ! ! ! ! pin descriptions pin name pin no. 1 2 hsctl c / hsync in 3 video in 4 vsepa functions hdrv output sync on video input composite sync / h sync input used to select whether to output the vdrv section of the hdrv output signal. high : vdrv section of hdrv is output low : vdrv section of hdrv is not output input either the composite synchronization signal or the horizontal synchronization signal. input is clamped, and is initiated by capacitor coupling. inputs the sync on video signal(green). input is sink chip clamped. input is initiated by capacitor coupling. f-v conversion 5 vsync in v sync input converts the horizontal synchronization signal frequency into a voltage. the voltage generated is proportional to the frequency of the horizontal synchronization signal. attach a 0.56 f capacitor between the ground pins. inputs the vertical synchronization signal. 6 cvpol vertical polarity integration integrates the vertical synchronization signal polarity detection circuit. attach a 1.5 f capacitor between this pin and the ground. 7 cvexi vertical existence integration 8 cpsel setting the clamp position 9 gnd ground 10 cpwid setting the clamp pulse width 11 vdrv vdrv output integrates the vertical synchronization signal existence detection circuit. attach a 1 f capacitor between this pin and the ground. used to set the clamp pulse generation position to either the front or back edge of hsync high : the front edge is the generation position open : composite / h sync in : the front edge is the generation position video in : the back edge is the generation position low : the back edge is the generation position ? 14 v cc power supply ? sets the clamp pulse width according to the attached time constant. attach a resistor between this pin and v cc and, a capacitor between this pin and gnd. when r = 3.9k ? and c = 100pf, pulse width is approximately 400 ns. set the resistor to register an abnormality at 1k ? . outputs the vertical synchronization signal. the output signal has positive polarity. 13 hdrv hdrv output outputs the clamp pulse generated from the horizontal synchronization signal. the output signal has positive polarity. 15 exiv vertical existence output indecates whether the vertical synchronization signal exists. for the output logic, refer to the separate table. 16 polv vertical polarity output indicates the polarity of the vertical synchronization signal. for the output logic, refer to the separate table. 17 exih horizontal existence output indicates whether the horizontal synchronization signal exists. for the output logic, refer to the separate table. 18 polh horizontal polarity output indicates the polarity of the horizontal synchronization signal. for the output logic, refer to the separate table. 12 clamp clamp output outputs the clamp pulse generated from the vertical synchronization signal. the output signal has a positive polarity.
ba7078af multimedia ics ! ! ! ! input / output circuits 1pin v cc 51k ? 30k ? hsctl 4pin v cc 1k ? 60k ? vsepa 2pin v cc 670 ? 200 ? 10 a c / hsync in vsync in 5pin v cc 3pin v cc 200 ? 2k ? video in 6pin v cc 200 ? cvpol 7pin v cc cvexi 10pin v cc cpwid 8pin v cc 50k ? 1k ? 50k ? cpsel
ba7078af multimedia ics 11pin v cc vdrv 9pin gnd 12pin v cc clamp hdrv 13pin v cc 16pin v cc 10k ? polv 14pin v cc v cc 17pin v cc 10k ? exih 15pin v cc 10k ? exiv 18pin v cc 10k ? polh
ba7078af multimedia ics ! ! ! ! electrical characteristics (unless otherwise noted, v cc = 5v, ta = 25 c) parameter power supply voltage v ma v v ns ma ma ns vsync in c / hsync in video in front edge back edge ns v v v v ma ns ns v v ma v v v v k ? v p-p 5.5 39 ? 0.5 145 ? ? 450 115 ? 0.5 ? 0.5 ? 125 145 0.5 ? ? ? 1.2 ? 1.5 13 0.2 5.0 30 5.0 0.2 95 ? ? 280 65 5.0 0.2 5.0 0.2 ? 75 95 0.2 5.0 ? ? ? ? ? 10 ? 4.5 21 4.5 ? ? 8 8 ? ? 4.5 ? 4.5 ? 8 ? ? ? 4.5 3 3.8 ? 2.5 ? 7 ? quiescent current vdrv output voltage "h" vdrv output voltage "l" vdrv output current "l" vdrv rising delay time hdrv output voltage "h" hdrv output voltage "l" hdrv output current "l" hdrv rising delay time (1) hdrv rising delay time (2) clamp output voltage "h" clamp output voltage "l" clamp output current "l" clamp rising delay time (1) synchronization detection output voltage "h" clamp rising delay time (2) synchronization detection output voltage "l" synchronization detection output current "l" synchronization detection output impedance minimum synchronization separation level hsctl "l" level threshold voltage hsctl "h" level threshold voltage cpsel "h" level threshold voltage cpsel "l" level threshold voltage v vdl i vdl trdvd v cc i cc v vdh i hdl trdhd1 v hdh v hdl v dh i dl v dl z od trdcp1 trdcp2 trdhd2 v cpl v cph i cpl v tcph v tcpl v thsh v thsl v smin. symbol typ. max. min. unit conditions ! ! ! ! synchronization signal detection chart input composite / hsync vsync polv l l h l l h l l h polh l l l l l l h h exiv l h h l h h h l h h h. comp (positive) h. comp (negative) no signal no signal positive negative no signal positive negative no signal positive negative h h h exih h h l l l h output
ba7078af multimedia ics ! ! ! ! relationship between input to output input composite / hsync explanation of symbol : signal input ? : no signal vsync clamp vdrv hdrv video cs video cs ? cs ? cs video cs vs vs ? cs vs vs video cs video cs ? cs ? cs video ? ? ? ? ? ? ? ? ? ? ? ? output ! ! ! ! input signal range parameter ? 1h = 1 / fh hor. separate sync posi. / neg. 1.0~5.0v p-p ? ? 15k~200khz 94ns~duty35% vert. separate sync ? ? posi. / neg. 1.0~5.0v p-p 40~200hz 8.0 s~duty35% composite sync posi. / neg. 1.0~5.0v p-p 40~200hz ? 1hmin.~400 s 15k~200khz 94ns~duty30% sync on video neg. 0.2~0.6v p-p 0~2.1v p-p 40~200hz ? 1hmin. 15k~200khz duty30% max. vert. sync frequency range : fv vert. sync pulse width range : pwv polarity amplitude (sync) : vs (video) : vv hor. sync pulse width range : pwh hor. sync frequency range : fh ! ! ! ! input signal waveform vert. / hor.separate sync t=1/f pw duty=pw/t(%) v s composite sync th=1/fh pwh pwv duty=pwh/th(%) (ex.pwv=1h) v s sync on video pwh th=1/fh pwv duty=pwh/th(%) (ex.pwv=1h) v s v v
ba7078af multimedia ics ! ! ! ! measurement circuit v v a v v a v v a v v a v v v v v v a v1 sw2 12 3 4.7 f 75 ? 4.7 f v2 sw3 1 23 v3 1 f 1 f 75 ? 0.56 f sw5 1 2 3 v5 75 ? 1m ? 1.5 f 4.7 f 1 f v8 100pf 3.9k ? v cc 8ma oscilloscope 1 2 3 sw11 8ma oscilloscope 1 2 3 sw12 8ma oscilloscope 1 2 3 sw13 v cc 5v 47 f 0.01 f 3ma oscilloscope 1 2 3 4 sw15 3ma oscilloscope 1 2 3 4 sw16 3ma oscilloscope 1 2 3 4 sw17 3ma oscilloscope 1 2 3 4 sw18 9 8 7 6 5 gnd cpsel cvexi cvpol vsync in vsepa 4 3 video in 2 c / hsync in 1 hsctl polh 18 exih 17 polv 16 exiv 15 v cc 14 hdrv 13 clamp 12 vdrv 11 cpwid 10 fig.1
ba7078af multimedia ics ! ! ! ! conditions for measurement of electrical characteristics parameter switch condition 2 1 1 1 1 1 3 3 3 2 1 2 2 3 2 1 2 2 3 3 2 1 3 3 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 1 1 1 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 2 1 3 1 3 3 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 2 1 3 3 1 2 2 1 1 5 1 1 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 3 3 2 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 12 1 1 1 1 1 1 1 2 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 1 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 18 quiescent current vdrv output voltage "h" vdrv output voltage "l" vdrv output current "l" vdrv rising delay time hdrv output voltage "h" hdrv output voltage "l" hdrv output current "l" hdrv rising delay time (1) hdrv rising delay time (2) clamp output voltage "h" clamp output voltage "l" clamp output current "l" clamp rising delay time (1) clamp rising delay time (2) polh output voltage "h" polh output voltage "l" polh output current "l" polh output impedance exih output voltage "h" exih output voltage "l" exih output current "l" exih output impedance polv output voltage "h" polv output voltage "l" polv output current "l" polv output impedance exiv output voltage "h" exiv output voltage "l" exiv output current "l" exiv output impedance minimum synchronization separation level hsctl "h" level threshold voltage hsctl "l" level threshold voltage cpsel "h" level threshold voltage cpsel "l" level threshold voltage
ba7078af multimedia ics ! ! ! ! application example hsctl c / h sync in video in vsync in 1 c1 4.7 f c2 1 f c3 0.56 f c7 0.47 f 2 3 4 6 c4 1.5 f 1 f c5 5 7 8 cpsel open : auto h : front l : back 9 18 17 16 15 14 13 12 11 10 c6 100pf 3.9k ? r1 v cc vdrv clamp hdrv 0.01 f 47 f r2 1m ? v cc 5v exist v polv exist h polh h sync det. sync sepa. v sync sepa. v sync det. clamp pulse gen. hor. sync control fig.2
ba7078af multimedia ics ! ! ! ! attached components r : the resistor for limiting the led current. use the resistor of not less than 1w. c1 : 47 f coupling capacitor for c / h sync in rpm-850 led r a low capacitance increases the size of the input pin waveform?s sag. c2 : 1 f coupling capacitor for video in a low capacitance increase the size of the input pin waveform?s sag. c3 : 0.56 f conversion capacitor for f-v a low capacitance increase the size of the ripple of the f-v conversion voltage. a large capacitance is not a problem, but will delay the reaction speed. c4 : 1.5 f capacitor for polh (detection of the vertical synchronization signal?s polarity) the minimum capacitance is determined as follows: the internal hysteresis comparator does not react when the duty of minimum frequency synchronization (fv = 40hz, t = 25ms) is 50%. cmin. = 16 t [f] a large capacitance is not a probrem, built will deray the reaction speed. c5 : 1 f capacitor for exih (detection of the vertical synchronization signal?s existance) the minimum capacitance is determined as follows: the internal hysteresis comparator does not react at the minimum frequency synchronization (fv = 40hz, t = 25ms) cmin. = 16 t [f] a large capacitance is not a problem, but will deray the reaction speed. c6 : 100pf constant for setting the clamp pulse width c7 : 0.47 f coupling capacitor for vsync in a low capacitance increases the size of the input pin waveform?s sag. r1 : 3.9k ? a low resistance results in a narrow clamp pulse width. set no lower than 1k ? . r2 : 1m ? discharge current setting resistor for clamp in
ba7078af multimedia ics ! ! ! ! electrical characteristic curves propagation delay of rise time : trdhd (ms) fig.3 c / hsync in-hdrv rising delay time vs. temperature temperature : ta( c) ? 50 ? 25 0 25 50 75 100 v cc = 5.0v 0 10 20 30 40 50 60 70 80 90 100 propagation delay of rise time : trdcl (ns) fig.4 c / hsync in-clamp rising delay time vs. temperature temperature : ta ( c) ? 50 ? 25 0 25 50 75 100 0 20 40 60 80 100 120 140 output position : front edge vcc = 5.0v propagation delay of rise time : trdhd (ns) fig.5 video in ? hdrv rising delay time vs. temperature temperature : ta ( c) ? 50 ? 25 0 25 50 75 100 0 20 40 60 80 100 120 140 vcc = 5.0v 160 propagation delay of rise time : trdcl (ns) fig.6 video in-clamp rising delay time vs. temperature temperature : ta ( c) ? 50 ? 25 0 25 50 75 100 0 20 40 60 80 100 120 140 output position back edge vcc = 5.0v propagation delay of rise time : trdvd (ns) fig.7 vsync in-vdrv rising delay time vs. temperature temperature : ta ( c) ? 50 ? 25 0 25 50 75 100 100 120 140 v cc = 5.0v 160 180 200 220 240 260 pin voltage : v s (v) fig.8 vsepa horizontal frequency vs. pin voltage horizontal frequency : fh (khz) v cc = 5.0v 0 204060 80 100 120 140 160 180 200 0 0.5 1 1.5 2 2.5 3 ! ! ! ! external dimensions (units : mm) sop18 0.4 0.1 1.27 0.3min. 0.11 1.8 0.1 5.4 0.2 7.8 0.3 0.15 0.1 18 1 11.2 0.2 10 9 0.15

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