View 74LVC841APW112_1885644.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the 74lvc841a is a high performance, low-power, low-voltage si-gate cmos device and superior to most advanced cmos compatible ttl families. inputs can be driven from either 3.3 v or 5 v devices. in 3-state operation, outputs can handle 5 v. this feature allows the use of these devices as translators in a mixed 3.3 v and 5 v environment. the 74lvc841a is a 10-bit transparent latch featuring separate d-type inputs for each latch and 3-state outputs for bus-oriented applications. a latch enable (pin le) input and an output enable (pin oe) input are common to all internal latches. the 74lvc841a consists of ten transparent latches with 3-state true outputs. when pin le is high, data at the dn inputs enters the latches. in this condition the latches are transparent, i.e., a latch output will change each time its corresponding d-input changes. when pin le is low the latches store the information that was present at the d-inputs a set-up time preceding the high-to-low transition of pin le. when pin oe is low, the contents of the ten latches are available at the outputs. when pin oe is high, the outputs go to the high-impedance off-state. operation of the pin oe input does not affect the state of the latches. 2. features n 5 v tolerant inputs/outputs; for interfacing with 5 v logic n wide supply voltage range from 1.2 v to 3.6 v n inputs accept voltages up to 5.5 v n cmos low power consumption n direct interface with ttl levels n flow-through pin-out architecture n complies with jedec standard jesd8b/jesd36 n esd protection: u hbm eia/jesd22-a114-b exceeds 2000 v u mm eia/jesd22-a115-a exceeds 200 v. n speci?ed from - 40 cto+85 c and - 40 c to +125 c. 74lvc841a 10-bit transparent latch with 5 v tolerant inputs/outputs; 3-state rev. 03 24 may 2004 product data sheet
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 2 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state 3. quick reference data [1] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. [2] the condition is v i = gnd to v cc . 4. ordering information table 1: quick reference data gnd = 0 v; t amb =25 c; t r =t f 2.5 ns. symbol parameter conditions min typ max unit t phl , t plh propagation delay dn to qn c l =50pf; v cc = 3.3 v - 3.0 - ns propagation delay le to qn c l =50pf; v cc = 3.3 v - 3.4 - ns t pzh , t pzl 3-state output enable time oe to qn c l =50pf; v cc = 3.3 v - 3.5 - ns t phz , t plz 3-state output disable time oe to qn c l =50pf; v cc = 3.3 v - 2.9 - ns c i input capacitance - 5.0 - pf c pd power dissipation capacitance per latch v cc = 3.3 v [1] [2] outputs enabled - 13 - pf outputs disabled - 4 - pf table 2: ordering information type number package temperature range name description version 74lvc841ad - 40 c to +125 c so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1 74lvc841adb - 40 c to +125 c ssop24 plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1 74lvc841apw - 40 c to +125 c tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 74lvc841abq - 40 c to +125 c dhvqfn24 plastic dual in-line compatible thermal enhanced very thin quad ?at package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm sot815-1
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 3 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state 5. functional diagram fig 1. functional diagram. fig 2. logic symbol. fig 3. iec logic symbol. 001aaa842 d0 d1 d2 d3 d4 d5 d6 d7 latch 1 to 8 q0 q1 q2 q3 q4 q5 q6 q7 3-state outputs d8 q8 le oe 2 3 4 5 6 7 8 9 10 23 22 21 20 19 18 17 16 15 13 1 d9 q9 11 14 le 001aaa838 oe 13 23 q 0 1 22 q 1 d 0 d 1 2 3 21 q 2 20 q 3 d 2 d 3 4 5 19 q 4 18 q 5 d 4 d 5 6 7 17 q 6 16 q 7 d 6 d 7 8 9 15 q 8 14 q 9 d 8 d 9 10 11 en 23 2 3 22 4 21 5 20 6 19 7 18 8 17 9 16 001aaa83 9 1d 13 1 c1 10 15 11 14
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 4 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state fig 4. logic diagram 001aaa843 q0 d0 d latch 1 q le le oe le q1 d1 d latch 2 q le le q2 d2 d latch 3 q le le q3 d3 d latch 4 q le le q4 d4 d latch 5 q le le q5 d5 d latch 6 q le le q6 d6 d latch 7 q le le q7 d7 d latch 8 q le le q8 d8 d latch 9 q le le q9 d9 d latch 10 q le le
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 5 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state 6. pinning information 6.1 pinning 6.2 pin description (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. fig 5. pin con?guration for so24 and (t)ssop24. fig 6. pin con?guration for dhvqfn24. 841 oe v cc d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 d8 q8 d9 q9 gnd le 001aaa836 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 001aaa83 7 841 transparent top view q9 d8 d9 q8 d7 q7 d6 q6 d5 q5 d4 q4 d3 q3 d2 q2 d1 q1 d0 q0 gnd le oe v cc 11 14 10 15 9 16 8 17 7 18 6 19 5 20 4 21 3 22 2 23 12 13 1 24 terminal 1 index area gnd (1) table 3: pin description pin symbol description 1 oe output enable input (active low) 2 d0 data input 3 d1 data input 4 d2 data input 5 d3 data input 6 d4 data input 7 d5 data input 8 d6 data input 9 d7 data input 10 d8 data input 11 d9 data input 12 gnd ground (0 v) 13 le latch enable input (active low) 14 q9 3-state latch output 15 q8 3-state latch output
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 6 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state 7. functional description 7.1 function table [1] h = high voltage level; h = high voltage level one set-up time prior to the high-to-low le transition; l = low voltage level; l = low voltage level one set-up time prior to the high-to-low le transition; z = high-impedance off-state; nc = no change; x = dont care. 8. limiting values 16 q7 3-state latch output 17 q6 3-state latch output 18 q5 3-state latch output 19 q4 3-state latch output 20 q3 3-state latch output 21 q2 3-state latch output 22 q1 3-state latch output 23 q0 3-state latch output 24 v cc supply voltage table 3: pin description continued pin symbol description table 4: function table [1] operating mode input internal latches output oe le dn qn enable and read register (transparent mode) lhlll l hhhh latch and read register l l l l l llhhh latch register and disable outputs hl l l z hlhhz hold l l x nc nc table 5: limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +6.5 v i ik input diode current v i <0v - - 50 ma v i input voltage [1] - 0.5 +6.5 v i ok output diode current v o >v cc or v o <0v - 50 ma
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 7 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for so24 packages: above 70 c derate linearly with 8 mw/k. for (t)ssop24 packages: above 60 c derate linearly with 5.5 mw/k. for dhvqfn24 packages: above 60 c derate linearly with 4.5 mw/k. 9. recommended operating conditions 10. static characteristics v o output voltage high or low state [1] - 0.5 v cc + 0.5 v 3-state [1] - 0.5 +6.5 v i o output source or sink current v o =0vtov cc - 50 ma i cc , i gnd v cc or gnd current - 100 ma t stg storage temperature - 65 +150 c p tot power dissipation t amb = - 40 c to +125 c [2] - 500 mw table 5: limiting values continued in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit table 6: recommended operating conditions symbol parameter conditions min max unit v cc supply voltage for maximum speed performance 2.7 3.6 v for low-voltage applications 1.2 3.6 v v i input voltage 0 5.5 v v o output voltage high or low state 0 v cc v 3-state 0 5.5 v t amb operating ambient temperature in free air - 40 +125 c t r , t f input rise and fall times v cc = 1.2 v to 2.7 v 0 20 ns/v v cc = 2.7 v to 3.6 v 0 10 ns/v table 7: static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = - 40 c to +85 c [1] v ih high-level input voltage v cc = 1.2 v v cc --v v cc = 2.7 v to 3.6 v 2.0 - - v v il low-level input voltage v cc = 1.2 v - - gnd v v cc = 2.7 v to 3.6 v - - 0.8 v
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 8 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state v oh high-level output voltage v i =v ih or v il i o = - 100 m a; v cc = 2.7 v to 3.6 v v cc - 0.2 v cc [2] -v i o = - 12 ma; v cc = 2.7 v v cc - 0.5 - - v i o = - 18 ma; v cc = 3.0 v v cc - 0.6 - - v i o = - 24 ma; v cc = 3.0 v v cc - 0.8 - - v v ol low-level output voltage v i =v ih or v il i o = 100 m a; v cc = 2.7 v to 3.6 v [2] - gnd 0.2 v i o = 12 ma; v cc = 2.7 v - - 0.4 v i o = 24 ma; v cc = 3.0 v - - 0.55 v i li input leakage current v i = 5.5 v or gnd; v cc = 3.6 v - 0.1 5 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 5.5 v or gnd; v cc = 3.6 v - 0.1 5 m a i off power-off leakage supply v i or v o = 5.5 v; v cc = 0.0 v - 0.1 10 m a i cc quiescent supply current v i =v cc or gnd; i o =0a; v cc = 3.6 v - 0.1 10 m a d i cc additional quiescent supply current per pin v i =v cc - 0.6 v; i o =0a; v cc = 2.7 v to 3.6 v [2] - 5 500 m a c i input capacitance - 5.0 - pf t amb = - 40 c to +125 c v ih high-level input voltage v cc = 1.2 v v cc --v v cc = 2.7 v to 3.6 v 2.0 - - v v il low-level input voltage v cc = 1.2 v - - gnd v v cc = 2.7 v to 3.6 v - - 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 100 m a; v cc = 2.7 v to 3.6 v v cc - 0.3 - - v i o = - 12 ma; v cc = 2.7 v v cc - 0.65 - - v i o = - 18 ma; v cc = 3.0 v v cc - 0.75 - - v i o = - 24 ma; v cc = 3.0 v v cc - 1--v v ol low-level output voltage v i =v ih or v il i o = 100 m a; v cc = 2.7 v to 3.6 v - - 0.3 v i o = 12 ma; v cc = 2.7 v - - 0.6 v i o = 24 ma; v cc = 3.0 v - - 0.8 v i li input leakage current v i = 5.5 v or gnd; v cc = 3.6 v - - 20 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 5.5 v or gnd; v cc = 3.6 v -- 20 m a table 7: static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 9 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state [1] all typical values are measured t amb = 25 c. [2] these typical values are measured at v cc = 3.3 v. 11. dynamic characteristics i off power-off leakage supply v i or v o = 5.5 v; v cc = 0.0 v - - 20 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 a; v cc = 3.6 v --40 m a d i cc additional quiescent supply current per pin v i =v cc - 0.6 v; i o =0a; v cc = 2.7 v to 3.6 v --5000 m a table 7: static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit table 8: dynamic characteristics gnd = 0 v; t r =t f 2.5 ns; c l = 50 pf; r l = 500 w . symbol parameter conditions min typ max unit t amb = - 40 c to +85 c [1] t phl , t plh propagation delay dn to qn see figure 7 and 11 v cc = 1.2 v - 15 - ns v cc = 2.7 v 1.5 - 7.5 ns v cc = 3.0 v to 3.6 v [2] 1.5 3.0 6.7 ns propagation delay le to qn see figure 8 and 11 v cc = 1.2 v - 17 - ns v cc = 2.7 v 1.5 - 8.6 ns v cc = 3.0 v to 3.6 v [2] 1.5 3.4 7.6 ns t pzh , t pzl 3-state output enable time oe to qn see figure 10 and 11 v cc = 1.2 v - 19 - ns v cc = 2.7 v 1.5 - 8.5 ns v cc = 3.0 v to 3.6 v [2] 1.5 3.5 7.2 ns t phz , t plz 3-state output disable time oe to qn see figure 10 and 11 v cc = 1.2 v - 8.0 - ns v cc = 2.7 v 1.5 - 6.6 ns v cc = 3.0 v to 3.6 v [2] 1.5 2.9 5.9 ns t w le pulse width high see figure 8 v cc = 1.2 v ---ns v cc = 2.7 v 2.0 - - ns v cc = 3.0 v to 3.6 v [2] 2.0 0.7 - ns
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 10 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state t su set-up time dn to le see figure 9 v cc = 1.2 v ---ns v cc = 2.7 v 2.0 - - ns v cc = 3.0 v to 3.6 v [2] 2.0 1.0 - ns t h hold time dn to le see figure 9 v cc = 1.2 v ---ns v cc = 2.7 v 1.0 - - ns v cc = 3.0 v to 3.6 v [2] 1.0 0.0 - ns t sk(0) skew v cc = 3.0 v to 3.6 v [3] - - 1.0 ns c pd power dissipation capacitance per latch v cc = 3.3 v [4] [5] outputs enabled - 13 - pf outputs disabled - 4 - pf t amb = - 40 c to +125 c t phl , t plh propagation delay dn to qn see figure 7 and 11 v cc = 1.2 v ---ns v cc = 2.7 v 1.5 - 9.5 ns v cc = 3.0 v to 3.6 v 1.5 - 8.5 ns propagation delay le to qn see figure 8 and 11 v cc = 1.2 v ---ns v cc = 2.7 v 1.5 - 11.0 ns v cc = 3.0 v to 3.6 v 1.5 - 9.5 ns t pzh , t pzl 3-state output enable time oe to qn see figure 10 and 11 v cc = 1.2 v ---ns v cc = 2.7 v 1.5 - 11.0 ns v cc = 3.0 v to 3.6 v 1.5 - 9.0 ns t phz , t plz 3-state output disable time oe to qn see figure 10 and 11 v cc = 1.2 v ---ns v cc = 2.7 v 1.5 - 8.5 ns v cc = 3.0 v to 3.6 v 1.5 - 7.5 ns t w le pulse width high see figure 8 v cc = 1.2 v ---ns v cc = 2.7 v 2.0 - - ns v cc = 3.0 v to 3.6 v 2.0 - - ns t su set-up time dn to le see figure 9 v cc = 1.2 v ---ns v cc = 2.7 v 2.0 - - ns v cc = 3.0 v to 3.6 v 2.0 - - ns table 8: dynamic characteristics continued gnd = 0 v; t r =t f 2.5 ns; c l = 50 pf; r l = 500 w . symbol parameter conditions min typ max unit
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 11 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state [1] all typical values are measured t amb = 25 c. [2] these typical values are measured at v cc = 3.3 v. [3] skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. [4] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. [5] the condition is v i = gnd to v cc . 12. waveforms t h hold time dn to le see figure 9 v cc = 1.2 v ---ns v cc = 2.7 v 1.0 - - ns v cc = 3.0 v to 3.6 v 1.0 - - ns t sk(0) skew v cc = 3.0 v to 3.6 v [3] - - 1.5 ns table 8: dynamic characteristics continued gnd = 0 v; t r =t f 2.5 ns; c l = 50 pf; r l = 500 w . symbol parameter conditions min typ max unit v m = 1.5 v at v cc 3 2.7 v; v m = 0.5 v cc at v cc < 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load. fig 7. input (dn) to output (qn) propagation delays. mna884 dn input qn output t phl t plh gnd v i v m v m v oh v ol
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 12 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state v m = 1.5 v at v cc 3 2.7 v; v m = 0.5 v cc at v cc < 2.7 v. v ol and v oh are typical output voltage drop that occur with the output load. fig 8. latch enable input ( le) pulse width, the latch enable input to output (qn) propagation delays. v m = 1.5 v at v cc 3 2.7 v; v m = 0.5 v cc at v cc < 2.7 v. v ol and v oh are typical output voltage drop that occur with the output load. the shaded areas indicate when the input is permitted to change for predicable output performance. fig 9. data setup and hold times for the dn input to the le input. mna885 le input qn output t phl t plh t w v m v oh v i gnd v ol v m mna887 t h t su t h t su v m v m v i gnd v i gnd le input dn input
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 13 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state v m = 1.5 v at v cc 3 2.7 v; v m = 0.5 v cc at v cc < 2.7 v; v x = v ol + 0.3 v at v cc 3 2.7 v; v x = v ol + 0.1 v cc at v cc < 2.7 v; v y = v oh - 0.3 v at v cc 3 2.7 v; v y = v oh - 0.1 v cc at v cc < 2.7 v. v ol and v oh are typical output voltage drop that occur with the output load. fig 10. 3-state enable and disable times. mna886 t plz t phz output disabled output enabled v y v x output enabled qn output low-to-off off-to-low qn output high-to-off off-to-high oe input v ol v oh v cc v i v m gnd gnd t pzl t pzh v m v m
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 14 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state [1] the circuit performs better when r l = 1000 w . test data is given in t ab le 9 . de?nitions for test circuits: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. fig 11. load circuitry for switching times. table 9: measurement points supply voltage input load v ext v cc v i c l r l t plh , t phl t pzh , t phz t pzl , t plz 1.2 v v cc 50 pf 500 w [1] open gnd 2 v cc 2.7 v 2.7 v 50 pf 500 w open gnd 2 v cc 3.0 v to 3.6 v 2.7 v 50 pf 500 w open gnd 2 v cc v ext v cc v i v o mna616 d.u.t. c l r t r l r l pulse generator
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 15 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state 13. package outline fig 12. package outline so24. unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1 99-12-27 03-02-19
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 16 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state fig 13. package outline ssop24. unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 0.8 0.4 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot340-1 mo-150 99-12-27 03-02-19 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 112 24 13 0.25 y pin 1 index 0 2.5 5 mm scale ssop24: plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1 a max. 2
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 17 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state fig 14. package outlinetssop24. unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 112 24 13 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 a max. 1.1
philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state 9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 18 of 21 fig 15. package outline dhvqfn24. references outline version european projection issue date iec jedec jeita note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. sot815-1 - - - - - - - - - 03-04-29 sot815-1 0 2.5 5 mm scale b y y 1 c c a c c b v m w m e 1 e 2 terminal 1 index area terminal 1 index area x unit a (1) max. a 1 bc e e h l e 1 y w v mm 1 0.05 0.00 0.30 0.18 0.5 4.5 e 2 1.5 0.2 2.25 1.95 d h 4.25 3.95 0.05 0.05 y 1 0.1 0.1 dimensions (mm are the original dimensions) 0.5 0.3 d (1) 5.6 5.4 e (1) 3.6 3.4 d e b a e dhvqfn24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm a a 1 c detail x e h l d h 2 23 11 14 13 12 1 24
9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 19 of 21 philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state 14. revision history table 10: revision history document id release date data sheet status change notice order number supersedes 74lvc841a_3 20040524 product data - 9397 750 13129 74lvc841a_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the current presentation and information standard of phillips semiconductors. ? addition of temperature range t amb = - 40 c to +125 c 74lvc841a_2 19980617 product speci?cation - 9397 750 04522 74lvc841a_1
philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state 9397 750 13129 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 24 may 2004 20 of 21 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 24 may 2004 document order number: 9397 750 13129 published in the netherlands philips semiconductors 74lvc841a 10-bit transparant latch with 5 v tolerant inputs/outputs; 3-state 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . 1 2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram. . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 recommended operating conditions . . . . . . . 7 10 static characteristics . . . . . . . . . . . . . . . . . . . . 7 11 dynamic characteristics . . . . . . . . . . . . . . . . . 9 12 waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 15 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 19 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 18 contact information . . . . . . . . . . . . . . . . . . . . 20

▲Up To Search▲

Price & Availability of 74LVC841APW112

	To Download 74LVC841APW112 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .