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1. general description the pca9703 is a low power 18 v tolerant spi general purpose input (gpi) shift register designed to monitor the status of switch in puts. it generates an interrupt when one or more of the switch inputs change state but allows selected inputs to not generate interrupts using the interrupt masking feature. the input level is recognized as a high when it is greater than 0.8 v dd and as a low when it is less than 0.55 v dd (minimum low threshold of 2.5 v at 5 v node). the pca9703 can monitor up to 16 switch inputs. the falling edge of the cs pin samples the input port status and clears the interrupt. when cs is low, the rising edge of the sclk loads t he shift register and shifts the value out of the shift register. the serial input is sampled on the falling edge of sclk. the contents of the shift register are loaded into the interrupt mask register of the device on the rising edge of cs . each of the input ports has a 18 v breakdo wn esd protection circuit, which dumps the esd/overvoltage current to ground. when used with a series resistor (minimum 100 k ), the input can connect to a 12 v battery and su pport double battery, reverse battery, 27 v jump start and 40 v load dump conditions in automotive applications. higher voltages can be tolerated on the inputs depending on the se ries resistor used to limit the input current. the int_en pin is used to both enable the gpi pins and to enable the int output pin to minimize battery drain in pull-up cycled applications. the sdin pull-down prevents floating nodes when the device is used in daisy-chain applications. with both the high breakdown voltage and high esd, this device is useful for both automotive (aec-q100 compliance available) and mobile applications. 2. features ? 16 general purpose input ports ? 18 v tolerant input ports with 100 k external series resistor ? input low threshold 0.55 v dd with minimum of 2.5 v at v dd =4.5v ? input hysteresis 0.04 v dd with minimum of 180 mv at v dd =4.5v ? open-drain interrupt output ? interrupt enable pin (int_en) disables gpi pins and interrupt output ? interrupt-masking feature allows no interrupt generation from selected inputs ? v dd range: 4.5 v to 5.5 v ? i dd is very low 2.5 a maximum ? spi serial interface with speeds up to 5 mhz ? spi supports daisy-chain connection for large switch numbers ? aec-q100 compliance available pca9703 18 v tolerant spi 16-bi t gpi with maskable int rev. 01 ? 23 february 2010 product data sheet
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 2 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int ? esd protection exceeds 5 kv hbm per jesd22-a114, 350 v mm per aec-q100, and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? operating temperature range: ? 40 c to +125 c ? offered in tssop24 and hwqfn24 packages 3. applications ? automotive ? body control modules ? electronic control units (e.g., for body controller) ? switch monitoring ? sbc wake pin extension ? industrial equipment ? cellular telephones ? emergency lighting 4. ordering information [1] pca9703pw/q900 is aec-q100 compliant. contact i2c.support@nxp.com for ppap. table 1. ordering information type number topside mark package name description version pca9703hf 9703 hwqfn24 plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 4 0.75 mm sot994-1 pca9703pw pca9703pw tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 pca9703pw/q900 [1] pca9703pw tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 3 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 5. block diagram 6. pinning information 6.1 pinning fig 1. block diagram of pca9703 cs sclk sdin sdout int 002aae021 shift register dff0 in0 dff1 in1 dff15 in15 pca9703 v ss v dd int_en input status register 20 a input input input mask register fig 2. pin configuration for hwqfn24 f ig 3. pin configuration for tssop24 002aae02 4 pca9703hf transparent top view in11 in4 in5 in12 in3 in13 in2 in14 in1 in15 in0 cs in6 in7 v ss in8 in9 in10 int_en int sdout v dd sdin sclk terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19 pca9703pw pca9703pw/q900 sdout v dd int sdin int_en sclk in0 cs in1 in15 in2 in14 in3 in13 in4 in12 in5 in11 in6 in10 in7 in9 v ss in8 002aae023 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 4 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 6.2 pin description [1] hwqfn24 package die supply ground is connected to both v ss pin and exposed center pad. v ss pin must be connected to supply ground for pr oper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. table 2. pin description symbol pin type description tssop24 hwqfn24 sdout 1 22 output 3-state serial data output; normally high-impedance int 2 23 output open-drain inte rrupt output (active low) int_en 3 24 input gpi pin enable and interrupt output enable 1 = gpi pin and interrupt output are enabled 0 = gpi pin and interrupt output are disabled and interrupt output is high-impedance in0 4 1 input input port 0 in1 5 2 input input port 1 in2 6 3 input input port 2 in3 7 4 input input port 3 in4 8 5 input input port 4 in5 9 6 input input port 5 in6 10 7 input input port 6 in7 11 8 input input port 7 v ss 12 9 [1] ground ground supply in8 13 10 input input port 8 in9 14 11 input input port 9 in10 15 12 input input port 10 in11 16 13 input input port 11 in12 17 14 input input port 12 in13 18 15 input input port 13 in14 19 16 input input port 14 in15 20 17 input input port 15 cs 21 18 input chip select (active low) sclk 22 19 input serial input clock sdin 23 20 input serial data input (20 a pull-down) v dd 24 21 supply supply voltage
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 5 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 7. functional description pca9703 is a 16-bit general purpose input (gpi) with an open-drain interrupt output designed to monitor switch status. by putting an external 100 k series resistor at the input port, the device allows the input to tolerate momentary double 12 v battery, reverse battery, 27 v jump start or 40 v load dump conditions. the interrupt output is asserted when an input port status changes, the input is not masked and the interrupt output is enabled. the open-drain interrupt output is enabled when int_en is high and disabled when int_en is low. the int_en also enables the gpi pins when it is high. in cyclic pull-up applications th e gpi pull-ups should be active bef ore the int_en is taken high and the int output should only be sampled afte r transient conditions have settled. additionally, interrupts can be disabled in software by using the interrupt mask feature. the input port status is accessed via the 4-wire spi interface. upon power-up, the power-up reset cell clears a ll the registers, result ing in all zeros in both the input status register and the interrupt mask register. since a zero in the interrupt mask register masks the interr upt from that pin, there will no t be any interrupts generated. after power-up it is necessary to access the pca9703 through the spi pins in order to activate the interrupt for any gpi pins. when the pca9703 is read over the spi wires, the input conditions are clocked into the input status register on the cs falling edge. since the inputs and the input status register now match, no interrupt is generated and any pre-existing interrupt is cleared. the input status register data is parallel loaded into the shift register on the first rising edge of the sclk. the serial input data is captured on the opposite clock edge so that there is a 1 ? 2 clock cycle hold time. the set-up time is diminished by the propagation time so the sc lk falling edge to rising edge must be long enough to provide sufficient set-up time. su ccessive clock cycles on the sclk pin clock the data out of the pca9703 and new data from the sdin into the shift register. there is no limit to the number of clock cycles that can be applied with the cs low, however sufficient clock cycles should be used to both shift out all of the gpi data and shift in the new interrupt mask data to the correct po sition with the msb first before the cs rising edge. for cyclic switch bias applicati ons the switch bias should be applied first, then after the input voltage is settled the general purpose in puts are switched on by taking the int_en high. this also enables the interrupt output, wh ich will only indicate an interrupt if the gpi data does not match the input status register on a bit that is enabled by the interrupt mask register value. if an interrupt is generate d, the pull-up should remain active and the int_en should remain active and the spi pins are used to update the input status register and read the data out. they are also used to store the new interrup t mask on the rising edge of cs . after the spi transaction is complete the int_en is taken low to turn the inputs off and disable the int output. then the gpi pull-ups can be turned off. the gpi pins are specifically designed so that any esd/overstress current flows to ground, not v dd . they are also specifically designed so that if the input voltage returns to the same value after pull-up cycling as before the input pu ll-up cycling, before the input is enabled it will be detected as the same state. if the v dd falls below the 4.5 v minimum specifi ed supply voltage, the input threshold will move down since they ar e a function of the v dd voltage. the input status register and the interrupt mask register reta in their values to below v dd = 2.0 v and power-down can only be used to generate a power-up reset if the v dd falls below 0.2 v before returning to the operating range.
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 6 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int multiple pca9703 devices can be serially connected for monitoring a large number of switches by connecting the sdout of one devi ce to the sdin of the next device. sclk and cs must be common among all devices and interrupt outputs may be tied together. no external logic is necessary because all the devices? interrupt outputs are open-drain that function as ?wired-and? and can simply be connected t ogether to a single pull-up resistor. 7.1 spi bus operation the pca9703 interfaces with the controller via the 4-wire spi bus that is comprised of the following signals: chip select (cs ), serial clock (sclk), serial data in (sdin), and serial data out (sdout). to access th e device, the controller asserts cs low, then sends sclk and sdin. when reading is complete and the interrupt mask data is in place, the controller de-asserts cs . see figure 4 for register access timing. 7.1.1 cs - chip select the cs pin is the device chip select and is an active low input. the falling edge of cs captures the input port status in the input status register. if the interrupt output is asserted, the falling edge of cs will clear the interrupt. when cs is low, the spi interface is active. when cs transitions high the interrupt mask is stored and when cs is high, the spi interface is disabled. 7.1.2 sclk - serial clock input sclk is the serial clock input to the device. it should be low and remain low during the falling and rising edge of cs . when cs is low, the first rising edge of sclk parallel loads the shift register from the input status register. the subsequent rising edges on sclk serially shifts data out from the shif t register. the falling edge of sclk samples the data on sdin. 7.1.3 sdin - serial data input sdin is the serial data input port. the data is sampled into the shift register on the falling edge of sclk. sdin is only active when cs is low. this input has a 20 a pull-down current source to prevent the sd in node from floating when cs is high. 7.1.4 sdout - serial data output sdout is the serial data output si gnal. sdout is high-impedance when cs is high and switches to low-impedance after cs goes low. when cs is low, after the first rising edge of sclk the most significant bit in the shift register is presented on sdout. subsequent rising edges of sclk shift the remaining data from the shift register onto sdout. 7.1.5 register access timing figure 4 shows the waveforms of the de vice operation. initially cs is high and sclk is low. on the falling edge of cs , input port status, data[n:0] is captured into the input status register, and subsequen tly the first rising edge of sclk parallel loads the shift register. the falling edge of sclk samples the data on the sdin. the msb from the shift register is valid and available on the sd out after the first rising edge of sclk.
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 7 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 7.1.6 software reset operation software reset will be activated by writing all zer oes into the shift regist er. this is identical to having an interrup t mask value of 0x00. such an op eration will reset t he device, clear the input status register to zero and set th e interrupt output to high (no interrupt). 7.2 interrupt output int is the open-drain interrupt output and is active low. a pull-up resistor of approximately 10 k is recommended. a user-defined interrupt mask bit pattern is shifted into the shift register via sdin. the value of bits in the mask pattern will dete rmine which input pins will cause an interrupt. any bit that is = 0 will disable the input pi n corresponding to t hat bit position from generating an inte rrupt. interrupts will be enabled for bi ts having value = 1. the mask bit pattern is not automatically alig ned with the desired input pins. it is the responsibility of the programmer to shift the correct number of (mask) bits to the correct positions into the shift register. the interrupt mask bit pattern must be positioned into the shift register prior to the cs rising edge. misaligned mask pattern will re sult in unexpected activation of the interrupt signal. the interrupt output is asserted when the input status is changed, and the interrupt mask bit corresponding to the input pin that caused the change is unmasked (bit value = 1), and is cleared on the falling edge of cs or when the input port status matches the input status register. when there are multiple devices, the int outputs may be tied together to a single pull-up. data[15:0] is data on the input pins, in[15:0]. shaded areas indicate active but invalid data. fig 4. register access timing cs sclk sdin sdout high-impedance msb in msb out 002aae28 6 msb ? 1 in msb ? 1 out lsb in lsb out input status register shift register data[15:0] data[15:0] sample sdin interrupt mask register
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 8 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int ta b l e 3 illustrates the state of the interrupt output versus the state of th e input port and input status register. the interrupt output is asserted when the input port and input status register differ. [1] input status register is the value or content of the d flip-flops. [2] logic states shown for int pin assumes 10 k pull-up resistor. 7.3 interrupt enable int_en is the interrupt output enable input and the general purpose input enable input. it is an active high input. when the int_en pin is low the gpi pins are turned off to minimize power loss when the input pull-ups are cycled and the int output is disabled. the cycled pull-up should be ac tive sufficiently long before the int_en is taken active that the gpi pin voltage is completely settled to prevent false or transient interrupt signals. 7.4 general purpose inputs the general purpose inputs (gpi) are designed to behave like a typical input in the 0 v to 5.5 v range, but are also designed to have lo w leakage currents at elevated voltages. the input structure allows for elevated voltages to be applied through a series resistor. the series resistor is required when the input vo ltage is above 5.5 v. the series resistor is required for two reasons: first, to prevent damage to the input avalanche diode, and second, to prevent the esd protection circui try from creating an excessive current flow. the esd protection circuitry includes a latc h-back style device, which provides excellent esd protection during assembly or typical 5.5 v applications. the series resistor limits the current flowing into the part and provides additional esd protection. the limited current prevents the esd latch-back device from latching back to a low voltage, which would cause excessive current flow and damage the part when the input voltage is above 5.5 v. the minimum required series resistance for applications with input voltages above 5.5 v is 100 k . for applications requiring an applied voltage above 27 v, equation 1 is recommended to determine the series resistor. failure to include the appropriate input series resistor may result in product failure and will void the warranty. (1) the series resistor should be place physically as close as possible to the connected input to reduce the effective node capacitance. the input response time is effected by the rc time constant of the series resi stor and the input node capacitance. table 3. interrupt output function truth table h = high; l = low; x = don?t care int_en input port status input status register [1] int output [2] mask bit = 1 (unmasked) mask bit = 0 (masked) hl l h h hl h l h hh l l h hh h h h lx x h h r s voltage applied 17 v ? i i ----------------------------------------------------------- - =
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 9 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 7.4.1 v il , v ih and switching points a minimum low threshold of 2.5 v is guaranteed for the logical switching points for the inputs. see figure 5 for details. the v il is specified as a maximum of 0.55 v dd and is 2.5 v at 4.5 v v dd . this means that if the user applies 2.5 v or less to the input (with v dd = 4.5 v), or as the voltage passes this threshold, th ey will always see a low. the v ih is specified as a minimum of 0.8 v dd . this means that if the user applies 3.6 v or more to the input (with v dd = 4.5 v), or as the voltage pass es this threshold, they will always see a high. hysteresis minimum is s pecified as 180 mv at v dd = 4.5 v. this means there will always be at least 180 mv of difference between t he low threshold and high threshold to help prevent oscillations and handle higher noise. fig 5. logic level thresholds 002aae101 v i v dd hysteresis minimum = 0.04v dd 0 v 0.55v dd 0.8v dd high low v ih v il possible ground shift
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 10 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 8. application design-in information 8.1 general application 8.2 automotive application supports: ? 12 v battery (8 v to 16 v) ? double battery (16 v to 32 v) ? reverse battery ( ? 8 v to ? 16 v) ? jump start (27 v for 60 seconds) ? load dump (40 v) fig 6. typical application cs sclk sdin sdout 002aae026 in0 in1 in15 pca9703 v ss v dd int_en int controller or processor 10 k 4.5 v to 5.5 v 1.5 k 100 k relay 18 v 100 k 18 v 10 k 5 v 500 k 180 v 50 k in2 open
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 11 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 8.2.1 sbc wake port extension with cyclic biasing system basis chips (sbc) offer many functions needed for in-vehicle networking solutions. some of the features built into sbc are: ? transceivers (hs-can, lin 2.0) ? scalable voltage regulators ? watchdog timers; wake-up function ? fail-safe function for more information on sbc, refer to http://www.nxp.com/index.html#/pip/pip=[pfp=53482]|pp=[t=pfp,i=53482] . 8.2.1.1 uja106x with pca9703, standby ? pca9703 fits to sbc uja106x and uja107x family ? pca9703 can be powered by v1 of sbc ? extends the sbc with 16 additional wake inputs ? c can be set to stop-mode during standby to save ecu standby current. sbc with gpi periodically monitors the wake inputs ? cyclic bias via v3 ? very low system current consumption even with clamped switches ? interrupt enable control via v2 fig 7. uja106x with pca9703 with supplied c (standby) cs sdin sdout sclk 002aae02 7 in0 pca9703 v ss v dd int_en int in1 in15 alternate pvr100ad-b5v0 v3 uja106x wake v1 gnd v cc c csn mosi miso sclk gnd v2
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 12 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 8.2.1.2 uja106x with pca9703, sleep ? very low quiescent system current (50 a) due to disabled c and cyclically biasing of switches ? wake-up upon change of switches or upon bus traffic (can and lin) ? pca970x supplied out of cyclica lly biased transistor regulator fig 8. uja106x with pca9703 with unsupplied c (sleep) cs sdin sdout sclk 002aae02 8 in0 pca9703 v ss v dd int_en in1 in15 alternate pvr100ad-b5v0 v3 uja106x wake v1 gnd v cc c csn mosi miso sclk gnd int alternate pmem4010nd rstn alternate pdtc144tu v2
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 13 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 8.2.1.3 uja107x with pca9703, standby and sleep ? uja107x sbc provides wbias pin for cyclic biasing of the inputs ? compatible with uja107x based assps fig 9. uja107x with pca9703 with supplied c (standby) fig 10. uja107x with pca9703 with supplied c (sleep) cs sdin sdout sclk 002aae02 9 in0 pca9703 v ss v dd int_en int in1 in15 bat uja107x wake2 v1 gnd v cc c csn mosi miso sclk gnd wbias rstn 1 k 1 k 1 k 100 k 100 k 100 k v1 10 k 10 k 10 k 10 k 47 k 47 k wake1 alternate pdta114e alternate pdta144e cs sdin sdout sclk 002aae97 2 in0 pca9703 v ss v dd int_en int in1 in15 bat uja107x wake2 v1 gnd v cc c csn mosi miso sclk gnd wbias rstn 1 k 1 k 1 k 100 k 100 k 100 k 10 k 10 k 10 k 10 k 47 k 47 k wake1 330 470 nf 10 k 47 k alternate pvr100ad-b5v0 alternate pdta114e alternate pdta144e alternate pdtc144t
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 14 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 8.2.2 application examples including switches to battery 9. limiting values [1] with gpi external series resistors, the inputs support dou ble battery, reverse battery and load dump conditions. during doub le battery or load dump the input pin will drain slightly higher leakage current until the input drops to 18 v. for more detail of leakage cur rent specification, please refer to table 5 ? static characteristics ? . see section 7.4 for series resistor requirements. fig 11. clamp 15 (ignition) detection fig 12. switches to battery and ground with cyclic biasing 002aae030 in0 pca9703 in1 in15 switch bias clamp 15 002aae031 in0 pca9703 in1 in15 switch bias bat bat table 4. limiting values in accordance with the absolute ma ximum rating system (iec 60134). t amb = ? 40 cto+125 c, unless otherwise specified. symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.0 v i i input current in[15:0] pins with series resistor and v i >5.5v [1] - 350 a v i input voltage gpi pins in[15:0]; no series resistor [1] ? 0.5 +6 v spi pins ? 0.5 +6 v t stg storage temperature ? 65 +150 c t j(max) maximum junction temperature operating - 125 c
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 15 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 10. static characteristics [1] v dd must be lowered to 0.2 v for at least 5 s in order to reset device. [2] minimum v il is 2.5 v at v dd =4.5v. [3] minimum v hys is 180 mv at v dd =4.5v. [4] for gpi pin voltages > 5.5 v, see section 7.4 . table 5. static characteristics v dd = 4.5 v to 5.5 v; v ss =0v; t amb = ? 40 c to +125 c; unless otherwise specified. symbol parameter conditions min typ max unit supply v dd supply voltage 4.5 5.0 5.5 v i dd supply current v dd =5.5v; input=5vor18v; int_en = v dd -1.02.5 a v por power-on reset voltage [1] -1.82.2v general purpose inputs (in0 to in15) v il low-level input voltage [2] - - 0.55v dd v v ih high-level input voltage 0.8v dd -- v v hys hysteresis voltage [3] 0.04v dd -- v i i input current gpi recommended maximum current; v i > 5.5 v; with series resistor r s [4] - - 100 a i ih high-level input current each input; v i =v dd ? 1-+1 a i li input leakage current v i = 17 v; 100 k series resistor ? 1-+1 a c i input capacitance v i =v ss or v dd -2.05.0pf interrupt output (int ) i ol low-level output current v dd =4.5v; v ol =0.4v 6 - - ma i oh high-level output current v oh =v dd ? 1-+1 a c o output capacitance - 2 5 pf spi and control (sdout, sdin, sclk, cs , int_en) v il low-level input voltage - - 0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i ih high-level input current sdin; v i =v dd = 5.5 v - 20 40 a i ol low-level output current sdout; v ol =0.4v; v dd =4.5v 5 - - ma i oh high-level output current sdout; v oh =v dd ? 0.5 v; v dd =4.5v ? 5 ? 11 - ma c i input capacitance v i =v ss or v dd -25pf c o output capacitance sdout; cs =v dd -46pf
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 16 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 11. dynamic characteristics table 6. dynamic characteristics v dd = 4.5 v to 5.5 v; v ss =0v; t amb = ? 40 c to +125 c; unless otherwise specified. symbol parameter conditions min typ max unit f max maximum input clock frequency - - 5 mhz t r rise time sdout; 10 % to 90 % at 5 v - 35 60 ns t f fall time sdout; 90 % to 10 % at 5 v - 25 50 ns t wh pulse width high sclk 50 - - ns t wl pulse width low sclk 50 - - ns t spilead spi enable lead time cs falling edge to sclk rising edge 50 - - ns t spilag spi enable lag time sclk falling edge to cs rising edge 50 - - ns t su(sdin) sdin set-up time sdin to sclk falling edge 20 - - ns t h(sdin) sdin hold time from sclk falling edge 30 - - ns t en(sdout) sdout enable time from cs low to sdout low-impedance; figure 16 --55ns t dis(sdout) sdout disable time from rising edge of cs to sdout high-impedance; figure 16 --85ns t v(sdout) sdout valid time from rising edge of sclk; figure 17 --55ns t su(sclk) sclk set-up time sclk falling to cs falling 50 - - ns t h(sclk) sclk hold time sclk rising after cs rising 50 - - ns t por power-on reset pulse time time before cs is active after v dd >v por - - 250 ns t rel(int) interrupt release time after cs going low; figure 18 - - 500 ns t v(int) valid time on pin int after inn changes or int_en goes high - 200 800 ns fig 13. timing diagram cs sclk sdin sdout int t spilag t wl t wh high-impedance t spilead msb in msb out 002aac428 t su(sdin) t h(sdin) t en(sdout) t v(sdout) t dis(sdout) t rel(int) 50 % 50 % t su(sclk) t h(sclk)
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 17 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int fig 14. ac waveform for t por timing fig 15. ac waveform for int timing cs sclk sdout msb out 002aad15 8 t por v por 2.5 v 0 v v dd msb ? 1 cs inn int_en 002aaf2 94 t rel(int) state 0 state 1 state 0 int t v(int) t v(int) t rel(int)
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 18 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 12. test information r l = load resistance. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 16. test circuitry for enab le/disable times, sdout (t en(sdout) and t dis(sdout) ) fig 17. test circuitry for switching times, sdout (t v(sdout) ) fig 18. test circuitry for switching times, int pulse generator v o c l 50 pf r l 10 k 002aac58 0 r t v i v dd dut v dd open 10 k pulse generator v o c l 50 pf 002aac58 1 r t v i v dd dut pulse generator v o c l 50 pf r l 10 k 002aac58 2 r t v i v dd dut v dd
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 19 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 13. package outline fig 19. package outline sot355-1 (tssop24) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 112 24 13 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355 -1 a max. 1.1
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 20 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int fig 20. package outline sot994-1 (hwqfn24) references outline version european projection issue date iec jedec jeita sot994-1 - - - mo-220 - - - sot994- 1 07-02-07 07-03-03 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. unit a (1) max mm 0.8 0.05 0.00 0.30 0.18 4.1 3.9 2.25 1.95 4.1 3.9 2.25 1.95 2.5 2.5 0.1 a 1 dimensions (mm are the original dimensions) h wqfn24: plastic thermal enhanced very very thin quad flat package; no leads; 2 4 terminals; body 4 x 4 x 0.75 mm 0 2.5 5 mm scale b c 0.2 d (1) d h e (1) e h e 0.5 e 1 e 2 l 0.5 0.3 v w 0.05 y 0.05 y 1 0.1 b a terminal 1 index area e d detail x a a 1 c b e 2 e 1 e e 1/2 e 1/2 e a c b ? v m c ? w m terminal 1 index area 6 13 12 7 18 24 19 1 l e h d h c y c y 1 x
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 21 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 22 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 21 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 7 and 8 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 21 . table 7. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 8. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 23 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 15. abbreviations msl: moisture sensitivity level fig 21. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 9. abbreviations acronym description assp application specif ic standard product can controller area network cdm charged-device model dut device under test ecu electronic control unit esd electrostatic discharge gpi general purpose input hbm human body model hs-can high-speed controller area network lin local interconnect network mm machine model msb most significant bit pcb printed-circuit board ppap production part approval process rc resistor-capacitor network sbc system basis chip spi serial peripheral interface c microcontroller
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 24 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 16. revision history table 10. revision history document id release date data sheet status change notice supersedes pca9703_1 20100223 product data sheet - -
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 25 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. non-automotive qualified products ? unless the data sheet of an nxp semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive sp ecifications and standards, customer (a) shall use the product without nx p semiconductors? warranty of the document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
pca9703_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 23 february 2010 26 of 27 nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pca9703 18 v tolerant spi 16-bit gpi with maskable int ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 23 february 2010 document identifier: pca9703_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 spi bus operation . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 cs - chip select . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.2 sclk - serial clock input . . . . . . . . . . . . . . . . . 6 7.1.3 sdin - serial data input. . . . . . . . . . . . . . . . . . . 6 7.1.4 sdout - serial data output . . . . . . . . . . . . . . . 6 7.1.5 register access timing . . . . . . . . . . . . . . . . . . . 6 7.1.6 software reset operation. . . . . . . . . . . . . . . . . . 7 7.2 interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.3 interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . 8 7.4 general purpose inputs . . . . . . . . . . . . . . . . . . 8 7.4.1 v il , v ih and switching points. . . . . . . . . . . . . . . 9 8 application design-in information . . . . . . . . . 10 8.1 general application. . . . . . . . . . . . . . . . . . . . . 10 8.2 automotive application . . . . . . . . . . . . . . . . . . 10 8.2.1 sbc wake port extensio n with cyclic biasing . 11 8.2.1.1 uja106x with pca9703, standby. . . . . . . . . . 11 8.2.1.2 uja106x with pca9703, sleep. . . . . . . . . . . . 12 8.2.1.3 uja107x with pca9703 , standby and sleep . 13 8.2.2 application examples including switches to battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 10 static characteristics. . . . . . . . . . . . . . . . . . . . 15 11 dynamic characteristics . . . . . . . . . . . . . . . . . 16 12 test information . . . . . . . . . . . . . . . . . . . . . . . . 18 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 14 soldering of smd packages . . . . . . . . . . . . . . 21 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 21 14.2 wave and reflow soldering . . . . . . . . . . . . . . . 21 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 25 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26 18 contact information . . . . . . . . . . . . . . . . . . . . 26 19 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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Price & Availability of PCA9703PW112

Part #	Manufacturer	Description	Price	BuyNow Qty.
PCA9703PW,112	NXP Semiconductors	IC SPI GPI 16-BIT 24TSSOP	1000: USD0.9089 500: USD0.9624 100: USD1.01 25: USD1.05 1: USD1.07	216

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