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preliminary: this document contains information on a new product. specifications and information contained herein are subject to change without notice. HN58S65A series 64 k eeprom (8-kword 8-bit) ready/ %xv\ function ade-203-691a (z) preliminary rev. 0.3 nov. 1997 description the hitachi HN58S65A series is electrically erasable and programmable rom organized as 8192-word 8-bit. it has realized high speed, low power consumption and high reliability by employing advanced mnos memory technology and c mos process and circuitry technology. they also have a 64-byte page programming function to make their write operations faster. features single supply: 2.2 to 3.6 v access time: 150 ns (max) power dissipation ? active: 10 mw/mhz (typ) ? standby: 36 w (max) on-chip latches: address, data, &( , 2( , :( automatic byte write: 15 ms (max) automatic page write (64 bytes): 15 ms (max) ready/ %xv\ 'dwd polling and toggle bit data protection circuit on power on/off conforms to jedec byte-wide standard reliable cmos with mnos cell technology 10 5 erase/write cycles (in page mode) 10 years data retention software data protection industrial versions (temperature range: C 40 to + 85 c) are also available.
HN58S65A series 2 ordering information type no. access time package HN58S65At-15 150 ns 28-pin plastic tsop(tfp-28db) pin arrangement 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a2 a1 a0 i/o0 i/o1 i/o2 v i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 ss a3 a4 a5 a6 a7 a12 rdy/ busy v we nc a8 a9 a11 oe cc (top view) HN58S65At series 15 16 17 18 19 20 21 22 23 24 25 26 27 28 pin description pin name function a0 to a12 address input i/o0 to i/o7 data input/output 2( output enable &( chip enable :( write enable v cc power supply v ss ground rdy/ %xv\ ready busy nc no connection
HN58S65A series 3 block diagram v v oe ce a5 a0 a6 a12 we cc ss i/o0 i/o7 high voltage generator control logic and timing y decoder x decoder address buffer and latch i/o buffer and input latch y gating memory array data latch rdy/ busy to to to operation table operation &( &( 2( 2( :( :( rdy/ %xv\ %xv\ i/o read v il v il v ih high-z dout standby v ih * 1 high-z high-z write v il v ih v il high-z to v ol din deselect v il v ih v ih high-z high-z write inhibit v ih v il 'dwd polling v il v il v ih v ol dout (i/o7) notes: 1. : dont care
HN58S65A series 4 absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc C0.6 to +7.0 v input voltage relative to v ss vin C0.5* 1 to +7.0* 3 v operating temperature range * 2 topr 0 to +70 c storage temperature range tstg C55 to +125 c notes: 1. vin min : C3.0 v for pulse width 2 50 ns. 2. including electrical characteristics and data retention. 3. should not exceed v cc + 1.0 v. recommended dc operating conditions parameter symbol min typ max unit supply voltage v cc 2.2 3.0 3.6 v v ss 000v input voltage v il C0.3* 1 0.4 v v ih v cc 0.7 v cc + 0.3* 2 v operating temperature topr 0 70 c notes: 1. v il min: C1.0 v for pulse width 50 ns. 2. v ih max: v cc + 1.0 v for pulse width 50 ns. dc characteristics (ta = 0 to + 70c, v cc = 2.2 to 3.6 v) parameter symbol min typ max unit test conditions input leakage current i li 2av cc = 5.5 v, vin = 5.5 v output leakage current i lo 2av cc = 5.5 v, vout = 5.5/0.4 v standby v cc current i cc1 1 to 2 3.5 a &( = v cc i cc2 500 a &( = v ih operating v cc current i cc3 6 ma iout = 0 ma, duty = 100%, cycle = 1 s at v cc = 3.6 v 12 ma iout = 0 ma, duty = 100%, cycle = 150 ns at v cc = 3.6 v output low voltage v ol 0.4 v i ol = 1.0 ma output high voltage v oh v cc 0.8 v i oh = C100 a
HN58S65A series 5 capacitance (ta = 25c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance cin* 1 6 pf vin = 0 v output capacitance cout* 1 12 pf vout = 0 v note: 1. this parameter is sampled and not 100% tested. ac characteristics (ta = 0 to + 70c, v cc = 2.2 to 3.6 v) test conditions input pulse levels : 0.4 v to 2.4 v (v cc = 2.7 to 3.6 v), 0.4 v to 1.9 v (v cc = 2.2 to 2.7 v) input rise and fall time : 2 5 ns input timing reference levels : 0.8, 1.8 v output load : 1ttl gate +100 pf output reference levels : 1.5 v, 1.5 v (v cc = 2.7 to 3.6 v) 1.1 v, 1.1 v (v cc = 2.2 to 2.7 v) read cycle HN58S65A -15 parameter symbol min max unit test conditions address to output delay t acc 150 ns &( = 2( = v il , :( = v ih &( to output delay t ce 150 ns 2( = v il , :( = v ih 2( to output delay t oe 10 80 ns &( = v il , :( = v ih address to output hold t oh 0ns &( = 2( = v il , :( = v ih 2( ( &( ) high to output float* 1 t df 080ns &( = v il , :( = v ih
HN58S65A series 6 write cycle parameter symbol min* 2 typ max unit test conditions address setup time t as 0 ns address hold time t ah 150 ns &( to write setup time ( :( controlled) t cs 0 ns &( hold time ( :( controlled) t ch 0 ns :( to write setup time ( &( controlled) t ws 0 ns :( hold time ( &( controlled) t wh 0 ns 2( to write setup time t oes 0 ns 2( hold time t oeh 0 ns data setup time t ds 150 ns data hold time t dh 0 ns :( pulse width ( :( controlled) t wp 200 ns &( pulse width ( &( controlled) t cw 200 ns data latch time t dl 200 ns byte load cycle t blc 0.4 30 s byte load window t bl 100 s write cycle time t wc 15* 3 ms time to device busy t db 120 ns write start time t dw 0* 4 ns notes: 1. t df is defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. use this device in longer cycle than this value. 3. t wc must be longer than this value unless polling techniques or rdy/ %xv\ are used. this device automatically completes the internal write operation within this value. 4. next read or write operation can be initiated after t dw if polling techniques or rdy/ %xv\ are used. 5. a6 through a12 are page addresses and these addresses are latched at the first falling edge of :( . 6. a6 through a12 are page addresses and these addresses are latched at the first falling edge of &( . 7. see ac read characteristics.
HN58S65A series 7 timing waveforms read timing waveform address ce oe we data out high data out valid t acc t ce t oe t oh t df
HN58S65A series 8 byte write timing waveform(1) ( :( controlled) address ce we oe din rdy/ busy t wc t ch t ah t cs t as t wp t oeh t bl t oes t ds t dh t db high-z high-z t dw
HN58S65A series 9 byte write timing waveform(2) ( &( controlled) address ce we oe din rdy/ busy t wc t ah t ws t as t oeh t wh t oes t ds t dh t db t cw t bl t dw high-z high-z
HN58S65A series 10 page write timing waveform(1) ( :( controlled) address a0 to a12 we ce oe din rdy/ busy t as t ah t bl t wc t oeh t dh t db t oes t ch t cs t wp t dl t blc t ds t dw high-z high-z *5
HN58S65A series 11 page write timing waveform(2) ( &( controlled) address a0 to a12 we ce oe din rdy/ busy t as t ah t bl t wc t oeh t dh t db t oes t wh t ws t cw t dl t blc t ds t dw high-z high-z *6 'dwd 'dwd polling timing waveform t ce t oeh t wc t dw t oes address ce we oe i/o7 t oe din x an an dout x dout x *7 *7 an
HN58S65A series 12 toggle bit this device provide another function to determine the internal programming cycle. if the eeprom is set to read mode during the internal programming cycle, i/o6 will charge from 1 to 0 (toggling) for each read. when the internal programming cycle is finished, toggling of i/o6 will stop and the device can be accessible for next read or program. toggle bit waveform notes: 1. i/o6 beginning state is 1. 2. i/o6 ending state will vary. 3. see ac read characteristics. 4. any address location can be used, but the address must be fixed. we t oes oe ce dout i/o6 dout dout dout next mode t oe t ce t dw t wc t oeh *1 *2 *2 address *3 *3 *4 din
HN58S65A series 13 software data protection timing waveform(1) (in protection mode) v ce we address data 1555 aa 0aaa 55 1555 a0 t blc t wc cc write address write data software data protection timing waveform(2) (in non-protection mode) v ce we address data t wc cc normal active mode 1555 aa 0aaa 55 1555 80 1555 aa 0aaa 55 1555 20
HN58S65A series 14 functional description automatic page write page-mode write feature allows 1 to 64 bytes of data to be written into the eeprom in a single write cycle. following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. each additional byte load cycle must be started within 30 s from the preceding falling edge of :( or &( . when &( or :( is kept high for 100 s after data input, the eeprom enters write mode automatically and the input data are written into the eeprom. 'dwd 'dwd polling 'dwd polling indicates the status that the eeprom is in a write cycle or not. if eeprom is set to read mode during a write cycle, an inversion of the last byte of data outputs from i/o7 to indicate that the eeprom is performing a write operation. rdy/ %xv\ %xv\ signal rdy/ %xv\ signal also allows status of the eeprom to be determined. the rdy/ %xv\ signal has high impedance except in write cycle and is lowered to v ol after the first write signal. at the end of a write cycle, the rdy/ %xv\ signal changes state to high impedance. :( :( , &( &( pin operation during a write cycle, addresses are latched by the falling edge of :( or &( , and data is latched by the rising edge of :( or &( . write/erase endurance and data retention time the endurance is 10 5 cycles in case of the page programming and 10 4 cycles in case of the byte programming (1% cumulative failure rate). the data retention time is more than 10 years when a device is page-programmed less than 10 4 cycles.
HN58S65A series 15 data protection 1. data protection against noise on control pins ( &( , 2( , :( ) during operation during readout or standby, noise on the control pins may act as a trigger and turn the eeprom to programming mode by mistake. to prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 15 ns or less. be careful not to allow noise of a width of more than 15 ns on the control pins. we ce oe v 0 v v 0 v 15 ns max ih ih 2. data protection at v cc on/off when v cc is turned on or off, noise on the control pins generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to program mode by mistake. to prevent this unintentional programming, the eeprom must be kept in an unprogrammable state while the cpu is in an unstable state. note: the eeprom should be kept in unprogrammable state during v cc on/off by using cpu reset signal. v cc cpu reset unprogrammable unprogrammable * *
HN58S65A series 16 (1) protection by &( , 2( , :( to realize the unprogrammable state, the input level of control pins must be held as shown in the table below. &( v cc 2( v ss :( v cc : dont care. v cc : pull-up to v cc level. v ss : pull-down to v ss level. 3. software data protection to prevent unintentional programming caused by noise generated by external circuits, this device has the software data protection function. in software data protection mode, 3 bytes of data must be input before write data as follows. and these bytes can switch the non-protection mode to the protection mode. sdp is enabled if onry the 3 byte code is input. data aa 55 a0 write data } address 1555 0aaa 1555 write address normal data input software data protection mode can be canceled by inputting the following 6 bytes. after that, this device turns to the non-protection mode and can write data normally. but when the data is input in the canceling cycle, the data cannot be written. data aa 55 80 aa 55 20 address 1555 0aaa 1555 1555 0aaa 1555 the software data protection is not enabled at the shipment. note: there are some differences between hitachis and other companys for enable/disable sequence of software data protection. if there are any questions , please contact with hitachi sales offices.
HN58S65A series 17 package dimensions HN58S65At series (tfp-28db) 0.10 m 0.55 8.00 0.22 0.08 13.40 0.30 0.17 0.05 0.13 1.20 max 11.80 0 ?5 28 1 14 15 8.20 max 0.10 +0.07 ?.08 0.50 0.10 0.80 0.45 max hitachi code jedec eiaj weight (reference value) tfp-28db ? ? 0.23 g 0.20 0.06 0.15 0.04 unit: mm dimension including the plating thickness base material dimension
HN58S65A series 18 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca. 94005-1897 u s a tel: 800-285-1601 fax:303-297-0447 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan.
HN58S65A series 19 revision record rev. date contents of modification drawn by approved by 0.0 dec. 5, 1996 initial issue y. nagai t. wada 0.1 mar. 13, 1997 change of page size: 32 byte to 64 byte y. nagai k. furusawa 0.2 aug. 29, 1997 timing waveform read timing waveform: correct error functional description data protection: addition of description y. nagai t. muto 0.3 nov.1997 change of subtitle

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