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pckv857 70190 mhz differential 1:10 clock driver product data supersedes data of 2001 dec 03 2002 sep 13 integrated circuits
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2 2002 sep 13 features ? esd classification testing is done to jedec standard jesd22. protection exceeds 2000 v to hbm per method a114. ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? optimized for clock distribution in ddr (double data rate) sdram applications as per jedec specifications ? 1-to-10 differential clock distribution ? very low skew ( < 100 ps) and jitter ( < 100 ps) ? operation from 2.2 v to 2.7 v av dd and 2.3 v to 2.7 v v dd ? sstl_2 interface clock inputs and outputs ? cmos control signal input ? test mode enables buffers while disabling pll ? low current power-down mode ? tolerant of spread spectrum input clock ? full ddr solution provided when used with sstl16877 or sstv16857 ? designed for ddr 200 and 266 dimm applications ? available in tssop-48, tvsop-48, and vfbga56 (8 no connects) packages description the pckv857 is a high-performance, low-skew, low-jitter zero delay buffer designed for 2.5 v v dd and 2.5 v av dd operation and differential data input and output levels. the pckv857 is a zero delay buffer that distributes a differential clock input pair (clk, clk ) to ten differential pairs of clock outputs (y[0:9], y[0:9] ) and one differential pair feedback clock outputs (fb out , fb out ) . the clock outputs are controlled by the clock inputs (clk, clk ), the feedback clocks (fb in , fb in ), and the analog power input (av dd ). when pwrdwn is high, the outputs switch in phase and frequency with clk. when pwrdwn is low, all outputs are disabled to high impedance state (3-state), and the pll is shut down (low power mode). the device also enters the low power mode when the input frequency falls below 20 mhz. an input frequency detection circuit will detect the low frequency condition and after applying a > 20 mhz input signal, the detection circuit turns on the pll again and enables the outputs. when av dd is grounded, the pll is turned off and bypassed for test purposes. the pckv857 is also able to track spread spectrum clocking for reduced emi. the pckv857 is characterized for operation from 0 to +70 c. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 21 22 23 24 41 42 43 44 45 46 47 48 gnd y 0 y 0 v ddq y 1 y 1 gnd y 2 gnd y 2 v ddq v ddq clk clk v ddq av dd agnd gnd y 3 y 3 v ddq y 4 y 4 gnd gnd y 5 y 5 v ddq y 6 y 6 gnd gnd y 7 y 7 v ddq pwrdwn fb in fb in v ddq fb out fb out gnd y 8 y 8 v ddq y 9 y 9 sw00691 gnd ordering information packages temperature range order code drawing number 48-pin plastic tssop 0 to +70 c pckv857dgg sot362-1 48-pin plastic tssop (tvsop) 0 to +70 c pckv857dgv sot480-1 56-ball plastic vfbga 1 0 to +70 c pckv857ev sot702-1 note: 1. 48 balls are connected, 8 balls are no-connects.
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 3 pin description pins symbol description 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 gnd sstl_2 ground pins 2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29, 30, 32, 33, 39, 40, 43, 44, 46, 47 y n , y n , fb out , fb out sstl_2 differential outputs 4, 11, 12, 15, 21, 28, 34, 38, 46 v ddq sstl_2 power pins 13, 14, 35, 36 clk in , clk in , fb in , fb in sstl_2 differential inputs 16 av dd analog power 17 agnd analog ground 37 pwrdwn power-down control input ball configuration 123456 a b c d e f g h j k sw00951 gnd gnd gnd agnd gnd gnd gnd gnd gnd gnd gnd v dd v dd v dd v dd av dd v dd v dd v dd v dd v dd nc nc nc nc nc nc nc nc clk clk fb out fb out fb in fb in pwrdwn y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 4 function table inputs outputs pll on/off pwrdwn clk clk y n y n fb out fb out pll on/off l l h z z z 1 z 1 off l h l z z z 1 z 1 off h l h l h l h on h h l h l h l on x 2 < 20 mhz < 20 mhz z z z 1 z 1 off notes: h = high voltage level l = low voltage level z = high impedance off-state x = don't care 1. subject to change. may cause conflict with fb in pins. 2. additional feature that senses when the clock input is less than 20 mhz and places the part in sleep mode. block diagram pll 37 pwrdwn 13 clk 14 clk 36 fb in 35 fb in 16 av dd 3 y 0 2 y 0 5 y 1 6 y 1 10 y 2 9 y 2 20 y 3 19 y 3 22 y 4 23 y 4 46 y 5 47 y 5 44 y 6 43 y 6 39 y 7 40 y 7 29 y 8 30 y 8 27 y 9 28 y 9 32 fb out 33 fb out sw00692
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 5 absolute maximum ratings 1 symbol parameter condition limits unit symbol parameter condition min max unit v ddq supply voltage range 0.5 3.6 v av dd supply voltage range 0.5 3.6 v v i input voltage range see notes 2 and 3 0.5 v ddq + 0.5 v v o output voltage range see notes 2 and 3 0.5 v ddq + 0.5 v i ik input clamp current v i < 0 or v i >v ddq e 50 ma i ok output clamp current v o < 0 or v o >v ddq e 50 ma i o continuous output current v o = 0 to v ddq e 50 ma continuous current to gnd or v ddq e 100 ma t stg storage temperature range 65 + 150 c notes: 1. stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operati ng conditionso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. this value is limited to 3.6 v maximum. recommended operating conditions 1 symbol parameter condition limits unit symbol parameter condition min typ max unit v ddq supply voltage range 2.3 e 2.7 v av dd supply voltage range 2.2 e 2.7 v v il low level input volta g e clk, clk , fb in , fb in e e v ddq /2 - 0.18 v il g pwrdwn - 0.3 e 0.7 v ih hi g h level input volta g e clk, clk , fb in , fb in v ddq /2 + 0.18 e e v ih gg pwrdwn 1.7 e v ddq + 0.3 dc input signal voltage note 2 - 0.3 e v ddq v v dc differential input signal voltage clk, fb in note 3 0.36 e v ddq + 0.6 v v id ac differential input signal voltage clk, fb in note 3 0.7 e v ddq + 0.6 v v ox output differential cross-voltage note 4 v ddq /2 - 0.2 v ddq /2 v ddq /2 + 0.2 v v ix input differential cross-voltage note 4 v ddq /2 - 0.2 e v ddq /2 + 0.2 v i oh high-level output current e e - 12 ma i ol low-level output current e e 12 ma sr input slew rate 1 e 4 v/ns t amb operating free-air temperature 0 e 70 c notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential input signal voltage specifies the differential voltage |vtr vcp| required for switching, where vtr is the tru e input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v cc and is the voltage at which the differential signals must be crossing.
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 6 dc electrical characteristics over recommended operating conditions. voltages are referenced to gnd (ground = 0 v). symbol parameter test conditions limits unit symbol parameter test conditions min typ max unit v ik input voltage, all inputs v ddq = 2.3 v, i i = 18 ma e e - 1.2 v v o high level out p ut voltage v ddq = min to max, i oh = 1 ma v ddq - 0.1 e e v v oh high - le v el o u tp u t v oltage v ddq = 2.3 v, i oh = 12 ma 1.7 e e v v o low level out p ut voltage v ddq = min to max, i ol = 1 ma e e 0.1 v v ol lo w- le v el o u tp u t v oltage v ddq = 2.3 v, i ol = 12 ma e e 0.6 v i i input current v ddq = 2.7 v, v i = 0 v to 2.7 v e e 10 m a i oz high-impedance-state output current v ddq = 2.7 v, v o = v ddq or gnd e e 10 m a i ddpd power-down current on v ddq + av dd clk and clk = 0 mhz, pwrdwn = low; s of i dd and ai dd e 30 100 m a i dd dynamic current on v ddq f o = 67 mhz to 190 mhz e 200 300 ma ai dd supply current on av dd f o = 67 mhz to 190 mhz e 8 10 ma c i input capacitance v cc = 2.5 v, v i = v cc or gnd 2 2.8 3 pf note: 1. this is intended to operate in the sstl_2 type iv unterminated mode without series resistors on the outputs. 2. all typical values are at respective nominal v ddq . 3. differential cross-point voltage is expected to track variations of v ddq and is the voltage at which the differential signals must be crossing. timing requirements over recommended ranges of supply voltage and operating free-air temperature. symbol parameter min max unit f ck operating clock frequency 60 190 mhz input clock duty cycle 40 60 % stabilization time 1 100 e m s note: 1. time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal after power- up.
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 7 ac characteristics gnd = 0 v; t r = t f 2.5 ns; c l = 50 pf; r l = 1 k w symbol parameter waveform condition limits unit symbol parameter waveform condition min typ max unit t (o) static phase offset figure 1 150 0 150 ps t sk(o) output clock skew figure 2 e e 75 ps t slr(o) output clock skew rate figure 3 1 e 2 v/ns t jit(per) jitter (period) figure 4 f o = 67 mhz to 200 mhz 75 e 75 ps t jit(cc) jitter (cycle-to-cycle) figure 5 f o = 67 mhz to 200 mhz 75 e 75 ps t jit(hper) half-period jitter figure 6 100 e 100 ps t plh 1 low to high level propagation delay test mode/clk to any output e 3.7 e ns t phl 1 high to low level propagation delay test mode/clk to any output e 3.7 e ns note: 1. refers to transition of noninverting output. the pll clock distribution device and sstl registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation sw00688 sdram sdram sdram sdram sdram sdram sdram sdram sdram sstl16877 or sstv16857 pckv857 front side sstl16877 or sstv16857
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 8 ac waveforms sw00882 t (o) = s 1 n =n t (o)n n t (o)n t (o)n + 1 (n is a large number of samples) clk clk fb in fb in figure 1. static phase offset sw00883 t sk(o) yx yx yx , fb out yx, fb out figure 2. output skew 80% 80% 20% 20% clock inputs and outputs t slr(i) , t slr(o) t slr(i) , t slr(o) v id , v od sw00886 figure 3. input and output slew rates
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 9 f o yx , fb out yx, fb out t cycle n yx , fb out yx, fb out 1 t jit(per) = t cycle n f o 1 sw00884 figure 4. period jitter t cycle n t cycle n + 1 sw00881 t jit(cc) = t cycle n t cycle n+1 yx , fb out yx, fb out figure 5. cycle-to-cycle jitter f o yx , fb out yx, fb out t half period n 1 t jit(hper) = t half period n 2*f o 1 sw00885 t half period n + 1 figure 6. half-period jitter skew any two outputs sw00396 figure 7. skew between any two outputs.
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 10 t 1 t 2 45% t 1 t 1 t 2 55% sw00397 figure 8. duty cycle limits and measurement test circuit pckv857 z = 60 w z = 60 w z = 50 w z = 50 w r = 10 w r = 10 w r = 50 w r = 50 w c = 14 pf c = 14 pf v dd /2 v dd /2 v tt v tt scope v dd /2 v dd /2 note: v tt = gnd sw00880 figure 9. output load test circuit
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 11 tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 12 tssop48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm sot480-1
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 13 vfbga56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm sot702-1
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 14 revision history rev date description _4 2002 sep 06 product data (9397 750 10343); fourth version supersedes product data 2001 dec 03. engineering change notice 853-2242 28874 (2002 sep 09). modifications: add new package option (vfbga) to existing product data sheet. _3 2001 dec 03 product data (9397 750 09244); third version
philips semiconductors product data pckv857 70190 mhz differential 1:10 clock driver 2002 sep 13 15 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 2002 all rights reserved. printed in u.s.a. date of release: 09-02 document order number: 9397 750 10343 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change notification (cpcn) procedure snw-sq-650a. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com.

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