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rev. 1.2 12/09 copyright ? 2009 by silicon laboratori es si8450/51/52/55 si8450/51/52/55 iso pro l ow p ower f ive -c hannel d igital i solator features applications safety regulatory approvals description silicon lab's family of ultra low power digital isolators are cmos devices that employ an rf coupler to transmit di gital information across an isolation barrier. very high speed operation at low power levels is achieved. these devices are available in 16-pin wide-body and narrow-body soic packages. two speed grade options (1 and 150 mbps) are available and achieve worst- case propagation delays of less than 10 ns. block diagram ? high-speed operation: dc to 150 mbps ? low propagation delay: <10 ns worst case ? wide operating supply voltage: 2.70?5.5 v ? ultra low power (typical) 5 v operation: ?? <1.6 ma per channel at 1 mbps ?? <1.9 ma per channel at 10 mbps ?? <6 ma per channel at 100 mbps 2.70 v operation: ?? <1.4 ma per channel at 1 mbps ?? <1.7 ma per channel at 10 mbps ?? <4 ma per channel at 100 mbps ? precise timing (typical): ?? 1.5 ns pulse width distortion ?? 0.5 ns channel-channel skew ?? 2 ns propagation delay skew ? up to 2500 v rms isolation ? transient immunity: 25 kv/s ? tri-state outputs with enable control ? dc correct ? no start-up initialization required ? 15 s startup time ? high temperature operation: 125 c at 150 mbps ? wide body and narrow body soic- 16 packages ? rohs-compliant ? isolated switch mode supplies ? isolated adc, dac ? motor control ? power factor correction systems ? ul 1577 recognized ?? 2500 v rms for 1 minute ? csa component notice 5a approval ?? iec 60950, 61010 approved ? vde certification conformity ?? iec 60747-5-2 (vde0884 part 2) si8451 si8452 b1 a1 a3 a4 a2 b3 b4 b2 si8450/55 a1 a3 a4 a2 b3 b4 b2 b1 a1 a3 a4 a2 b3 b4 b2 b1 a5 a5 b5 b5 a5 b5 nc en2/nc en1 en2 en1 en2 patents pending pin assignments v dd1 a1 a3 a4 en1/nc gnd1 a2 1 2 3 4 5 6 7 8 top view (si8450/51/52) v dd2 b2 b1 b4 b3 gnd2 en2 9 12 11 10 13 14 15 16 wide body soic narrow body soic v dd1 a1 a3 a4 en1/nc gnd1 a2 1 2 3 4 5 6 7 8 v dd2 b2 b1 b4 b3 gnd2 en2 9 12 11 10 13 14 15 16 a5 b5 a5 b5 top view (si8450/51/52)
si8450/51/52/55 2 rev. 1.2
si8450/51/52/55 rev. 1.2 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2. eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 3.3. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4. errata and design migration guid elines (revision a only) . . . . . . . . . . . . . . . . . . . . . . 26 4.1. enable pin causes outputs to go low (revision a only) . . . . . . . . . . . . . . . . . . . . 26 4.2. power supply bypass capacitors (revision a only) . . . . . . . . . . . . . . . . . . . . . . . .26 4.3. latch up immunity (rev ision a only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5. pin descriptions (si8450/ 51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6. pin descriptions (si8455) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8. package outline: 16-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9. landing pattern: 16- pin wide-body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10. package outline: 16-pi n narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11. landing pattern: 16-pin na rrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12. top marking: 16-pin wide b ody soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 13. top marking: 16-pin narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
si8450/51/52/55 4 rev. 1.2 1. electrical specifications table 1. electrical characteristics (v dd1 =5v10%, v dd2 =5v10%, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?8 5? ? enable input high current i enh v enx = v ih ?2 . 0? a enable input low current i enl v enx = v il ?2 . 0? a dc supply current (all inputs 0 v or at supply) si8450ax, bx, si8455bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 ma si8451ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 2.0 3.0 6.0 4.1 3.0 4.5 9.0 6.2 ma si8452ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 2.3 2.7 5.4 4.7 3.5 4.1 8.1 7.1 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8450ax, bx, si8455bx v dd1 v dd2 ? ? 4.3 3.5 6.5 5.3 ma si8451ax, bx v dd1 v dd2 ? ? 4.1 4.0 6.2 6.0 ma si8452ax, bx v dd1 v dd2 ? ? 4.1 4.0 6.2 6.0 ma notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channe l resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. see "4. errata and design migration guidelines (revision a only)" on page 26 for more details. 4. start-up time is the time period from the applic ation of power to valid data at the output.
si8450/51/52/55 rev. 1.2 5 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8450bx, si8455bx v dd1 v dd2 ? ? 4.3 4.8 6.5 6.7 ma si8451bx v dd1 v dd2 ? ? 4.4 5.0 6.2 7.0 ma si8452bx v dd1 v dd2 ? ? 4.6 4.8 6.4 6.7 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8450bx, si8455bx v dd1 v dd2 ? ? 4.6 24 6.9 30 ma si8451bx v dd1 v dd2 ? ? 8.6 20.4 10.8 25.5 ma si8452bx v dd1 v dd2 ? ? 12.6 16.5 15.8 20.6 ma timing charac teristics si845xax maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl , t plh see figure 2 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 25 ns propagation delay skew 2 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns table 1. electrical characteristics (continued) (v dd1 =5v10%, v dd2 =5v10%, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channe l resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. see "4. errata and design migration guidelines (revision a only)" on page 26 for more details. 4. start-up time is the time period from the applic ation of power to valid data at the output.
si8450/51/52/55 6 rev. 1.2 figure 1. enable timing diagram si845xbx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 2 3.0 6.0 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? 1.5 2.5 ns propagation delay skew 2 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l =15pf see figure 2 ?3.85.0ns output fall time t f c l =15pf see figure 2 ?2.83.7ns common mode transient immunity cmti v i =v dd or 0 v ? 25 ? kv/s enable to data valid 3 t en1 see figure 1 ? 5.0 8.0 ns enable to data tri-state 3 t en2 see figure 1 ? 7.0 9.2 ns start-up time 3,4 t su ?1 54 0 s table 1. electrical characteristics (continued) (v dd1 =5v10%, v dd2 =5v10%, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channe l resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. see "4. errata and design migration guidelines (revision a only)" on page 26 for more details. 4. start-up time is the time period from the applic ation of power to valid data at the output. enable outputs t en1 t en2
si8450/51/52/55 rev. 1.2 7 figure 2. propagation delay timing typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v
si8450/51/52/55 8 rev. 1.2 table 2. electrical characteristics (v dd1 = 3.3 v10%, v dd2 = 3.3 v10%, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 3.1 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?8 5? ? enable input high current i enh v enx = v ih ?2 . 0? a enable input low current i enl v enx = v il ?2 . 0? a dc supply current (all inputs 0 v or at supply) si8450ax, bx, si8455bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 ma si8451ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 2.0 3.0 6.0 4.1 3.0 4.5 9.0 6.2 ma si8452ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 2.3 2.7 5.4 4.7 3.5 4.1 8.1 7.1 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8450ax, bx, si8455bx v dd1 v dd2 ? ? 4.3 3.5 6.5 5.3 ma si8451ax, bx v dd1 v dd2 ? ? 4.1 4.0 6.2 6.0 ma si8452ax, bx v dd1 v dd2 ? ? 4.1 4.0 6.2 6.0 ma notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. see "4. errata and design migration guidelines (revision a only)" on page 26 for more details. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si8450/51/52/55 rev. 1.2 9 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8450bx, si8455bx v dd1 v dd2 ? ? 4.3 4.8 6.5 6.7 ma si8451bx v dd1 v dd2 ? ? 4.4 5.0 6.2 7.0 ma si8452bx v dd1 v dd2 ? ? 4.6 4.8 6.4 6.7 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8450bx, si8455bx v dd1 v dd2 ? ? 4.4 16.8 6.6 21 ma si8451bx v dd1 v dd2 ? ? 6.9 14.5 8.6 18.1 ma si8452bx v dd1 v dd2 ? ? 9.5 12 11.9 15 ma timing characteristics si845xax maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl ,t plh see figure 2 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 25 ns propagation delay skew 2 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns table 2. electrical characteristics (continued) (v dd1 = 3.3 v10%, v dd2 = 3.3 v10%, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. see "4. errata and design migration guidelines (revision a only)" on page 26 for more details. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si8450/51/52/55 10 rev. 1.2 si845xbx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 2 3.0 6.0 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? 1.5 2.5 ns propagation delay skew 2 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l = 15 pf see figure 2 ?4.36.1ns output fall time t f c l = 15 pf see figure 2 ?3.04.3ns common mode transient immunity at logic low output cmti v i =v dd or 0 v ? 25 ? kv/s enable to data valid 3 t en1 see figure 1 ? 5.0 8.0 ns enable to data tri-state 3 t en2 see figure 1 ? 7.0 9.2 ns start-up time 3,4 t su ?1 54 0 s table 2. electrical characteristics (continued) (v dd1 = 3.3 v10%, v dd2 = 3.3 v10%, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. see "4. errata and design migration guidelines (revision a only)" on page 26 for more details. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si8450/51/52/55 rev. 1.2 11 table 3. electrical characteristics 1 (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 2.3 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 2 z o ?8 5? ? enable input high current i enh v enx = v ih ?2 . 0? a enable input low current i enl v enx = v il ?2 . 0? a dc supply current (all inputs 0 v or at supply) si8450ax, bx, si8455bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 ma si8451ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 2.0 3.0 6.0 4.1 3.0 4.5 9.0 6.2 ma si8452ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 2.3 2.7 5.4 4.7 3.5 4.1 8.1 7.1 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8450ax, bx, si8455bx v dd1 v dd2 ? ? 4.3 3.5 6.5 5.3 ma si8451ax, bx v dd1 v dd2 ? ? 4.1 4.0 6.2 6.0 ma si8452ax, bx v dd1 v dd2 ? ? 4.1 4.0 6.2 6.0 ma notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation del ay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. see "4. errata and design migration guidelines (revision a only)" on page 26 for more details. 5. start-up time is the time period from the a pplication of power to valid data at the output.
si8450/51/52/55 12 rev. 1.2 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8450bx, si8455bx v dd1 v dd2 ? ? 4.3 4.8 6.5 6.7 ma si8451bx v dd1 v dd2 ? ? 4.4 5.0 6.2 7.0 ma si8452bx v dd1 v dd2 ? ? 4.6 4.8 6.4 6.7 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8450bx, si8455bx v dd1 v dd2 ? ? 4.3 13.3 6.5 16.6 ma si8451bx v dd1 v dd2 ? ? 6.2 11.7 7.8 14.6 ma si8452bx v dd1 v dd2 ? ? 8.0 9.9 10 12.4 ma timing characteristics si845xax maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl ,t plh see figure 2 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 25 ns propagation delay skew 3 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns table 3. electrical characteristics 1 (continued) (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation del ay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. see "4. errata and design migration guidelines (revision a only)" on page 26 for more details. 5. start-up time is the time period from the a pplication of power to valid data at the output.
si8450/51/52/55 rev. 1.2 13 si845xbx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 2 3.0 6.0 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? 1.5 2.5 ns propagation delay skew 3 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l =15pf see figure 2 ?4.86.5ns output fall time t f c l =15pf see figure 2 ?3.24.6ns common mode transient immunity at logic low output cmti v i =v dd or 0 v ? 25 ? kv/s enable to data valid 4 t en1 see figure 1 ? 5.0 8.0 ns enable to data tri-state 4 t en2 see figure 1 ? 7.0 9.2 ns start-up time 4,5 t su ?1 54 0 s table 3. electrical characteristics 1 (continued) (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 oc; applies to narrow and wide-body soic packages) parameter symbol test condition min typ max unit notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation del ay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. see "4. errata and design migration guidelines (revision a only)" on page 26 for more details. 5. start-up time is the time period from the a pplication of power to valid data at the output.
si8450/51/52/55 14 rev. 1.2 table 4. absolute maximum ratings 1 parameter symbol min typ max unit storage temperature 2 t stg ?65 ? 150 oc ambient temperature under bias t a ?40 ? 125 oc supply voltage (revision a) 3 v dd1 , v dd2 ?0.5 ? 5.75 v supply voltage (revision b) 3 v dd1 , v dd2 ?0.5 ? 6.0 v input voltage v i ?0.5 ? v dd + 0.5 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive channel i o ??10ma lead solder temperature (10 s) ? ? 260 oc maximum isolation voltage (1 s) ? ? 3600 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. vde certifies storage temper ature from ?40 to 150 c. 3. see "7. ordering guide" on page 29 for more information. table 5. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature* t a 150 mbps, 15 pf, 5 v ?40 25 125 oc supply voltage v dd1 2.70 ? 5.5 v v dd2 2.70 ? 5.5 v *note: the maximum ambient temperature is dependent on data freque ncy, output loading, number of operating channels, and supply voltage. table 6. regulatory information* csa the si845x is certified under csa component acceptanc e notice 5a. for more details, see file 232873. vde the si845x is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. ul the si845x is certified under ul15 77 component recognition program. for more details, see file e257455. *note: regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. for more information, see "7. ordering guide" on page 29.
si8450/51/52/55 rev. 1.2 15 table 7. insulation and safety-related specifications parameter symbol test condition value unit wb soic-16 nb soic-16 nominal air gap (clearance) 1 l(io1) 8.0 4.9 mm nominal external tracking (creepage) 1 l(io2) 8.0 4.01 mm minimum internal gap (internal clearance) 0.008 0.008 mm tracking resistance (comparative tracking index) cti din iec 60112/vde 0303 part 1 >175 >175 v resistance (input-output) 2 r io 10 12 10 12 ? capacitance (input-output) 2 c io f = 1 mhz 2.0 2.0 pf input capacitance 3 c i 4.0 4.0 pf notes: 1. the values in this table correspond to the nominal creepage and clearance values as detailed in ?8. package outline: 16-pin wide body soic? and ?10. package outline: 16-pin narrow body soic?. vde certifies the clearance and creepage limits as 4.7 mm minimum for the nb soic-16 package and 8.5 mm minimum for the wb soic-16 package. ul does not impose a clearance and creepage minimum for co mponent level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic-16 package and 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si84xx is converted into a 2-terminal device. pins 1?8 are shorted together to form the first terminal and pi ns 9?16 are shorted together to form th e second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 8. iec 60664-1 (vde 0884 part 2) ratings parameter test conditions specification basic isolation group material group iiia installation classification rated mains voltages < 150 v rms i-iv rated mains voltages < 300 v rms i-iii rated mains voltages < 400 v rms i-ii
si8450/51/52/55 16 rev. 1.2 table 9. iec 60747-5-2 insulation characteristics for si845xxb* parameter symbol test condition characteristic unit maximum working insulation voltage v iorm 560 vpeak input to output test voltage v pr method a after environmental tests subgroup 1 (v iorm x1.6=v pr , t m =60sec, partial discharge < 5 pc) 896 vpeak method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1050 after input and/or safety test subgroup 2/3 (v iorm x1.2=v pr , t m =60sec, partial discharge < 5 pc) 672 highest allowable over voltage (transient overvoltage, t tr =10 sec) v tr 4000 vpeak pollution degree (din vde 0110, table 1) 2 insulation resistance at t s , v io =500v r s >10 9 ? *note: this isolator is suitable for basic electrical isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the si845x prov ides a climate classification of 40/125/21. table 10. iec safety limiting values 1 parameter symbol tes t condition min typ max unit wb soic-16 nb soic-16 case temperature t s ? ? 150 150 c safety input, output, or supply current i s ? ja = 100 c/w (wb soic-16), 105 c/w (nb soic-16), v i =5.5v, t j =150c, t a =25c ? ? 220 215 ma device power dissipation 2 p d ? ? 415 415 mw notes: 1. maximum value allowed in the event of a failure; also see the thermal derating curve in figure 3. 2. the si845x is tested with vdd1 = vdd2 = 5.5 v, tj = 150 oc , cl = 15 pf, input a 150 mbp s 50% duty cycle square wave.
si8450/51/52/55 rev. 1.2 17 figure 3. (wb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 figure 4. (nb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 11. thermal characteristics parameter symbol test condition min typ max unit wb soic-16 nb soic-16 ic junction-to-air thermal resistance ? ja ? 100 105 ? oc/w 0 200 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 450 300 370 220 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.6 v v dd1 , v dd2 = 5.5 v 0 200 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 430 300 360 215 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.6 v v dd1 , v dd2 = 5.5 v
si8450/51/52/55 18 rev. 1.2 table 12. si845x logic operation table v i input 1,2 en input 1,2,3,4 vddi state 1,5,6 vddo state 1,5,6 v o output 1,2 comments h h or nc p p h enabled, normal operation. lh or nc p p l x l p p hi-z or l 7 disabled. x h or nc up p l upon transition of vddi from unpowered to pow- ered, v o returns to the same state as v i in less than 1 s. x l up p hi-z or l 7 disabled. x x p up undetermined upon transition of vddo from unpowered to pow- ered, v o returns to the same state as v i within 1 s, if en is in either th e h or nc state. upon tran- sition of vddo from unpowered to powered, v o returns to hi-z within 1 s if en is l. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. en is the enable control input located on the same output side. 2. x = not applicable; h = logic high; l = logic low; hi-z = high impedance. 3. it is recommended that the enable inputs be connected to an external logic high or low level when the si845x is operating in noisy environments. 4. no connect (nc) replaces en1 on si8450. no connects are no t internally connected and can be left floating, tied to vdd, or tied to gnd. 5. "powered" state (p) is defined as 2.70 v < vdd < 5.5 v. 6. "unpowered" state (up) is defined as vdd = 0 v. 7. when using the enable pin (en) function, the output pin state is driven to a logic low state when the en pin is disabled (en = 0) in revision a. revision b outputs go into a high-impedance state when the en pin is disabled (en = 0). see "4. errata and design migration guidelines (revision a only)" on page 26 for more details.
si8450/51/52/55 rev. 1.2 19 table 13. enable input truth table 1 p/n en1 1,2 en2 1,2 operation si8450 ? h outputs b1, b2, b3, b4, b5 are enabled and follow input state. ? l outputs b1, b2, b3, b4, b5 are disabled and logic low or in high impedance state. 3 si8451 h x output a5 enabled and follow input state. l x output a5 disabled and logic low or in high impedance state. 3 x h outputs b1, b2, b3, b4 are enabled and follow input state. x l outputs b1, b2, b3, b4 are disabled and logic low or in high impedance state. 3 si8452 h x outputs a4 and a5 are enabled and follow input state. l x outputs a4 and a5 are disabled and logic low or in high impedance state. 3 x h outputs b1, b2, b3 are enabled and follow input state. x l outputs b1, b2, b3 are disabled and logic low or in high impedance state. 3 si8455 ? ? outputs b1, b2, b3, b4, b5 are enabled and follow input state. notes: 1. enable inputs en1 and en2 can be used for multiplexing, fo r clock sync, or other output control. these inputs are internally pulled-up to local vdd by a 3 a current source allowing them to be connected to an external logic level (high or low) or left floating. to minimize noise coupling, do not c onnect circuit traces to en1 or en2 if they are left floating. if en1, en2 are unused, it is recommended they be connected to an external logi c level, especially if the si845x is operating in a noisy environment. 2. x = not applicable; h = logic high; l = logic low. 3. when using the enable pin (en) function, the output pin state is driven to a logic low state when the en pin is disabled (en = 0) in revision a. revision b outputs go into a high-impedance state when the en pin is disabled (en = 0). see "4. errata and design migration guidelines (revision a only)" on page 26 for more details.
si8450/51/52/55 20 rev. 1.2 2. typical performance characteristics the typical performance characteristics de picted in the following diagrams are for information purposes only. refer to tables 1, 2, and 3 for actual specification limits. figure 5. si8450/55 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation figure 6. si8451 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 7. si8452 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 8. si8450/55 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 9. si8451 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 10. si8452 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 35 0 102030405060708090100110120130140150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 35 0 102030405060708090100110120130140150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 35 0 102030405060708090100110120130140150 data rate (mbps) current (ma) 5v 3.3v 2.70v
si8450/51/52/55 rev. 1.2 21 figure 11. propagation delay vs. temperature 5 6 7 8 9 10 -40 -20 0 20 40 60 80 100 120 temperature (degrees c) delay (ns) rising edge falling edge
si8450/51/52/55 22 rev. 1.2 3. application information 3.1. theory of operation the operation of an si845x channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si845x channel is shown in figure 12. figure 12. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 13 for more details. figure 13. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver input signal output signal modulation signal
si8450/51/52/55 rev. 1.2 23 3.2. eye diagram figure 14 illustrates an eye-diag ram taken on an si8450. for the data source, the test used an anritsu (mp1763c) pulse pattern generator set to 1000 ns/div. the output of the generator's clock and data from an si8450 were captured on an oscillosc ope. the results illustra te that data integrity was mainta ined even at the high data rate of 150 mbps. the results also show that 2 ns pulse wid th distortion and 250 ps peak jitter were exhibited. figure 14. eye diagram
si8450/51/52/55 24 rev. 1.2 3.3. layout recommendations dielectric isolation is a set of specific ations produced by the safety regulatory agencies from around the world that describes the physical construction of electrical equipment that derives power from a high-voltage power system such as 100?240 v ac systems or industrial power systems. the dielec tric test (or hipot test) given in the safety specifications places a very high voltage between the input power pins of a product an d the user circuits and the user touchable surfaces of the product. for the iec rela ting to products deriving their power from the 100?240 v power grids, the minimum test voltage is 2500 v ac (or 3750 v dc ?the peak equivalent voltage). there are two terms described in the safety specifications: ? creepage?the distance along the insulating surface an arc may travel. ? clearance?the distance through the shortest path through air that an arc may travel. figure 15 illustrates the accepted met hod of providing the pro per creepage distance along the surface. for a 120 v ac application, this distance is 3.2 mm, and the na rrow-body soic package can be used. for a 220?240 v ac application, this distance is 6.4 mm, and a wide-body soic package must be used. there must be no copper traces within this 3.2 or 6.4 mm exclusion area, and the surface should have a conforma l coating, such as solder resist. the digital isolator chip must straddle this exclusion area. figure 15. creepage distance 3.3.1. supply bypass the si845x requires a 1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package. see "4. errata and design migration guidelines (revision a only)" on page 26 for more details. 3.3.2. pin connections for narrow-body devices, pin 2 and pin 8 gnd must be externally connected to respec tive ground. pin 9 and pin 15 must also be connected to external ground. no conn ect pins are not internally connected. they can be left floating, tied to vdd, or tied to gnd. 3.3.3. output pin termination the nominal output impedance of an isolat or driver channel is approximately 85 : , 40%, which is a combination of the value of the on-chip series term ination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appr opriately terminated with controlled impedance pcb traces. iec specified creepage distance
si8450/51/52/55 rev. 1.2 25 3.3.4. rf radiated emissions the si845x family uses a rf carrier frequency of app roximately 700 mhz. this re sults in a small amount of radiated emissions at this frequency and its harmonics. the radiation is not from the ic chip but due to a small amount of rf energy driving the isolated grou nd planes which can act as a dipole antenna. the unshielded si845x evaluation board passes fcc cla ss b (part 15) requirements. table 14 shows measured emissions compared to fcc requirements. note that the da ta reflects worst-case conditions where all inputs are tied to logic 1 and the rf tr ansmitters are fully active. radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the pcb is a less efficient antenna. 3.3.5. rf, magnetic, and common mode transient immunity the si84xx families have very high common mode transient immunity while transmitting data. this is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. measurements show no failures at 25 kv/s (typical). during a high surg e event, the output may glitch low for up to 20?30 ns, but the output corrects immediately after the surge event. the si84xx families pass the industrial requirements of cispr24 for rf immu nity of 10 v/m using an unshielded evaluation board. as shown in figure 16, the isolated ground planes form a parasitic dipole antenna. the pcb should be laid-out to not act as an ef ficient antenna for the rf frequency of interest. rf susceptibility is also significantly reduced when the end system is hous ed in a metal enclosure, or otherwise shielded. the si845x digital isolator can be us ed in close proximity to large moto rs and various other magnetic-field producing equipment. in theory, data transmission errors can occur if the magnetic field is too large and the field is too close to the isolator. however, in actual use, the si84xx devices provide extremely high immunity to external magnetic fields and have been indepe ndently evaluated to withstand magn etic fields of at least 1000 a/m according to the iec 61000-4-8 and iec 61000-4-9 specifications. figure 16. dipole antenna table 14. radiated emissions frequency (mhz) measured (dbv/m) fcc spec (dbv/m) compared to spec (db) 712 29 37 ?8 1424 39 54 ?15 2136 42 54 ?12 2848 43 54 ?11 4272 44 54 ?10 4984 44 54 ?10 5696 44 54 ?10 isolator gnd1 gnd2 dipole antenna
si8450/51/52/55 26 rev. 1.2 4. errata and design migration guidelines (revision a only) the following errata apply to revision a devices only. see "7. ordering guide" on page 29 for more details. no errata exist for revision b devices. 4.1. enable pin causes output s to go low (revision a only) when using the enable pin (en1, en2) function on the isop ro 5-channel (si8450/1/2) isolators, the corresponding output pin states (pin = an, bn, where n can be 1?5) are driven to a logic low (to ground) when the enable pin is disabled (en1 or en2 = 0). this functionality is differ ent from the legacy 3-channel (si8430/1) and 4-channel (si8440/1/2) isolators. on those devices, the isolator outputs go into a high-impedance state (hi-z) when the enable pin is disabled (en1 = 0 or en2 = 0). 4.1.1. resolution the enable pin functionality causing the outputs to go low is supported in production for revision a of the isopro devices. revision b corrects the enab le pin functionality (i.e., the outputs will go into the high-impedance state to match the legacy isolator products). refer to the ordering gu ide sections of the data sh eet(s) for more information. 4.2. power supply bypass ca pacitors (revision a only) when using the isopro isolators with power supplies > 4.5 v, sufficient vdd bypass capacitors must be present on both the vdd1 and vdd2 pins to ensure the vdd rise time is less than 0.5 v/s (which is > 9 s for a > 4.5 v supply). although rise time is power supply dependent, > 1 f capacitors are required on both power supply pins (vdd1, vdd2) of the isolator device. 4.2.1. resolution this issue has been corrected with re vision b of the device. refer to "7. ordering guide" on page 29 for more information. 4.3. latch up imm unity (revision a only) isopro latch up immunity generally exceeds 200 ma per pin. exceptions: certain pins provide < 100 ma of latch- up immunity. to increase latch-up immunity on these pins, 100 ? of equivalent resistance must be included in series with all of the pins listed in table 15. the 100 ? equivalent resistance can be comprised of the source driver's output resistance and a series termination resistor. 4.3.1. resolution this issue has been corrected with revision b of the de vice. refer to the ordering guide for more information. table 15. affected ordering part numbers (revision a only) affected ordering part numbers* device revision pin# name pin type si8450sv-a-is/is1, si8451sv-a-is/is1, si8452sv-a-is/is1 a 2 a1 input 6 a5 input or output 10 en2 input 14 b2 output si8455sv-a-is/is1 a 2 a1 input 6 a5 input 14 b2 output *note: "sv" = speed grade/isolation rating (aa, ab, ba, bb).
si8450/51/52/55 rev. 1.2 27 5. pin descriptions (si8450/51/52) name soic-16 pin# type description v dd1 1 supply side 1 power supply. a1 2 digital input side 1 digital input. a2 3 digital input side 1 digital input. a3 4 digital input side 1 digital input. a4 5 digital i/o side 1 digital input or output. a5 6 digital i/o side 1 digital input or output. en1/nc* 7 digital input side 1 active high enable. nc on si8450. gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. en2 10 digital input side 2 active high enable. b5 11 digital i/o side 2 digital input or output. b4 12 digital i/o side 2 digital input or output. b3 13 digital output side 2 digital output. b2 14 digital output side 2 digital output. b1 15 digital output side 2 digital output. v dd2 16 supply side 2 power supply. *note: no connect. these pins are not internally connected. they can be left floating, tied to v dd or tied to gnd. v dd1 a1 a3 a4 en1/nc gnd1 a2 1 2 3 4 5 6 7 8 top view (si8450/51/52) v dd2 b2 b1 b4 b3 gnd2 en2 9 12 11 10 13 14 15 16 wide body soic narrow body soic v dd1 a1 a3 a4 en1/nc gnd1 a2 1 2 3 4 5 6 7 8 v dd2 b2 b1 b4 b3 gnd2 en2 9 12 11 10 13 14 15 16 a5 b5 a5 b5 top view (si8450/51/52)
si8450/51/52/55 28 rev. 1.2 6. pin descriptions (si8455) name soic-16 pin# type description* v dd1 1 supply side 1 power supply. gnd1 2 ground side 1 ground. a1 3 digital input side 1 digital input. a2 4 digital input side 1 digital input. a3 5 digital input side 1 digital input. a4 6 digital input side 1 digital input. a5 7 digital input side 1 digital input. gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. b5 10 digital output side 2 digital output. b4 11 digital output side 2 digital output. b3 12 digital output side 2 digital output. b2 13 digital output side 2 digital output. b1 14 digital output side 2 digital output. gnd2 15 ground side 2 ground. v dd2 16 supply side 2 power supply. *note: for narrow-body devices, pin 2 and pin 8 gnd must be exte rnally connected to respective ground. pin 9 and pin 15 must also be connected to external ground. v dd1 gnd1 a1 a3 a4 gnd1 a2 1 2 3 4 5 6 7 8 v dd2 gnd2 b2 b1 b4 b3 gnd2 9 12 11 10 13 14 15 16 a5 b5 narrow body soic v dd1 a1 a3 a4 gnd1 a2 1 2 3 4 5 6 7 8 v dd2 b2 b1 b4 b3 gnd2 9 12 11 10 13 14 15 16 a5 b5 top view (si8455) wide body soic top view (si8455) gnd1 gnd2
si8450/51/52/55 rev. 1.2 29 7. ordering guide revision b devices are recommended for all new designs. figure 17. ordering part number (opn) convention table 16. ordering guide for valid opns 1 ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side maximum data rate (mbps) isolation rating temp range package type si8450aa-b-is1 5 0 1 1 kvrms ?40 to 125 c nb soic-16 si8450ba-b-is1 5 0 150 si8451aa-b-is1 4 1 1 si8451ba-b-is1 4 1 150 si8452aa-b-is1 3 2 1 si8452ba-b-is1 3 2 150 si8455ba-b-is1 5 0 150 si8450ab-b-is1 5 0 1 2.5 kvrms ?40 to 125 c nb soic-16 si8450bb-b-is1 5 0 150 si8451ab-b-is1 4 1 1 si8451bb-b-is1 4 1 150 si8452ab-b-is1 3 2 1 si8452bb-b-is1 3 2 150 si8455bb-b-is1 5 0 150 notes: 1. all packages are rohs-compliant. moisture sensitivity level is msl2a with peak reflow temperature of 260 c according to the jedec industry standard classifications and peak solder temperature. 2. revision a devices are supported for existing designs, but revision b is recommended for all new designs. si84xysv-r-tpn isolator product data channel count reverse channel count max data rate (a=1mbps,b=150mbps) insulation rating (a=1kv, b=2.5kv) product revision temp range (i=-40 to +125c) package type (s=soic) package extension (1=narrow body- 16 pin)
si8450/51/52/55 30 rev. 1.2 revision a devices 2 si8450aa-a-is1 2 501 1 kvrms ?40 to 125 c nb soic-16 si8450ba-a-is1 2 501 5 0 SI8451AA-A-IS1 2 411 si8451ba-a-is1 2 411 5 0 si8452aa-a-is1 2 321 si8452ba-a-is1 2 321 5 0 si8455ba-a-is1 2 501 5 0 si8450ab-a-is1 2 501 2.5 kvrms ?40 to 125 c nb soic-16 si8450bb-a-is1 2 501 5 0 si8451ab-a-is1 2 411 si8451bb-a-is1 2 411 5 0 si8452ab-a-is1 2 321 si8452bb-a-is1 2 321 5 0 si8455bb-a-is1 2 501 5 0 table 16. ordering guide for valid opns 1 ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side maximum data rate (mbps) isolation rating temp range package type notes: 1. all packages are rohs-compliant. moisture sensitivity level is msl2a with peak reflow temperature of 260 c according to the jedec industry standard classifications and peak solder temperature. 2. revision a devices are supported for existing designs, but revision b is recommended for all new designs.
si8450/51/52/55 rev. 1.2 31 8. package outline: 16-pin wide body soic figure 18 illustrates the package details for the si845x digital isolator. ta ble 17 lists the values for the dimensions shown in the illustration. figure 18. 16-pin wide body soic table 17. package diagram dimensions symbol millimeters min max a ? 2.65 a1 0.1 0.3 d 10.3 bsc e 10.3 bsc e1 7.5 bsc b 0.31 0.51 c 0.20 0.33 e 1.27 bsc h 0.25 0.75 l 0.4 1.27 ? 0 7
si8450/51/52/55 32 rev. 1.2 9. landing pattern: 16-pin wide-body soic figure 19 illustrates the reco mmended landing pattern details for the si 845x in a 16-pin wide- body soic. table 18 lists the values for the dimens ions shown in the illustration. figure 19. 16-pin soic land pattern table 18. 16-pin wide body soic landing pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05mm is assumed.
si8450/51/52/55 rev. 1.2 33 10. package outline: 1 6-pin narrow body soic figure 20 illustrates the package details for the si845x in a 16-pin narrow-body soic (so-16). table 19 lists the values for the di mensions shown in the illustration. figure 20. 16-pin small outline integrated circuit (soic) package table 19. package diagram dimensions dimension min max a ? 1.75 a1 0.10 0.25 a2 1.25 ? b 0.31 0.51 c 0.17 0.25 d9 . 9 0 b s c e6 . 0 0 b s c e1 3.90 bsc e1 . 2 7 b s c l 0.40 1.27 l2 0.25 bsc
si8450/51/52/55 34 rev. 1.2 h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. table 19. package diagram dimensions (continued)
si8450/51/52/55 rev. 1.2 35 11. landing pattern: 16-pin narrow body soic figure 21 illustrates the re commended landing pattern de tails for the si845x in a 16-pin narrow-body soic. table 20 lists the values for the dimensions shown in the illustration. figure 21. 16-pin narrow body soic pcb landing pattern table 20. 16-pin narrow body soic landing pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si8450/51/52/55 36 rev. 1.2 12. top marking: 16-pin wide body soic figure 22. si8450/51/52/55 top marking table 21. top marking explanation line 1 marking: base part number ordering options (see ordering guide for more information). si84 = isolator product series xy = channel configuration x = # of data channels (5, 4, 3, 2, 1) y = # of reverse channels (2, 1, 0)* s = speed grade a = 1 mbps; b = 150 mbps v = insulation rating a = 1 kv; b = 2.5 kv line 2 marking: yy = year ww = workweek assigned by assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly house line 3 marking: circle = 1.5 mm diameter (center-justified) ?e3? pb-free symbol country of origin iso code abbreviation tw = taiwan *note: si8455 has 0 reverse channels. si84xysv yywwtttttt tw e3
si8450/51/52/55 rev. 1.2 37 13. top marking: 16-pin narrow body soic figure 23. 16-pin narrow body soic top marking table 22. 16-pin narrow body soic top marking table line 1 marking: base part number ordering options (see ordering guide for more information). si84 = isolator product series xy = channel configuration x = # of data channels (5, 4, 3, 2, 1) y = # of reverse channels (2, 1, 0)* s = speed grade a = 1 mbps; b = 150 mbps v = insulation rating a=1kv; b=2.5kv line 2 marking: circle = 1.2 mm diameter ?e3? pb-free symbol yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. circle = 1.2 mm diameter ?e3? pb-free symbol. *note: si8455 has 0 reverse channels. si84xysv yywwtttttt e3
si8450/51/52/55 38 rev. 1.2 d ocument c hange l ist revision 0.1 to revision 0.2 ? updated all specs to re flect latest silicon. ? added "4. errata and design migration guidelines (revision a only)" on page 26. ? added "13. top marking: 16-pin narrow body soic" on page 37. revision 0.2 to revision 1.0 ? updated document to reflec t availability of revision b silicon. ? updated tables 1,2, and 3. ?? updated all supply currents and channel-channel skew. ? updated table 4. ?? updated absolute maximum supply voltage. ? updated table 7. ?? updated clearance and creepage dimensions. ? updated table 12. ?? updated note 7. ? updated table 13. ?? updated note 3. ? updated "4. errata and design migration guidelines (revision a only)" on page 26. ? updated "7. ordering guide" on page 29. revision 1.0 to revision 1.1 ? updated tables 1, 2, and 3. ?? updated notes in both tables to reflect output impedance of 85 : . ?? updated rise and fall time specifications. ?? updated cmti value. revision 1.1 to revision 1.2 ? updated document throughout to include msl improvements to msl2a. ? updated "7. ordering guide" on page 29. ?? updated note 1 in ordering guide table to reflect improvement and compliance to msl2a moisture sensitivity level.
si8450/51/52/55 rev. 1.2 39 n otes :
si8450/51/52/55 40 rev. 1.2 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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