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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. february 2010 doc id 17058 rev 1 1/82 82 stmpe16m31px stmpe24m31px s-touch? 16/24-channel touchkey controller with proximity sensing features up to 24 capacitive sensor inputs independent and configurable automatic calibration on all channels proximity sensing capability for over 3 cm distance 15 ff resolution, 512 steps with 30 pf auto- tuning up to 30 pf external reference capacitor pwm and gpio: ? up to 16 general purpose inputs/outputs ? 8 independent pwm controllers, up to 16 pwm outputs ? 12 ma sourcing/sinking on gpio for led driving (at 3.3 v v io ) ? maximum source/sink current 120 ma operating voltage: ?1.65-1.95v (v cc , internally supplied) ?2.7-5.5v(v io ) low operating current: 300 a in active mode, 40 a in sleep mode and 5 a in hibernate mode i 2 c interface (up to 400 khz). i 2 c is 3.3 v tolerant 8 kv hbm esd protection on all sensing pins applications multimedia bars in notebook computers portable media players and game consoles mobile phones and smartphones description the stmpe16m31px and stmpe24m31px capacitive touchkey controllers offer highly versatile and flexible capacitive sensing capabilities in one single chip. the devices integrate up to 24 capacitive sensing channels which are highly sensitive and noise tolerant. eight independent pwm controllers allow to control up to 16 leds with brightness control, ramping and blinking capabilities. the i 2 c interface supports up to 400 khz communication with the system host. a very wide dynamic range allows most applicatio ns to work without hardware tuning. a single stmpe24m31px device can be used to implement a complete notebook multimedia control bar with eight capacitive touchkeys, proximity sensor with sensitivity up to 5 cm and eight independently controlled led. qfn40 (5 x 5 mm) qfn32 (4 x 4 mm) table 1. device summary order code package packaging stmpe24m31pxqtr qfn40 (5 x 5 mm) tape and reel STMPE16M31PXQTR qfn32 (4 x 4 mm) tape and reel www.st.com
contents stmpe16m31 px, stmpe24m31px 2/82 doc id 17058 rev 1 contents 1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 power scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2i 2 c interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 write operations for one or more bytes . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 general call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 register map and function descrip tion . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 gpio controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 pwm array controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 pwm controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1 pwm function register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12 basic pwm programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.1 interrupt on basic pwm controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13 touch sensor controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.1 sampling rate calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.2 sensor resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
stmpe16m31px, stmp e24m31px contents doc id 17058 rev 1 3/82 13.3 auto tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.4 locked impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.5 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.6 definition of data accessible through channel data register . . . . . . . . . . . 59 14 touchkey and proximity sensi ng controller . . . . . . . . . . . . . . . . . . . . . 60 15 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 15.1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 16.1 capacitive sensor specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 17 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
pin assignment stmpe16m31px, stmpe24m31px 4/82 doc id 17058 rev 1 1 pin assignment figure 1. stmpe24m31px pin out !-6 34-0%-08
stmpe16m31px, stmpe2 4m31px pin assignment doc id 17058 rev 1 5/82 figure 2. stmpe16m31px pin out table 2. pin description stmpe24m31px pin number stmpe16m31px pin number pin name voltage domain description 1 1 gpio-0 vio gpio / capacitive sense 2 2 gpio-1 vio gpio / capacitive sense 3 3 gpio-2 vio gpio / capacitive sense 4 4 gnd - ground 5 5 vio - i/o supply 6 - cap-16 vcc capacitive sense 7 - cap-17 vcc capacitive sense 8 6 gpio-3 vio gpio / cap sense 9 7 gpio-4 vio gpio / cap sense 10 8 gpio-5 vio gpio / cap sense 11 9 gpio-6 vio gpio / cap sense 12 10 gpio-7 vio gpio / cap sense 13 11 gnd - ground 14 12 vio - i/o supply !-6 34-0%-08
pin assignment stmpe16m31px, stmpe24m31px 6/82 doc id 17058 rev 1 stmpe24m31px pin number stmpe16m31px pin number pin name voltage domain description 15 - cap-18 vcc capacitive sense 16 - cap-19 vcc capacitive sense 17 13 vcc - 18 14 int vcc open drain interrupt output. this pin should be pulled to vcc or gnd, depending on polarity of interrupt used. this pin must not be left floating. 19 15 address 0 vcc i 2 c address 0 20 16 scl vcc i 2 c clock 21 17 sda vcc i 2 c data 22 18 reset_n vcc active low reset signal 23 19 address 1 vcc i 2 c address 1 24 20 cref vcc reference capacitor 25 - cap-20 vcc capacitive sense (minimum 10 pf capacitor is recommended) 26 - cap-21 vcc capacitive sense 27 21 gnd vcc ground 28 22 gpio-8 vio gpio / capacitive sense 29 23 gpio-9 vio gpio / capacitive sense 30 24 vio - i/o supply 31 25 gpio-10 vio gpio / capacitive sense 32 26 gpio-11 vio gpio / capacitive sense 33 27 gpio-12 vio gpio / capacitive sense 34 28 gpio-13 vio gpio / cap sense 35 29 vio - i/o supply 36 30 gnd - i/o voltage supply 37 - cap-22 vcc capacitive sense 38 - cap-23 vcc capacitive sense 39 31 gpio-14 vio gpio / capacitive sense 40 32 gpio-15 vio gpio / capacitive sense table 2. pin description (continued)
stmpe16m31px, stmpe2 4m31px pin assignment doc id 17058 rev 1 7/82 figure 3. block diagram !-6 -58 07- array 6## 6)/ 3#,+ 3$!4 2%3% 32ef 07- controller ).4 ! '0)/ controller #apacitancesensor '0)/ '.$ ! #!0 -only '.$ 6##domain 6)/domain #alibration .oisefilter (ost interface unit
pin assignment stmpe16m31px, stmpe24m31px 8/82 doc id 17058 rev 1 figure 4. sample application - notebook multimedia bar table 3. limitations on intrinsic capacitance on pcb / flexi pcb (1) 1. for small pcbs, it is possible to operate the device with cref left unconnected. however, without a small capacitance at this pin, the capac itive sensing operation tends to be noisier. it is recommended that a capacitor of 10 pf to be connected to this pin. cmax-cmin (difference between highest and lowest channel capacitance) cmax matching capacitors < 30 pf < 30 pf not required <3 0 pf > 30 pf, < 60 pf cref of up to 30 pf required >30pf, <60pf >30pf, <60pf cref of up to 30 pf required channel matching capacitance of up to 25 pf required > 60 pf > 60 pf pcb optimization required !-6 3ensor 3ensor 07- %mbedded controller 3$!4 3#,+ ).4 2ef )ndicator,%$s 3ensorpads 234
stmpe16m31px, stmpe2 4m31px pin assignment doc id 17058 rev 1 9/82 1.1 power scheme the stmpe24m31px/16m31px is powered by a 2.7- 5.5 v supply. an internal voltage regulator regulates this supply into 1.8 v for core operation. it is recommended to connect a 1f capacitor at v cc pin for filtering purpose. the v io powers all gpios directly, if any led driving is required on the gpio, the v io should be at least 3.3 v. figure 5. power supply scheme 1.2 power states the stmpe24m31px/16m31px operate in 3 states. ta b l e 4 illustrates the capability of the device in each of the power states. 34-0%-08 34-0%-08 6)/ 6## '.$ 6 u& table 4. functions available in each power state hibernate sleep active i 2 c yes yes yes gpio hotkey yes yes yes pwm no yes yes capacitive sensing no slow yes proximity sensor no no yes
i 2 c interface module stmpe1 6m31px, stmpe24m31px 10/82 doc id 17058 rev 1 2 i 2 c interface module the stmpe24m31px/16m31px has 2 physical i 2 c address pins, allowing 4 different i 2 c address settings. the features that are supported by the i 2 c interface module are the following ones: ?i 2 c slave device ? operates at v cc ? compliant to philips i 2 c specification version 2.1 ? supports standard (up to 100 kbps) and fast (up to 400 kbps) modes ? 7-bit and 10-bit device addressing modes ? general call ? start/restart/stop the features that are not supported are: ? hardware general call ? cbus compatibility ? high-speed (3.4 mbps) mode 2.1 device operation start condition a start condition is iden tified by a falling edge of sda while scl is stable at high state. a start condition must precede any data/command transfer. the device continuously monitors for a start condition and does not respond to any transaction unless one is encountered. stop condition a stop condition is identified by a rising edge of sda while scl is stable at high state. a stop condition terminates the communication between the slave device and bus master. a read command that is followed by noack can be followed by a stop condition to force the slave device into idle mode. when the slave device is in idle mode, it is ready to receive the next i 2 c transaction. a stop condition at the end of a write command stops the write operation to registers. table 5. i 2 c address pins address 1 address 0 i 2 c address 0 0 0x58 0 1 0x59 100x5a 110x5b
stmpe16m31px, stmpe24m31px i 2 c interface module doc id 17058 rev 1 11/82 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter releases the sda after sending eight bits of data. during the ninth bit, the receiver pulls the sda low to acknowledge the receipt of the eight bits of data. the receiver may leave the sda in high state if it would to not acknowledge the receipt of the data. data input the device samples the data input on sda on the rising edge of the scl. the sda signal must be stable during the rising edge of scl and the sda signal must change only when scl is driven low. memory addressing for the bus master to communicate to the slave device, the bus master must initiate a start condition and be followed by the slave device address. accompanying the slave device address, there is a read/w bit (r/w ). the bit is set to 1 for read and 0 for write operation. if a match occurs on the slave device address, the corresponding device gives an acknowledgement on the sda during the 9 th bit time. if there is no match, it deselects itself from the bus by not responding to the transaction. the register memory map of the device is 8-bit address width. therefore, the maximum number of register is 256 registers of 8-bit width. ta bl e 6 illustrates the device operat ing modes that are supported. table 6. device operation modes mode bytes initial sequence read 1 start, device address, r/w =0, base register address to be read restart, device address, r/w =1, data read, stop if no stop is issued, the data read can be continuously preformed. the address is automatically incremented on subsequent data read. write 1 start, device address, r/w =0, register address to be written, data write, stop if no stop is issued, the data write can be continuously performed. the address is automatically incremented on subsequent write.
i 2 c interface module stmpe1 6m31px, stmpe24m31px 12/82 doc id 17058 rev 1 figure 6. read and write modes (random and sequential) one byte re ad start r n w = 0 a c k a c k restart r n w = 1 a c k n o a c k s top more than one byte re ad start r n w = 0 a c k a c k restart r n w = 1 a c k a c k a c k n o a c k s top one byte write start r n w = 0 a c k a c k a c k s top m ore th an one byte write start r n w = 0 a c k a c k a c k a c k a c k s top master slave i2c transaction using 7-bit addressing one byte re ad start r n w = 0 a c k a c k a c k restart r n w = 1 a c k n o a c k s top more than one byte re ad start r n w = 0 a c k a c k a c k restart r n w = 1 a c k a c k a c k a c k n o a c k s top one byte write start r n w = 0 a c k a c k a c k a c k s top more than one byte write start r n w = 0 a c k a c k a c k a c k a c k a c k s top master slave i2c transaction using 10-bit addressing data to write + 1 data to write + 2 dev a ddr (2 m sb ) dev a ddr (2 m sb ) dev addr (8 lsb ) reg a ddr data to write ? dev a ddr (2 m sb ) dev addr (8 lsb ) reg a ddr 11110 dev a ddr (2 m sb ) data read dev a ddr reg addr dev a ddr data read data read + 1 data read + 2 dev a ddr reg addr data to be written dev a ddr reg addr dev a ddr data read 11110 data to write + 1 data to write + 2 dev a ddr reg addr data to write dev a ddr (2 m sb ) dev addr (8 lsb ) reg a ddr 11110 ? data read data read + 1 data read + 2 dev addr (8 lsb ) reg a ddr 11110 11110 data to write 11110 dev a ddr (2 m sb ) data read
stmpe16m31px, stmpe24m31px i 2 c interface module doc id 17058 rev 1 13/82 figure 7. flow diagram for read and write modes !-6 !ck 34!24 $evice!ddr 2n7 !ddrof2eg !ck 34!24 !ck $evice!ddr 2n7 re34!24 $ata2ead i .o!ck !ck 34/0 %.$ .o!ck -aster 3lave $ata7rite i !ck
read operations stmpe1 6m31px, stmpe24m31px 14/82 doc id 17058 rev 1 3 read operations read operations for one or more bytes a write is first performed to load the base register address into the address counter but without sending a stop condition. then, the bus master sends a restart condition and repeats the device address with the r/w bit set to 1. the slave device acknowledges and outputs the content of the addressed byte. if no more data is to be read, the bus master must not acknowledge the byte and terminates the transfer with a stop condition. if the bus master acknowledges the data byte, then it can continue to perform the data reading. to terminate the stream of data byte, the bus master must not acknowledge the last output byte and follow by a stop condition. the data fetched are from consecutive addresses. after the last memory address, the address counter 'rolls-over' and the device continue to output data from the memory address of 0x00. acknowledgement in read operation for the above read command, the slave device waits, after each byte read, for an acknowledgement during the 9th bit time. if the bus master does not drive the sda to low state (no acknowledgement by the master), then the slave device terminates and switches back to its idle mode, wa iting for the next command.
stmpe16m31px, stmpe24m 31px write operations doc id 17058 rev 1 15/82 4 write operations 4.1 write operations for one or more bytes a write is first performed to load the base register address into the address counter without sending a stop condition. after the bus master receives an acknowledgement from the slave device, it may start to send a data byte to the register (pointed by the address counter). the slave device again acknowledges and the bus master terminates the transfer with a stop condition. if the bus master would like to continue to wr ite more data, it can just contin ue write operation without issuing the stop condition. after the bus master writes the last data byte and the slave device acknowledges the receipt of the last data, the bus master may terminate the write operation by sending a stop condition. when the address counter reaches the last memory address, it 'rolls-over' on the next data byte write.
general call address stm pe16m31px, stmpe24m31px 16/82 doc id 17058 rev 1 5 general call address a general call address is a transaction with the slave address of 0x00 and r/w = 0. when a general call address is made, the gpio expander responds to this transaction with an acknowledgement and behaves as a slave-receiver mode. the meaning of a general call address is defined in the second byte sent by the master-transmitter. note: all other second by te values will be ignored. note: please allow a gap of approximately 2 s gap before the next i2c transaction after the general call of 0x04 or 0x06. table 7. definition of the second byte of the i 2 c transaction r/w second byte value definition 0 0x06 2-byte transaction in which the second byte tells the slave device to perform a soft reset and write (or latch in) the 2-bit programmable part of the slave address. 0 0x04 2-byte transaction in which the second byte tells the slave device not to perform a soft reset and write (or latch in) the 2-bit programmable part of the slave address. 0 0x00 not allowed as second byte.
stmpe16m31px, stmpe24m31px register map and function description doc id 17058 rev 1 17/82 6 register map and function description this section lists and describes the registers of the stmpe16m31px and stmpe24m31px devices, starting with a register map and then provides detailed descriptions of register types. table 8. register map address register name reset value i 2 c register function 0x00 chip_id 0x2431 r chip identifi cation number msb: 0x24, lsb: 0x32 0x02 id_ver 0x03 r version of device engineering samples: 0x01, 0x02 final silicon: 0x03 0x03 syscon-1 0x00 rw general system control 0x04 syscon-2 0xfe rw sensor and pwm clock divider 0x06 int_ctrl 0x00 rw interrupt control 0x08 int_sta 0x00 rw interrupt status 0x09 int_en 0x00 rw interrupt enable 0x0a gpio_int_sta 0x0000 rw interrupt status gpio 0x0c gpio_int_en 0x0000 rw interrupt enable gpio 0x0e pwm_int_sta 0x00 rw i nterrupt status pwm 0x0f pwm_int_en 0x00 rw interrupt enable pwm 0x10 gpio_dir 0x0000 rw gpio direction setting 0x12 gpio_mp_sta 0x0000 r gpio pin state monitor 0x14 gpio_set_pin 0x0000 rw gpio set pin state 0x16 gpio_alt_fun 0x0000 rw gpio alternate function 0x20 gpio_0_pwm_cfg 0x00 rw configures pwm output of gpio-0 0x21 gpio_1_pwm_cfg 0x00 rw configures pwm output of gpio-1 0x22 gpio_2_pwm_cfg 0x00 rw configures pwm output of gpio-2 0x23 gpio_3_pwm_cfg 0x00 rw configures pwm output of gpio-3 0x24 gpio_4_pwm_cfg 0x00 rw configures pwm output of gpio-4 0x25 gpio_5_pwm_cfg 0x00 rw configures pwm output of gpio-5 0x26 gpio_6_pwm_cfg 0x00 rw configures pwm output of gpio-6
register map and function description stmpe16m31px, stmpe24m31px 18/82 doc id 17058 rev 1 0x27 gpio_7_pwm_cfg 0x00 rw configures pwm output of gpio-7 0x28 gpio_8_pwm_cfg 0x00 rw configures pwm output of gpio-8 0x29 gpio_9_pwm_cfg 0x00 rw configures pwm output of gpio-9 0x2a gpio_10_pwm_cfg 0x00 rw configures pwm output of gpio-10 0x2b gpio_11_pwm_cfg 0x00 rw configures pwm output of gpio-11 0x2c gpio_12_pwm_cfg 0x00 rw configures pwm output of gpio-12 0x2d gpio_13_pwm_cfg 0x00 rw configures pwm output of gpio-13 0x2e gpio_14_pwm_cfg 0x00 rw configures pwm output of gpio-14 0x2f gpio_15_pwm_cfg 0x00 rw configures pwm output of gpio-15 0x30 pwm_master_en 0x00 rw pwm master enable 0x40 pwm_0_set 0x00 rw pwm0 setup 0x41 pwm_0_ctrl 0x00 rw pwm0 control 0x42 pwm_0_ramp_rate 0x00 rw pwm0 ramp rate 0x43 pwm_0_trig 0x00 rw pwm0 trigger 0x44 pwm_1_set 0x00 rw pwm1 setup 0x45 pwm_1_ctrl 0x00 rw pwm1 control 0x46 pwm_1_ramp_rate 0x00 rw pwm1 ramp rate 0x47 pwm_1_trig 0x00 rw pwm1 trigger 0x48 pwm_2_set 0x00 rw pwm2 setup 0x49 pwm_2_ctrl 0x00 rw pwm2 control 0x4a pwm_2_ramp_rate 0x00 rw pwm2 ramp rate 0x4b pwm_2_trig 0x00 rw pwm2 trigger 0x4c pwm_3_set 0x00 rw pwm3 setup 0x4d pwm_3_ctrl 0x00 rw pwm3 control 0x4e pwm_3_ramp_rate 0x00 rw pwm3 ramp rate 0x4f pwm_3_trig 0x00 rw pwm3 trigger 0x50 pwm_4_set 0x00 rw pwm4 setup 0x51 pwm_4_ctrl 0x00 rw pwm4 control 0x52 pwm_4_ramp_rate 0x00 rw pwm4 ramp rate table 8. register map (continued) address register name reset value i 2 c register function
stmpe16m31px, stmpe24m31px register map and function description doc id 17058 rev 1 19/82 0x53 pwm_4_trig 0x00 r/w pwm4 trigger 0x54 pwm_5_set 0x00 r/w pwm5 setup 0x55 pwm_5_ctrl 0x00 r/w pwm5 control 0x56 pwm_5_ramp_rate 0x00 r/w pwm5 ramp rate 0x57 pwm_5_trig 0x00 r/w pwm5 trigger 0x58 pwm_6_set 0x00 r/w pwm6 setup 0x59 pwm_6_ctrl 0x00 r/w pwm6 control 0x5a pwm_6_ramp_rate 0x00 r/w pwm6 ramp rate 0x5b pwm_6_trig 0x00 r/w pwm6 trigger 0x5c pwm_7_set 0x00 r/w pwm7 setup 0x5d pwm_7_ctrl 0x00 r/w pwm7 control 0x5e pwm_7_ramp_rate 0x00 r/w pwm7 ramp rate 0x5f pwm_7_trig 0x00 r/w pwm7 trigger 0x70 cap_sen_ctrl 0x00 r/w capacitive sensor control 0x71 ratio_eng_rept_c trl 0x00 r/w ratio engine report control (only available in final silicon) 0x72 ch_sel 0x00000000 r/w selects active capacitive channels 0x76 cal_int 0x00 r/w 10ms ? 64s calibration interval 0x77 cal_mod 0x00 r/w selects calibration model 0x78 maf_set 0x00 r/w control of median averaging filter 0x7c data_type 0x00 r/w selects type of data available in channel data ports. 0x01: tvr 0x02: evr 0x03: channel delay 0x04: impedance (13-bit) 0x05:calibrated impedance (13- bit) 0x06:locked impedance (13-bit) 0x90 key_prox_ctrl 0x00 r/w general key filter control 0x92 key_filt_group-1 0x00000000 r/w define channels included in key filter group 1 0x96 prox_cfg 0x00 r/w proximity configuration register 0x97 ptvr 0x00 r/w tvr used for proximity sensing 0x98 pevr 0x00 r/w evr used for proximity sensing and forced proximity calibration table 8. register map (continued) address register name reset value i 2 c register function
register map and function description stmpe16m31px, stmpe24m31px 20/82 doc id 17058 rev 1 0xb1 peport1 0x00 r proximity data 1 0xbo peport0 0x00 r proximity data o 0x9a key_filt_data 0x00000000 filtered touchkey data 0xb4 touch_det 0x00000000 r touch detection register (real time) 0xc0 ch_data-0 0x0000 channel data according to data type setting 0xc2 ch_data-1 0x0000 0xc4 ch_data-2 0x0000 0xc6 ch_data-3 0x0000 0xc8 ch_data-4 0x0000 0xca ch_data-5 0x0000 0xcc ch_data-6 0x0000 0xce ch_data-7 0x0000 0xd0 chdata-8 0x0000 0xd2 ch_data-9 0x0000 0xd4 ch_data-10 0x0000 0xd6 ch_data-11 0x0000 0xd8 ch_data-12 0x0000 0xda ch_data-13 0x0000 0xdc ch_data-14 0x0000 0xde ch_data-15 0x0000 0xe0 ch_data-16 0x0000 0xe2 ch_data-17 0x0000 0xe4 ch_data-18 0x0000 0xe6 ch_data-19 0x0000 0xe8 ch_data-20 0x0000 0xea ch_data-21 0x0000 0xec ch_data-22 0x0000 0xee ch_data-23 0x0000 table 8. register map (continued) address register name reset value i 2 c register function
stmpe16m31px, stmpe24m 31px system controller doc id 17058 rev 1 21/82 7 system controller the system controller contains the registers that control the following functions: ? device identification ? version identification ? power state management ? clock speed management ? clock gating to various modules table 9. system controller registers address register name reset value r/w description 0x00 chip_id 0x2432 r chip identification number msb: 0x24, lsb: 0x32 0x02 id_ver 0x03 r version of device 0x03 syscon-1 0x00 rw general system control 0x04 syscon-2 0xfe rw sensor and pwm clock divider
system controller stm pe16m31px, stmpe24m31px 22/82 doc id 17058 rev 1 syscon-1 general system control address: 0x03 type: r/w reset: 0x00 description: the general system co ntrol register (syscon-1) cont rols the operat ion state and clock speed of the device. 76543210 reserved reserved reserved clkspd sleep_en reserved soft_rst hibrnt rw rw rw rw rw rw rw rw 11111110 [7:5] reserved: do not write to these bits. reads ?0 ?. writing ?1? to these bits may result in unpredictable behaviour. [4] clkspd: selects the macro engine?s speed. 0: 2 mhz 1: reserved [3] sleep_en: enable or disable the sleep mode. under all operating conditions, this bit should be set to '0'. 1: enable the touch sensor?s sleep mode 0: disable the touch sensor?s sleep mode [2] reserved: do not write to these bits. reads ?0?. [1] soft_rst: soft reset. 1: to perform soft reset. [0] hibrnt: hibernate. 1: to force the device to hibernate mode.
stmpe16m31px, stmpe24m 31px system controller doc id 17058 rev 1 23/82 syscon-2 sensor and pw m clock divider address: 0x04 type: r/w reset: 0xfe description: sensor and pwm clock divider. the syscon -2 register contro ls the sensor and pwm clock speed, and the clock gating of various functional modules. this bit will always read '0'. as the i2c tr ansaction to read this bit will wake up the device from hibernate mode. 76543210 sclk_div pclk_div gpio_clk pwm_clk cs_clk rw rw rw rw 1110 [7:5] sclk_div: sensor clock divider. 000, 001: reserved 010 : 32 (to be used only if load capacitance is < 30 pf) 011: 64 100: 128 101: 256 110: 512 111: 1024 sensor clock is 2 mhz / ( prbs_factor * sclk_div[2:0] ) prbs factor is a pseudo-random sequence of number , ranging from 1-8. this is used to reduce the effect of surrounding emi on the sensor. aver age of this factor is approximately 2.5 effective sampling rate is 2 mhz/ (2.5*sclk_div[2:0]). maximum total sampling rate : 2mhz/(2.5*64) = 12.5 khz minimum total sampling rate : 2 mhz/(2.5*1024) = 780 hz if n channel is active, the per-channel sampling rate is ?total sampling rate / n?. maximum channel sampling rate = 12.5 khz/24 = 521 hz [4:3] pclk_div: pwm clock divider 00 for 16 khz 01 for 32 khz 10 for 64 khz 11 for 128 khz
system controller stm pe16m31px, stmpe24m31px 24/82 doc id 17058 rev 1 [2] pmw_clk: pwm clock disable write ?1? to disable the clock to pwm module. when clock to pwm module is disabled, access to pwm module register will not work correctly. [1] gpio_clk: gpio clock disable write ?1? to diwrite ?1? to disa ble the clock to gpio module. when clock to gpio module is disabled, access to gpio module register will not work correctly. [0] cs_clk: capacitive sensor clock disable write ?1? to disable the clock to capactive sensor module when clock to touch module is disabled, acce ss to touch module registers will not work correclty.
stmpe16m31px, stmpe24m 31px system controller doc id 17058 rev 1 25/82 7.1 interrupt system this module controls the interruption to the ho st based on the activity of other modules in the system, such as the capacitive sensing, gpio and pwm modules. figure 8. interrupt system table 10. interrupt system registers address register name reset value r/w description 0x06 int_ctrl 0x00 rw interrupt control register 0x08 int_sta 0x00 rw interrupt status register 0x09 int_en 0x00 rw interrupt enable register 0x0a gpio_int_sta 0x0000 rw inter rupt status gpio register 0x0c gpio_int_en 0x0000 rw inter rupt enable gpio register 0x0e pwm_int_sta 0x00 rw interrupt status pwm register 0x0f pwm_int_en 0x00 rw interrupt enable pwm register !-6 ).4 status '0)/ status bit '0)/ events 3ystemevents 4ou chscreen %nvironment alarm 07- status bit 07- events
system controller stm pe16m31px, stmpe24m31px 26/82 doc id 17058 rev 1 int_ctrl interrupt control register address: 0x06 type: r/w reset: 0x00 description: syscon3 controls the interrupt signal generation. 76543210 reserved int_pol int_type int_en rw rw rw rw rw rw rw rw 00000000 [7:3] reserved [2] int_pol: interrupt polarity 0: active low 1: active high [1] int_type: interrupt trigger type 0: level trigger 1: edge trigger [0] int_en: interrupt enable 1: enable the interrupt 0: disable the interrupt
stmpe16m31px, stmpe24m 31px system controller doc id 17058 rev 1 27/82 int_sta interrupt status register address: 0x08 type: r/w reset: 0x00 description: this register holds interrupt status from each event. 76543210 gpio pwm wakeup env eoc touch prox reserved rw rw rw rw rw rw rw - 00000000 [7] gpio: activity in gpio read ?1? if gpio event occurs write ?1? to clear the interrupt status [6] pwm: any channel of pwm has completed the programmed sequence read ?1? if pwm event occurs write ?1? to clear the interrupt status [5] device wake up from sleep or hibernate mode read ?1? if wake-up event occurs write ?1? to clear the interrupt status [4] env: possible drastic/abnormal environmental changes that requires attention from system software. this event includes ?calibration stuck? and ?tuning out of range?. if this bit is set, it is recommended that the host software initiates an unconditional calibration. read ?1? if the events occur write ?1? to clear the interrupt status [3] eoc: end of calibration read ?1? if the host-triggered calibration has completed write ?1? to clear the interrupt status [2] touch: touch-key event read ?1? if touch is detected write ?1? to clear the interrupt status [1] prox: proximity sensor event read ?1? if proximity sensor detects an object write ?1? to clear the interrupt status [0] reserved
system controller stm pe16m31px, stmpe24m31px 28/82 doc id 17058 rev 1 int_en interrupt enable register address: 0x09 type: r/w reset: 0x00 description: controls interrupt source enable. 76543210 gpio pwm wakeup env eoc touch prox reserved rw rw rw rw rw rw rw w 00000000 [7] gpio: activity in gpio write ?1? to enable interrupt signal from gpio write ?0? to disable interrupt signal from gpio [6] pwm: any channel of pwm has completed the programmed sequence write ?1? to enable interrupt signal from pwm write ?0? to disable interrupt signal from pwm [5] device wake up from sleep or hibernate mode read ?1? if wake-up event occurs write ?1? to clear the interrupt status [4] env: possible drastic/abnormal environmental changes that requires attention from system software. this event includes ?calibration stuck? and ?tuning out of range? write ?1? to enable interrupt signal from calibration/tuning event write ?0? to disable interrupt signal from calibration/tuning event [3] eoc: end of calibration write ?1? to enable interrupt signal from end of calibration event write ?0? to disable interrupt signal from end of calibration event [2] touch: touchkey event system should access touch detection regi ster when this interrupt is received. touch interrupt source needs to be enabled to activate key filter data. write ?1? to enable interrupt signal from touch event write ?0? to disable interrup t signal from touch event [1] prox: proximity sensor event write ?1? to enable interrupt signal from proximity sensor [0] reserved write ?0? to disable interrupt signal from proximity sensor
stmpe16m31px, stmpe24m 31px system controller doc id 17058 rev 1 29/82 gpio_int_sta interrupt status gpio register address: 0x0a ? 0x0b type: r/w reset: 0x0000 description: this register reflects the status of gpio that has been configured as input. when there is a change in gpio state, the corres ponding bit will be set to ?1? by hardware. writing ?1? to the corresponding bit cl ears it. writing ?0? has no effect. lsb (0x0a) msb (0x0b) 76543210 io-7 io-6 io-5 io-4 io-3 io-2 io-1 io-0 rw rw rw rw rw rw rw rw 00000000 76543210 io-15 io-14 io-13 io-12 io-11 io-10 io-9 io-8 rw rw rw rw rw rw rw rw 00000000 [7:0] io - x: interrupt status of gpio - x read ?1? if state transition is detected in corresponding gpio channel write?1? to clear the interrupt staus.
system controller stm pe16m31px, stmpe24m31px 30/82 doc id 17058 rev 1 gpio_int_en interrupt enable gpio register address: 0x0c ? 0x0d type: r/w reset: 0x0000 description: this register is used to enable the gener ation of interrupt signal, at the int pin. lsb (0x0c) msb (0x0d) pwm_int_sta interrupt status pwm register address: 0x0e type: r/w reset: 0x00 description: when a pwm controller completes the pwm s equence, the corresponding bit in this register goes to ?1?. write ?1 ? in this register clears th e written bit, writing ?0? has no effect. 76543210 io-7 io-6 io-5 io-4 io-3 io-2 io-1 io-0 rw rw rw rw rw rw rw rw 00000000 76543210 io-15 io-14 io-13 io-12 io-11 io-10 io-9 io-8 rw rw rw rw rw rw rw rw 00000000 [7:0] io - x interrupt status of gpio - x read ?1? if state transition is detected in corresponding gpio channel write?1? to clear the interrupt staus. 76543210 pwm-7 pwm-6 pwm-5 pwm-4 pwm-3 pwm-2 pwm-1 pwm-0 rw rw rw rw rw rw rw rw 00000000 [7:0] pwm - x interrupt status of pwm ? x. read ?1? if the corresponding pwm channel complete programmed sequence write ?1? to clear the interrupt status
stmpe16m31px, stmpe24m 31px system controller doc id 17058 rev 1 31/82 pwm_int_en interrupt enab le pwm enable register address: 0x0f type: r/w reset: 0x00 description: writing ?1? to this register enables the generation of int by the corresponding pwm channel. 76543210 pwm-7 pwm-6 pwm-5 pwm-4 pwm-3 pwm-2 pwm-1 pwm-0 rw rw rw rw rw rw rw rw 00000000 [7:0] pwm - x enable of pwm ? x. write ?1? to the corresponding bit to enable interrupt generated by a pwm channel
interrupt service routine s tmpe16m31px, stmpe24m31px 32/82 doc id 17058 rev 1 8 interrupt service routine on receiving an interrupt, system software should: read interruptstatus if (gpio.bit==1) { read interruptstatusgpio process gpio int write interruptstatusgpio to clear the corresponding bit write interruptstatus to clear the corresponding bit } if (pwm.bit==1) { read interruptstatuspwm process pwm int write interruptstatuspwm to clear the corresponding bit write interruptstatus to clear the corresponding bit } if ( ev_alarm or touchscreen or touchkey) { process int write interruptstatus to clear the corresponding bit }
stmpe16m31px, stmpe24m31px gpio controller doc id 17058 rev 1 33/82 9 gpio controller a total of 16 gpios are available in the stmpe24m31px/stmpe16m31px. most of the gpios are sharing physical pins with some alternate functions. the gpio controller contains the registers that allow the host system to configure each of the pins into either a gpio, or one of the alternate functions. unused gpios should be configured as outputs to minimize the power consumption. table 11. gpio controller registers gpio_dir gpio direction register address: 0x10 ? 0x11 type: rw reset: 0x00 description: direction seeting of the gpio. lsb (0x10) msb (0x11) address register name reset value r/w description 0x10 gpdr 0x0000 r/w gpio direction register 0x12 gpmr 0x0000 r/w gpoio monitor pin state register 0x14 gpsr 0x0000 r/w gpio set pin register 0x16 gpfr 0x0000 r/w gpio alternate function register 76543210 io-7 io-6 io-5 io-4 io-3 io-2 io-1 io-0 rw rw rw rw rw rw rw rw 00000000 76543210 io-15 io-14 io-13 io-12 io-11 io-10 io-9 io-8 rw rw rw rw rw rw rw rw 00000000 [7:0] io - x write ?1? to a bit to set the corresponding i/o to output. write ?0? to a bit to set the corresponding i/o to input.
gpio controller stmpe1 6m31px, stmpe24m31px 34/82 doc id 17058 rev 1 gpio_mp_sta gpio monito r pin state register address: 0x12 ? 0x13 type: r reset: 0x00 description: contains the state of all gpio. lsb (0x12) msb (0x13) 76543210 io-7 io-6 io-5 io-4 io-3 io-2 io-1 io-0 rw rw rw rw rw rw rw rw 00000000 76543210 io-15 io-14 io-13 io-12 io-11 io-10 io-9 io-8 rw rw rw rw rw rw rw rw 00000000 [7:0] io - x read ?1? if the corresponding io is in high state read ?0? if the corresponding io is in low state
stmpe16m31px, stmpe24m31px gpio controller doc id 17058 rev 1 35/82 gpio_set_pin gpio set pin state register address: 0x14 ? 0x15 type: rw reset: 0x00 description: setting of the i/o output state. lsb (0x14) msb (0x15) 76543210 io-7 io-6 io-5 io-4 io-3 io-2 io-1 io-0 rw rw rw rw rw rw rw rw 00000000 76543210 io-15 io-14 io-13 io-12 io-11 io-10 io-9 io-8 rw rw rw rw rw rw rw rw 00000000 [7:0] io - x write ?1? to set the corresponding io output state to high write ?0? to set the correspo nding io output state to low
gpio controller stmpe1 6m31px, stmpe24m31px 36/82 doc id 17058 rev 1 gpio_af gpio function register address: 0x16 ? 0x17 type: rw reset: 0x00 description: setting of the gpio function. lsb (0x16) msb (0x17) 76543210 io-7 io-6 io-5 io-4 io-3 io-2 io-1 io-0 rw rw rw rw rw rw rw rw 00000000 76543210 io-15 io-14 io-13 io-12 io-11 io-10 io-9 io-8 rw rw rw rw rw rw rw rw 00000000 [7:0] io - x write ?1? to set the corresponding gpio to alternate function (io) write ?0? to set the corresponding gpio to primary function (capacitive sensor)
stmpe16m31px, stmpe24m31px pwm array controller doc id 17058 rev 1 37/82 10 pwm array controller the stmpe24m31px integrates 8 independent pwm controllers capable of blinking and brightness control. each of the pwm controllers can be programmed to execute a series of blinking/brightness control actions. one pwm controller could be mapped to more than one gpio, allowing multiple gpio outputs to share a pwm controller. each pwm controller can be connected to any of gpio channel through the routing network which is controlled by gpion_pwm_cfg register (n = gpio channel number). figure 9. pwm array controller 07-#( 07-#( 2outingnetwork '0)/
pwm array controller stm pe16m31px, stmpe24m31px 38/82 doc id 17058 rev 1 gpio_pwm_cfg pwm array controller address: 0x20-2f type: rw reset: 0x00 description: this register controls the routing networ k which connects each pwm channel to any gpio channel. gpion_pwm_cfg register (n=0-15, represent the gpio channel number) 76543210 out_en reserved out_idle pwm_sel rw rw rw rw rw rw rw rw 00000000 [7] out_en: write ?1? to set the i/o (configured as gpio) to operate as pwm output. all gpio register setting will be by-passed. [6:4] reserved [3] out_idle: write ?1? to set the i/o state to high after pwm sequence has been completed write ?0? to set the i/o state to lo w after pwm sequence has been completed [2:0] pwm_sel: write ?1? to set the i/o state to high after pwm sequence has been completed write ?0? to set the i/o state to lo w after pwm sequence has been completed
stmpe16m31px, stmpe24m31px pwm controller doc id 17058 rev 1 39/82 11 pwm controller the pwm controller allows to control the brightness, ramping/fading and blinking of leds. the stmpe24m31px/16m31px features 8 independent pwm controllers. the pwm controllers outputs are connected to the gpio through the pwm array controller. the pac provides the following list of flexibility to the overall pwm?s system: ? each gpio may utilize the output of 1 of the 8 pwm controllers. ? up to 16 gpio may be controlled by the same pwm at the same time. ? each of the pwm could be programmed to be triggered by a touch sensing input. the pwm controller uses a base clock of 512 khz, clock pulses have a variable duty cycle of 0 to 100% in 16 steps. the pwm?s frequency is 32 khz (to be out of audio range). 11.1 pwm function register map this section lists and describes the pwm function registers of the stmpe16m31px and stmpe24m31px devices, starting with a register map and then provides detailed descriptions of register types. table 12. pwm function registers address register name reset value r/w description 0x30 pwm_mater_en 0x00 rw pwm master enable 0x40 pwm_0_set 0x00 rw pwm0 setup 0x41 pwm_0_ctrl 0x00 rw pwm0 control 0x42 pwm_0_ramp 0x00 rw pwm0 ramp rate 0x43 pwm_0_trig 0x00 rw pwm0 trigger 0x44 pwm_1_set 0x00 rw pwm1 setup 0x45 pwm_1_ctrl 0x00 rw pwm1 control 0x46 pwm_1_ramp 0x00 rw pwm1 ramp rate 0x47 pwm_1_trig 0x00 rw pwm1 trigger 0x48 pwm_2_set 0x00 rw pwm2 setup 0x49 pwm_2_ctrl 0x00 rw pwm2 control 0x4a pwm_2_ramp 0x00 rw pwm2 ramp rate 0x4b pwm_2_trig 0x00 rw pwm2 trigger 0x4c pwm_3_set 0x00 rw pwm3 setup 0x4d pwm_3_ctrl 0x00 rw pwm3 control 0x4e pwm_3_ramp 0x00 rw pwm3 ramp rate 0x4f pwm_3_trig 0x00 rw pwm3 trigger
pwm controller stmpe16m 31px, stmpe24m31px 40/82 doc id 17058 rev 1 pwm_master_en master enable register address: 0x30 type: rw reset: 0x00 description: enable/disable setting of all pwm channels. address register name reset value r/w description 0x50 pwm_4_set 0x00 rw pwm4 setup 0x51 pwm_4_ctrl 0x00 rw pwm4 control 0x52 pwm_4_ramp 0x00 rw pwm4 ramp rate 0x53 pwm_4_trig 0x00 rw pwm4 trigger 0x54 pwm_5_set 0x00 rw pwm5 setup 0x55 pwm_5_ctrl 0x00 rw pwm5 control 0x56 pwm_5_ramp 0x00 rw pwm5 ramp rate 0x57 pwm_5_trig 0x00 rw pwm5 trigger 0x58 pwm_6_set 0x00 rw pwm6 setup 0x59 pwm_6_ctrl 0x00 rw pwm6 control 0x5a pwm_6_ramp 0x00 rw pwm6 ramp rate 0x5b pwm_6_trig 0x00 rw pwm6 trigger 0x5c pwm_7_set 0x00 rw pwm7 setup 0x5d pwm_7_ctrl 0x00 rw pwm7 control 0x5e pwm_7_ramp 0x00 rw pwm7 ramp rate 0x5f pwm_7_trig 0x00 rw pwm7 trigger table 12. pwm function registers (continued) 76543210 en7 en6 en5 en4 en3 en2 en1 en0 rw rw rw rw rw rw rw rw 00000000 [7:0] en-x (x = 7-0) write ?1? to enable the corresponding pwm channel read ?0? if the pwm sequence is completed if pwm is set to be touch sensor-triggered : read ?1? if the corresponding pwm channel is running
stmpe16m31px, stmpe24m31px pwm controller doc id 17058 rev 1 41/82 pwm_n_set pwm-n setup register address: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c type: rw reset: 0x00 description: setting of brightness, time unit and ramp-mode. 76543210 brigthness timing rampmode rw rw rw rw rw rw rw rw 00000000 [7:4] brightness: it defines the duty cycle during the on period of the pwm channel output in no-ramp mode or the highest duty cycle to be reached in ramp-mode. the pwm duty cycle determines the brightness level of the led t hat the pwm output drives. ?0000? : duty cycle ratio 1:15 ( 6.25%, minimum brightness) ?0001? : duty cycle ratio 2:14 (12.50%) ?0010? : duty cycle ratio 3:13 (18.75%) ?0011? : duty cycle ratio 4:12 (25.00%) ?0100? : duty cycle ratioo 5:11 (31.25%) ?0101? : duty cycle ratio 6:10 (37.50%) ?0110? : duty cycle ratio 7: 9 (43.75%) ?0111? : duty cycle ratio 8: 8 (50.00%) ?1000? : duty cycle ratio 9: 7 (56.25%) ?1001? : duty cycle ratio 10: 6 (62.50%) ?1010? : duty cycle ratio 11: 5 (68.75%) ?1011? : duty cycle ratio 12: 4 (75.00%) ??1100 ?: duty cycle ratio 13: 3 (81.25%) ??1101 ?: duty cycle ratio 14: 2 (87.50%) ?1110? : duty cycle ratio 15: 1 (93.75%) ?11 11? : duty cycle ratio 16: 0 (100.00%, maximum brightness). [3:0] timing: it is the time unit from which the duration of the on period and off period is defined in pwm- n control register. ?000? = 20 ms ?001? = 40 ms ?010? = 80 ms ?011? = 160 ms ?100? = 320 ms ?101? = 640 ms ?110? = 1280 ms ?111? = 2560 ms [0] ramp mode: write ?1? to enable ramp-mode write ?0? to disable ramp-mode which in this setting the output goes to the set brightness level
pwm controller stmpe16m 31px, stmpe24m31px 42/82 doc id 17058 rev 1 pwm_n_ctrl pwm-n control register address: 0x41, 0x45, 0x49, 0x4d, 0x51, 0x55, 0x59, 0x5d type: rw reset: 0x00 description: setting of on/off period, repetition, and on/off order. 76543210 period 0 period 1 repetition order rw rw rw rw rw rw rw rw 00000000 [7:6] period 0 define the on time based on time unit set in pwm-n setup register ?00? : 1 time unit ?01? : 2 time unit ?10? : 3 time unit ?11? : 4 time unit [5:4] period 1 define the off time based on time unit set in pwm-n setup register ?00? : 1 time unit ?01? : 2 time unit ?10? : 3 time unit ?11? : 4 time unit [3:1] repetition set the repetition of programmed seque nce (pair of period 0 and period 1) ?000? : infinite repetition ?001? : execute only one pair ?010? : execute 2 pairs ?011? : execute 3 pairs ?100? : execute 4 pairs ?101? : execute 5 pairs ?110? : execute 6 pairs ?111? : execute 7 pairs [0] order set the order of period 0 and period 1 ?1? : sequence = period 1 and then period 0 ?0? : sequence = period 0 and then eriod 1
stmpe16m31px, stmpe24m31px pwm controller doc id 17058 rev 1 43/82 pwm_n_ramp_rate pwm-n ramp rate register address: 0x42, 0x46, 0x4a, 0x4e, 0x52, 0x56, 0x5a, 0x5e type: rw reset: 0x00 description: setting of ramp rate 76543210 inv reserved rampdown rampup rw rw rw rw rw rw rw rw 00000000 [7] inv led driving/sinking mode write ?1? for led sinking mode (high = led off, low = led on) write ?0? for led driving mode (high = led on, low = led off [6] reserved [5:3] rampdown set the pwm ramp down rate ?000? : 1/4 of time unit per brightness level change ?001? : 1/8 of time unit per brightness level change ?010? : 1/16 of time unit per brightness level change ?011? : 1/32 of time unit per brightness level change ?100? : 1/64 of time unit per brightness level change ?101? : 1/128 of time unit per brightness level change ?110? : reserved ?111? : reserved [2:0] rampup set the pwm ramp up rate ?000? : 1/4 of time unit per brightness level change ?001? : 1/8 of time unit per brightness level change ?010? : 1/16 of time unit per brightness level change ?011? : 1/32 of time unit per brightness level change ?100? : 1/64 of time unit per brightness level change ?101? : 1/128 of time unit per brightness level change ?110? : reserved ?111? : reserved
pwm controller stmpe16m 31px, stmpe24m31px 44/82 doc id 17058 rev 1 pwm_n_trig pwm-n trigger register address: 0x43, 0x47, 0x4b, 0x4f, 0x53, 0x57, 0x5b, 0x5f type: rw reset: 0x00 description: setting of touch sensor-triggered pwm. 76543210 reserved en ts_ch rw rw rw rw rw rw rw rw 00000000 [7:6] reserved [6:5] en: write ?1? to enable touch sensor-triggered pwm function write ?0? to disable touch s ensor-triggered pwm function [4:0] ts_ch define the touch sensor channel which is set as trigger of the corresponding pwm channel.
stmpe16m31px, stmpe24m31 px basic pwm programming doc id 17058 rev 1 45/82 12 basic pwm programming the pwm controllers are capable of generating the following brightness patterns: figure 10. pulses with programmable br ightness, on/off period and repetition the registers need to be programmed for this sequence: ? on period = period 0[1:0] * time unit [3:0] ? off period = period 1[1:0] * time unit [3:0] ? duty cycle during on period = brightness [7:4] ? number of cycles = repetition [3:0] ? ramp-mode is disabled figure 11. ramps with programmable brightness, on/off period and repetition $utycycle 4ime /.period /ffperiod /.period /ffperiod timeunit 4ime /.period /ffperiod /.period /ffperiod timeunit $utycycle
basic pwm programming stm pe16m31px, stmpe24m31px 46/82 doc id 17058 rev 1 the registers need to be programmed for this sequence : ? on period = period 0[1:0] * time unit [3:0] ? off period = period 1[1:0] * time unit [3:0] ? duty cycle during on period = brightness [7:4] ? number of cycles = repetition [3:0] ? ramp-mode is enabled ? ramp up/down rate is programmable figure 12. fixed brightness output ? on period = period 0[1:0] * time unit [3:0] ? off period = don?t care ? duty cycle during on period = brightness [7:4] ? number of cycles = repetition [3:0] = 0 (infinite repetition) !-6 $utycycle timeunit 4ime
stmpe16m31px, stmpe24m31 px basic pwm programming doc id 17058 rev 1 47/82 12.1 interrupt on basic pwm controller a basic pwm controller could be programmed to generate interrupt on completion of blinking sequence. user needs to consider: a) each basic pwm controller has its own bit in interrupt enable/status registers. if enabled, the completion in any of the pwm controllers triggers an interrupt. no interrupt will be generated if infinite repetition is set.
touch sensor controller stmpe16m31px, stmpe24m31px 48/82 doc id 17058 rev 1 13 touch sensor controller the stmpe16m31px and stmpe24m31px device s use the stmicroelectronics? patent pending capacitive front end. the capacitive sensor is configure by the following registers: table 13. touch sensor controller registers address register name reset value r/w description 0x70 ch_sen_ctrl 0x00 rw capacitive sensor control 0x72 ch_sel 0x00000000 rw selects active capacitive channels 0x76 cal_int 0x00 rw 10ms ? 64s calibration interval 0x77 cal_mod 0x00 rw selects calibration model 0x78 maf_set 0x00 rw median averaging filter (maf) setting 0x7c data_type 0x00 rw selects type of data available in channel data ports. 0x01: tvr 0x02: evr 0x03: channel delay 0x04: impedance (13-bit) 0x05: calibrated impedance (13-bit) 0x06: locked impedance (13-bit) 0xc0-0xef ch_data-n 0x0000 r/w channel data based on channel data type
stmpe16m31px, stmpe24m31px touch sensor controller doc id 17058 rev 1 49/82 figure 13. touch sensing module flowchart 13.1 sampling rate calculation the capacitive sensor operates with a 2 mhz base clock, a single capacitive sensor scans up to 24 active channels. the sclk_div divides the sensor clock by 32- 1024, giving 2 khz-67.5 khz sensor clock. for capacitive sensing, a prbs sequence is ut ilized to remove the ef fect of surrounding noise. this prbs has an average value of 4.5. the effective total sampling rate is thus 2 khz-67.5 khz divided by 4.5, giving 440 hz ? 14 khz. if all 24 channels of capacitive sensors are active, the channel conversion rate is thus 440 hz/24 = 18.3 hz (min), 14 khz/24 = 580 hz (max) using the maximum maf setting (18 remove 2), the maximum filtered channel output rate is 580 hz/18 = 32hz. !-6 -edian filterandaveraging algorithmoneachchannel -edian filter average stepsf&stepp&range )ndividual referencedelayregister /ptionalexternal#ref 0rogrammabl ecalibrationinterval -ultiple calibration models #alibrationwillbeperformedonlyonnon touch channels !ctivec hannelchannelselection #omparingcurrentimpedancewithcalibrated impedance462with(93effect 4ouchkey )mpedance sensor 3ignal conditioning !utomatic calibrationunit 4ouch detectionunit +eyfiltering +eyfilteringunitselectsthestrongest touchamongactivechannels
touch sensor controller stmpe16m31px, stmpe24m31px 50/82 doc id 17058 rev 1 13.2 sensor resolution the capacitive sensor hardware in the stmpexxm31 devices has a sensitivity of 15 ff and a range of 512 steps giving it a dynamic range of 7.5 pf. the impedance reading is the output of an internal maf (median removal filter). as up to 16 samples are taken for each reading, the impedance reading is the sum of 16 of 9-bit samples. to allow maximum consistency, the 3 impedance readings are always 13-bit, whichever maf setting is used. the touch variance (tvr) and enviromental variance (evr) are specified in a 9-bit format. for comparison with the impedances, the tvr and evr would be internally shifted 4 bits up. 13.3 auto tuning the capacitive sensor hardware in the stmpexxm31 devices has a sensitivity of 15 ff and a range of 512 steps giving it a dynamic range of 7.5 pf. this means that at any time, the device is able to sense a change in capacitance up to 7.5 pf. when the channel capacitance moves out of the 7.5 pf window, the auto tuning feature kicks in to ensure proper sensing operation.
stmpe16m31px, stmpe24m31px touch sensor controller doc id 17058 rev 1 51/82 figure 14. auto tuning operation !-6 p& sensing range p& auto tune range #h#app& sensing windowat p& #h#app& sensing windowat p& #h#app& sensing windowat p& #h#app& sensing windowat p& additional capacitor required
touch sensor controller stmpe16m31px, stmpe24m31px 52/82 doc id 17058 rev 1 13.4 locked impedance locked impedance is data available in channel data the moment 0x06 is written into ?channel data type register?. writing a different value into the ?channel data type register? allows the locked impedance to be refreshed. in actual application, software writes 0x06, reads locked impedance, writes 0x00, writes 0x06, and reads the next set of data. for data type 0x04-0x05, data are constantly be ing refreshed, even as it is being accessed. if accessed slowly, the full set of data may have been sampled at significantly different time. 13.5 calibration calibration event is performed in every period which is programmable from the calibration interval register (0x76). in each calibration event, 8 impedance samples are collected and averaged. the time period between samples is programmable from cal_mod (model register (0x77). figure 15. calibration !-6 #alibration #alibration #alibration #alibration samplingx #alibration)nterval
stmpe16m31px, stmpe24m31px touch sensor controller doc id 17058 rev 1 53/82 cap_sen_ctrl capacitive sens or control register address: 0x70 type: rw reset: 0x00 description: this register controls the capacitive sensor?s operation. 76543210 cs_en hys forcedat rw rw rw rw rw rw rw rw 00000000 [7] cs_en write ?1? to enable the capacitive sensor module write ?0? to disable the capacitive sensor module this bit should be set after all other touch sens or setting have been written. the changes in other setting when this bit is ?1? is not allowed. if ratio-engine or key-filter unit is used, this bi t should only be set, after ratio-engine and key- filter unit has been configured. [6:1] hys tvr hysteresis when there is no touch, the va lue of tvr is used as threshol d to determine touch condition. if touch is detected, the touch detection thre shold is changed to tvr-(hys*4), hence the effective value of hysteresis is 0-256. [0] forcedat write ?1? to initiate unconditional forced auto-tu ning to center the static impedance value in the dynamic range. prior sending this command, the calibration model must be set to mode ?10? with auto-tuning enabled. read ?1? if the auto-tuning process in progress read ?0? if the auto-tuning process has been completed. it is required that upon start up th e system, this command is called once. when the auto-tuning is executed in the presenc e of finger on the sensor, the ?touch? status will become ?no-touch? after completion of the proces s. once finger is removed, the auto-calibration will take care of this situation allowi ng the detection of next ?touch? event.
touch sensor controller stmpe16m31px, stmpe24m31px 54/82 doc id 17058 rev 1 ch_sel channel selection register address: 0x72-0x74 type: rw reset: 0x000000 description: this register configures the active capacitive sensing channels. bit 7-0 (0x72) bit 15-8 (0x73) bit 23-16 (0x74) 76543210 s7 s6 s5 s4 s3 s2 s1 s0 rw rw rw rw rw rw rw rw 00000000 76543210 s15 s14 s13 s12 s11 s10 s9 s8 rw rw rw rw rw rw rw rw 00000000 76543210 s23 s22 s21 s20 s19 s18 s17 s16 rw rw rw rw rw rw rw rw 00000000 [7:0] s-x write ?1? to enable the corresponding capacitive sensor channel write ?0? to disable the corresponding capacitive sensor channel
stmpe16m31px, stmpe24m31px touch sensor controller doc id 17058 rev 1 55/82 cal_int calibration interval configuration register address: 0x76 type: rw reset: 0x00 description: this register configures the interval between successive calibrations. 76543210 multiplier interval rw rw rw rw rw rw rw rw 00000000 [7:6] multiplier set the multiplier value for calibration interval set in interval[5:0] ?00? for 8 ?01? for 32 ?10? for 128 ?11? for 512 [5:0] interval set the calibration interval calibration interval : = interval[5:0]*10 ms * multiplier.
touch sensor controller stmpe16m31px, stmpe24m31px 56/82 doc id 17058 rev 1 cal_mod calibration mode register address: 0x77 type: rw reset: 0x00 description: this register configures the way calibration samples are collected, and the model of calibration algorithm. 76543210 csinterval model cal_en rw rw rw rw rw rw rw rw 00000000 [7:3] csinterval set the interval between samples in one calibration unit interval = csinterval[4:0]*10ms [2:1] imodel set the calibration model ?00? for normal auto-calibration ?10? for auto-calibration with auto-tuning. in this mode channel reference delay is not accessible from i2c. the system will perfor m auto-tuning if the impedance is moving out of dynamic range. ?01? is reserved ?11? is reserved [0] cal_en ?1? to enable the auto-calibration ?0? to disable the auto-calibration
stmpe16m31px, stmpe24m31px touch sensor controller doc id 17058 rev 1 57/82 maf_set median averaging filter register address: 0x78 type: rw reset: 0x00 description: this register chooses the median averaging filter mode. data_type data type definition register address: 0x7c type: rw reset: 0x00 description: this register define the type of data to be accessed at capacitive channel data register. 76543210 reserved maf_mode maf_en rw rw rw rw rw rw rw rw 00000000 [2:1] maf_mode ?00? to collect 10 samples, remove 2 samples ?01? to collect 18 samples, remove 2 samples ?10? to collect 20 samples, remove 4 samples [0] maf_en ?1? enable the maf ?0? disable the maf 76543210 mode rw rw rw rw rw rw rw rw 00000000 [7:0] mode 0x01: tvr (9-bit) 0x02: evr (9-bit) 0x03: channel delay (6-bit) 0x04: impedance (13-bit) 0x05: calibrated impedance (13-bit) 0x06: locked impedance (13-bit)
touch sensor controller stmpe16m31px, stmpe24m31px 58/82 doc id 17058 rev 1 ch_data-n chdata-n registers (0-23) address: 0xc0-0xef type: rw reset: 0x00 description: capacitive sensor channel data. the type of data represented by this register depends on the channel data type register (0x7c). lsb, address : 0xc0 + (2 *n), n = channel number msb, address : 0xc0 + (2 *n+1), n = channel numer 76543210 channel n data [7:0] rw rw rw rw rw rw rw rw 00000000 76543210 channel n data [15:8] rw rw rw rw rw rw rw rw 00000000 [16:0] channel data display data selected by channel data type register (0x7c)
stmpe16m31px, stmpe24m31px touch sensor controller doc id 17058 rev 1 59/82 13.6 definition of data accessib le through channel data register table 14. types of data accessible through the channel data register data name definition tvr tvr (touch variance register) is a th reshold defined by system, of which, if the sense impedance changed by a m agnitude more than the associated tvr, this channel is considered touched. the result of this comparison is directly accessible in the touch_det register. evr evr (environmental variance register) is a threshold defined by system, of which, if the sensed impedance cha nged by a magnitude less than the associated evr, this is considered an environmental change and the device will calibrate the internal reference (calibrated impedance) accordingly. channel delay channel delay is used to tune the individual channel into effective measurement range. this field is 6-bit (0-63). each bit in this field represents approximately 0.5 pf capacitance. impedance this field is a real time reflection of impedance measured at the corresponding channel. as capacitance is inversely proportional to impedance, this field reduces in value when capacitance on the channel increases. this field is of 13-bit length. the least significant 4 bits are results of internal processing and should not be used. t he actual impedance data could be obtained by shifting the [imped ance] 4 bits to the right. calibrated impedance read-only this field contains an internal reference used by the device to decide whether a touch has occurred. this value is ad justed regularly (calibration) by the device automatically. locked impedance data in this field is similar to data in impedance field, except that once this data type is chosen, the device mainta ins a complete set of impedance data in this field and stop refreshing it. this is useful for the application wher e it is required that all impedance data are sampled within a very short time.
touchkey and proximity sensing controller stmpe16m31px, stmpe24m31px 60/82 doc id 17058 rev 1 14 touchkey and proximity sensing controller the touchkey controller processes raw capacitance measurement data into ?touch/no- touch? boolean data for easy usage. the key filter unit provides additional flexibility by allowing the system to define a maximum number of keys that could be detected and considered active, based on the amount of impedance change detected. the proximity sensor using a technique called ?dithering? to increase the sensitivity of one selected channel. dithering factor (configurable from 4 - 32x) determines the sensitivity of proximity sensor. table 15. touchkey controller registers address register name reset value r/w description 0x90 kfu_prox_ctrl 0x00 r/w key filter and proximity sensor control 0x92 key_filt_group1 0x00000000 r/w define channels included in key filter group 1 0x96 prox_cfg 0x00 r/w proximity configuration register 0x97 ptvr 0x00 r/w proximity variance register (ptvr) 0x98 pevr 0x00 r/w proximity enviromental variance register 0xb0 prox_data_0 0x00 r proximity data port 0 0xb1 prox_data_1 0x00 r proximity data port 1 0x9a key_filt_data 0x00000000 r filtered touchkey data 0xb4 touch_det 0x00000000 r touch detection register (real time)
stmpe16m31px, stmpe24m31px touchkey and proximity sensing controller doc id 17058 rev 1 61/82 figure 16. data flow in touchkey controller !-6 #( +&'2/50 bitmap or!,, +&$!4! buffereddata 4ouchdetectionrealtimedata #( #( #( #( #( #( #( #( #( #( #(
touchkey and proximity sensing controller stmpe16m31px, stmpe24m31px 62/82 doc id 17058 rev 1 key_prox_ctrl key filter un it configuration register address: 0x90 type: rw reset: 0x00 description: setting of key filter unit. 76543210 prox_chl_select reserved prox_en mode_kfu1 rw rw rw rw rw rw rw rw 00000000 [7:4] prox_chl_select: chooses one of the first 16 sensing channel as proximity sebsor input [3] reserved [2] prox_en: write ?1? to enable proximity sensing operation [1:0] mode_kfu ?00? for no filter ?01? for 1 highest impedance change ?10? for 2 highest impedance change ?11? for 3 highest impedance change
stmpe16m31px, stmpe24m31px touchkey and proximity sensing controller doc id 17058 rev 1 63/82 key_filt_group-1 kfgroup-1 address: 0x92-0x94 (keyfiltermask1) type: r/w reset: 0x000000 description: configure the channels included in a group of key filter unit. bit 7-0 (0x92) bit 15-8 (0x93) bit 23-16 (0x94) 76543210 s7 s6 s5 s4 s3 s2 s1 s0 rw rw rw rw rw rw rw rw 00000000 76543210 s15 s14 s13 s12 s11 s10 s9 s8 rw rw rw rw rw rw rw rw 00000000 76543210 s23 s22 s21 s20 s19 s18 s17 s16 rw rw rw rw rw rw rw rw 00000000 [23:0] s-x write ?1? to include the corresponding channel in a group of key filter unit
touchkey and proximity sensing controller stmpe16m31px, stmpe24m31px 64/82 doc id 17058 rev 1 key_filt_data key filter data register address: 0x9a-0x9c type: rw reset: 0x000000 description: represent the status of (touch/no-touch), after being filtered by key filter unit. this register is always active and key status can be accessed from this register regardless of key filter unit activity. bit 7-0 (0x9a) bit 15-8 (0x9b) bit 23-16 (0x9c) 76543210 s7 s6 s5 s4 s3 s2 s1 s0 rw rw rw rw rw rw rw rw 00000000 76543210 s15 s14 s13 s12 s11 s10 s9 s8 rw rw rw rw rw rw rw rw 00000000 76543210 s23 s22 s21 s20 s18 s2 s17 s16 rw rw rw rw rw rw rw rw 00000000 [23:0] s-x read ?1? if the corresponding sensor channel status is ?touched?.
stmpe16m31px, stmpe24m31px touchkey and proximity sensing controller doc id 17058 rev 1 65/82 touch_det touchkey detection register address: 0xb4-b6 type: rw reset: 0x000000 description: represents the real time status of the touc hkey input. this is a direct result of comparison of sensed impedance with calibrated impedance (taking in account of hysteresis). this data is not buffered. bit 7-0 (0xb4) bit 15-8 (0xb5) 76543210 s7 s6 s5 s4 s3 s2 s1 s0 rw rw rw rw rw rw rw rw 00000000 [s23:s16] 76543210 s15 s14 s13 s12 s11 s10 s9 s8 rw rw rw rw rw rw rw rw 00000000 [s15:s6]
touchkey and proximity sensing controller stmpe16m31px, stmpe24m31px 66/82 doc id 17058 rev 1 bit 23-16 (0xb6) prox_cfg proximity configuration register address: 0x96 type: rw reset: 0x00 description: proximity configuration register. 76543210 s23 s22 s21 s20 s19 s18 s17 s16 r/w r/w rw/ r/w r/w r/w r/w r/w 00000000 [7:0] s-x read ?1? if the corresponding sensor channel status is ?touched? 76543210 dithering reserved proximity calibration interval access mode r/w r/w r/w r/w r/w r/w r/w r/w 00000000 [7:6] dithering factor 00 - 4x 01 -8x 10 -16x 11-32x the higher the dithering factor, the more sensitiv e the proximity sensing is. however, the speed will be slower. [5] reserved [4:2] proximity calibration interval: 000-1 001-2 010-4 011-8 100-16 others: reserved controls the number of dithered impedance sampling between successive calibrations. shorter calibration interval allows it to adapts quickly to changes in environmental factors, but reduces the sensitivity to slowly approaching hand. [1:0] access mode: 00-dithered impedance 01- calibrated dithered impedance others: reserved
stmpe16m31px, stmpe24m31px touchkey and proximity sensing controller doc id 17058 rev 1 67/82 ptvr proximity variance register address: 0x97 type: rw reset: 0x00 description: proximity variance register. typical value is 0x08 - 0x20
touchkey and proximity sensing controller stmpe16m31px, stmpe24m31px 68/82 doc id 17058 rev 1 pevr proximity envirom ental variance register address: 0x98 type: rw reset: 0x00 description: proximity enviromental variance register. writing '1' to this bit forces the proximity sensing module to use the current dithered impedance as calibrated dithered impedance. after writing '1' to this bit, i2c should monitor the calibration status bit ( prox data port 1, bit 6). on reading '1' in calibration status bit, i2c must write '0' in forced pr oximity calibration bi t to complete the calibration action. prox data port proximity data port address: 0xb0 (lsb), 0xb1 (msb) type: r reset: 0x00 description: proximity data port. [7] forced proximity calibration [6] evr used for proximity detection. typically value of 0x02-0x05 is used. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 prox_sta cal_sta reserved ???? [7:6] proximity status: real-time status of proximity sensor [14] calibration status: reads '1' if calibration is completed. reads '0' if i2c executes a forced calibration [13] reserved [12:0] 13 bit dithered impedan ce/calibrated dithered impedance
stmpe16m31px, stmpe24m31px maximum rating doc id 17058 rev 1 69/82 15 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. 15.1 recommended op erating conditions table 16. absolute maximum ratings symbol parameter value unit v cc supply voltage 2.5 v v io gpio and vreg supply voltage 6 v vesd (hbm) esd protection on each gpio/touch pin 8 kv table 17. recommended operating conditions symbol parameter value unit min max v cc supply voltage 1.65 1.95 v v io gpio supply voltage 2.7 5.5 v gpio gpio input voltage gnd-0.5 vio+0.5 kv
dc electrical characteristic s stmpe16m31px, stmpe24m31px 70/82 doc id 17058 rev 1 16 dc electrical characteristics -40 to 85 c unless stated otherwise. table 18. dc electrical characteristics symbol parameter test conditions value unit min typ max vcc core supply voltage 1.65 - 1.95 v vio io supply voltage 2.7 - 5.5 v iactive active current 2 mhz/32 sensor clock, proximity engine active - 600 900 a iactive active current 2 mhz/32 sensor clock, with/without touch, key only - 400 600 a isleep sleep current 2 mhz/32 sensor clock, without touch -5075a ihibernate hibernate current no sensing capability. hotkey available -5 8a vil input voltage low state (reset/a0/a1/i2c) v cc = 1.8 v -0.3v - 0.35vcc v vih input voltage high state (reset/a0/a1/i2c) v cc =1.8v 0.75vc c - vcc+0.3 v v vil input voltage low state (gpio) v io = 2.7 - 5.5 v -0.3v - 0.35vio v vih input voltage high state (gpio) v io = 2.7 - 5.5 v 0.65vio - vio+0.3 v v vol output voltage low state (gpio) v io =2.7-5.5v, i ol =12ma -0.3v - 0.25vio v voh output voltage high state (gpio) v io = 2.7- 5.5 v, i ol =12ma 0.75vio - vio+0.3 v v i leakage input leakage on all gpio/touch pins v io =5.5v, v cc powered by v io , i/o set as input, 5.5 v applied to i/o --100na
stmpe16m31px, stmpe24m31px dc electrical characteristics doc id 17058 rev 1 71/82 16.1 capacitive se nsor specification -40 to 85 c unless stated otherwise. symbol parameter test conditions value unit min typ max cs capacitive sensor sensitivity v io = 2.7 - 5.5 v, internal v reg 12 16 20 ff csvr variance of cs across channels v io = 2.7 - 5.5 v, internal v reg -10 -%
package mechanical data st mpe16m31px, stmpe24m31px 72/82 doc id 17058 rev 1 17 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stmpe16m31px, stmpe24m31px package mechanical data doc id 17058 rev 1 73/82 figure 17. package outline for qfn40 (5 x 5 mm) - pitch 0.4 mm
package mechanical data st mpe16m31px, stmpe24m31px 74/82 doc id 17058 rev 1 table 19. package mechanical data for qfn40 (5 x 5 mm) - pitch 0.4 mm figure 18. qfn40 recommended footprint without ground pad via symbol millimeters min typ max a 0.80 0.85 0.90 a1 0.02 0 0.05 a3 -0.203 - - b 0.20 0.15 0.25 d 5 4.90 5.10 d2 3.80 3.70 3.90 e 5 4.90 5.10 e2 3.80 3.70 3.90 e0.40- - l 0.35 0.25 0.45
stmpe16m31px, stmpe24m31px package mechanical data doc id 17058 rev 1 75/82 figure 19. qfn40 recommended footprint with ground pad via 0.30 0.68 0.68 1.27 1.27 via
package mechanical data st mpe16m31px, stmpe24m31px 76/82 doc id 17058 rev 1 figure 20. tape information for qfn40 (5 x 5 mm) - pitch 0.4 mm
stmpe16m31px, stmpe24m31px package mechanical data doc id 17058 rev 1 77/82 figure 21. reel information for qfn40 (5 x 5 mm) - pitch 0.4 mm
package mechanical data st mpe16m31px, stmpe24m31px 78/82 doc id 17058 rev 1 figure 22. package outline for qfn32 (4 x 4 mm) - pitch 0.4 mm poa_qfn 3 2_ 8 1 8 69 8 6_a
stmpe16m31px, stmpe24m31px package mechanical data doc id 17058 rev 1 79/82 table 20. package mechanical data for qfn32 (4 x 4 mm) - pitch 0.4 mm symbol millimeters min typ max a 0.70 - 0.90 a1 0.03 0.05 0.08 a3 - 0.20 - b 0.19 0.21 0.28 d 3.85 4.00 4.15 d2 1.9 - 2.1 e 3.85 4.00 4.15 e2 1.9 - 2.1 e-0.40- e/2 - 0.20 - l 0.10 0.20 0.30
package mechanical data st mpe16m31px, stmpe24m31px 80/82 doc id 17058 rev 1 figure 23. footprint recommendation for qfn32 (4 x 4 mm) - pitch 0.4 mm qfn 3 2_fr
stmpe16m31px, stmpe24m 31px revision history doc id 17058 rev 1 81/82 18 revision history table 21. document revision history date revision changes 08-feb-2010 1 initial release.
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