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w27E512 64k 8 electrically eras able eprom publication release date: june 2000 - 1 - revision a9 general description the w27E512 is a high speed, low power electrically erasable and programmable read only memory organized as 65536 8 bits that operates on a single 5 volt power supply. the w27E512 provides an electrical chip er ase function. features high speed access time: 45/55/70/90/120/150 ns (max.) read operating current: 30 ma (max.) erase/programming operating current 30 ma (max.) standby current: 1 ma (max.) single 5v power supply +14v erase/+12v programming voltage fully static operation all inputs and outputs dir ectly ttl/cmos compatible three - state outputs available p ackages: 28 - pin 600 mil dip, 330 mil sop, tsop and 32 - pin plcc pin configurations 26 27 28 1 2 3 4 5 6 7 8 21 22 23 24 25 16 17 18 19 20 9 10 11 12 13 14 15 q3 ce q7 q6 q5 q4 a9 a11 oe/vpp a10 a14 a13 a8 gnd q2 q1 a0 a1 a2 a3 a4 a5 a6 a7 a12 q0 v cc 28-pin dip a15 a6 a5 a4 a3 a2 a1 a0 nc q0 5 6 7 8 9 10 11 12 13 1 4 4 3 2 1 3 2 3 1 3 0 29 28 27 26 25 24 23 22 21 32-pin plcc q 1 q 2 n c q 3 q 4 q 5 g n d 1 5 1 6 1 7 1 8 1 9 2 0 a 7 n c a 1 2 a 1 4 a 1 3 v c c a8 a9 a11 nc oe/vpp a10 q7 ce q6 a 1 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin tsop q3 ce q7 q6 q5 q4 a10 gnd q2 q1 a0 a1 a2 q0 a9 a11 oe/vpp a14 a13 a8 a3 a4 a5 a6 a7 a12 v cc a15 block diagram ce oe/v control output buffer decoder core array q0 q7 . . a0 . . gnd v cc pp a15 pin de scription symbol description a0 - a15 address inputs q0 - q7 data inputs/outputs ce chip enable oe /v pp output enable, program/erase supply voltage v cc power supply gnd ground nc no connection
w27 e512 - 2 - functional descripti on read mode like conventional uveproms, the w27E512 has two control functions, both of which produce data at the outputs. ce is for power control and chip select. oe /v pp controls the output buffer to gate data to the output pins. when addresses are stable, the address access time (t acc ) is equal to the delay from ce to output (t ce ), and data are available at the outputs t oe after the falling edge of oe /v pp , if t acc and t ce timings are met. erase mode the erase operation is the only way to change data from "0" to "1." unlike conventional uveproms, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the w27E512 uses elec trical erasure. generally, the chip can be erased within 100 ms by using an eprom writer with a special erase algorithm. erase mode is entered when oe /v pp is raised to v pe (14v), v cc = v ce (5v), a9 = v pe (14v), a0 low, and all other addr ess pins low and data input pins high. pulsing ce low starts the erase operation. erase verify mode after an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not . the erase verify mode ensures a substantial erase margin if v cc = v ce (3.75v), ce low, and oe /v pp low. program mode programming is performed exactly as it is in conventional uveproms, and programming is the only way to change cell data from "1" to "0." the program mode is entered when oe /v pp is raised to v pp (12v), v cc = v cp (5v), the address pins equal the desired addresses, and the input pins equal the desired inputs. pulsing ce low starts the programming operation. program verify mode all of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. hence, after each byte is programmed, a program verify operation should be performed. the program verify mode automatically ensures a substantial program margin. this mode will be entered after the program operation if oe /v pp low and ce low. erase/program inhibit erase or program in hibit mode allows parallel erasing or programming of multiple chips with different data. when ce high, erasing or programming of non - target chips is inhibited, so that except for the ce and oe /v pp pi ns, the w27E512 may have common inputs.
w27E512 publication release date: june 2000 - 3 - revision a9 standby mode the standby mode significantly reduces v cc current. this mode is entered when ce high. in standby mode, all outputs are in a high impedance state, independent of oe /v pp . two - line output control since eproms are often used in large memory arrays, the w27E512 provides two control inputs for multiple memory connections. two - line control provides for lowest possible memory power dissipation and ensures that data bus cont ention will not occur. system considerations an eprom's power switching characteristics require careful device decoupling. system designers are interested in three supply current issues: standby current levels (i sb ), active current levels (i cc ), and transi ent current peaks produced by the falling and rising edges of ce . transient current magnitudes depend on the device output's capacitive and inductive loading. two - line control and proper decoupling capacitor selection will suppress trans ient voltage peaks. each device should have a 0.1 m f ceramic capacitor connected between its v cc and gnd. this high frequency, low inherent - inductance capacitor should be placed as close as possible to the device. additionally, for every eight devices, a 4.7 m f electrolytic capacitor should be placed at the array's power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductances. table of operati ng modes (v pp = 12v, v pe = 14v, v hh = 12v, v cp = 5v, v ce = 5v, x = v ih or v il ) mode pins ce oe /v pp a0 a9 v cc outputs read v il v il x x v cc d out output disable v il v ih x x v cc high z standby (ttl) v ih x x x v cc hig h z standby (cmos) v cc 0.3v x x x v cc high z program v il v pp x x v cp d in program verify v il v il x x v cc d out program inhibit v ih v pp x x v cp high z erase v il v pe v il v pe v ce d ih erase verify v il v il x x 3.75 d out erase i nhibit v ih v pe x x v ce high z product identifier - manufacturer v il v il v il v hh v cc da (hex) product identifier - device v il v il v ih v hh v cc 08 (hex)
w27 e512 - 4 - dc characteristics absolute maximum ratings parameter rating unit ambient temperature with power applied - 55 to +125 c storage temperature - 65 to +125 c voltage on all pins with respect to ground except oe /v pp, a9 and v cc pins - 0.5 to v cc +0.5 v voltage on oe /v pp pin w ith respect to ground - 0.5 to +14.5 v voltage on a9 pin with respect to ground - 0.5 to +14.5 v voltage v cc pin with respect to ground - 0.5 to +7 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the l ife and reliability of the device. dc erase characteristics (t a = 25 c 5 c, v cc = 5.0v 10%) parameter sym. conditions limits unit min. typ. max. input load current i li v in = v il or v ih - 10 - 10 m a v cc erase current i cp ce = v il, oe /v pp = v pe - - 30 ma v pp erase current i pp ce = v il, oe /v pp = v pe - - 30 ma input low voltage v il - - 0.3 - 0.8 v input high voltage v ih - 2.4 - 5.5 v output low voltage (verify) v ol i ol = 2.1 ma - - 0.45 v output high voltage (verify) v oh i oh = - 0.4 ma 2.4 - - - a9 erase voltage v id - 13.25 14 14.25 v v pp erase voltage v pe - 13.25 14 14.25 v v cc supply voltage (erase) v ce - 4.5 5.0 5.5 v v cc supply voltage (erase verify) v ce - 3.5 3.75 4.0 v note: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp .
w27E512 publication release date: june 2000 - 5 - revision a9 capacitance (v cc = 5v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit input capacitance c in v in = 0v 6 pf output capacitance c out v out = 0v 12 pf ac characteristics ac test conditions parameter conditions input pulse levels 0 to 3.0v input rise and fall times 5 ns input and output timing reference level 1.5v/1.5v output load c l = 30 pf, i oh /i ol = - 0.4 ma/2.1 ma ac test load and waveforms +1.3v 3.3k ohm 100 pf for 90/120/150 ns (including jig and scope) d (in914) out 30 pf for 45/55/70 ns (including jig and scope) input 3.0v 0v 1.5v test point test point 1.5v output
w27 e512 - 6 - read operation dc ch aracteristics (v cc = 5.0v 10%, t a = 0 to 70 c) parameter sym. conditions limits unit min. typ. max. input load current i li v in = 0v to v cc - 5 - 5 m a output leakage current i lo v out = 0v to v cc - 10 - 10 m a standby v cc current (ttl input) i sb ce = v ih - - 1.0 ma standby v cc current (cmos input) i sb1 ce = v cc 0.2v - 5 100 m a v cc operating current i cc ce = v il i ou t = 0 ma f = 5 mhz - - 30 ma input low voltage v il - - 0.3 - 0.8 v input high voltage v ih - 2.0 - v cc +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = - 0.4 ma 2.4 - - v read operation ac ch aracteristics (v cc = 5.0v 10%, t a = 0 to 70 c) parameter sym. w27E512 - 45 w27E512 - 55 w27E512 - 70 w27E512 - 90 w27E512 - 12 w27E512 - 15 unit min. max. min. max. min. max. min. max. min. max. min. max. read cycle time t rc 45 - 55 - 70 - 90 - 120 - 150 - ns chip enable access time t ce - 45 - 55 - 70 - 90 - 120 - 150 ns address access time t acc - 45 - 55 - 70 - 90 - 120 - 150 ns output enable access time t oe - 20 - 25 - 30 - 40 - 55 - 60 ns oe /v pp high to high - z out put t df - 20 - 20 - 30 - 30 - 30 - 50 ns output hold from address change t oh 0 - 0 - 0 - 0 - 0 - 0 - ns note: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp .
w27E512 publication release date: june 2000 - 7 - revision a9 dc programming chara cteristics (v cc = 5.0v 10%, t a = 25 c 5 c) parameter sym. conditions limits unit min. typ. max. input load current i li v in = v il or v ih - 10 - 10 m a v cc program current i cp ce = v il , oe /v pp = v pp - - 30 ma v pp program current i pp ce = v il , oe /v pp = v pp - - 30 ma input low voltage v il - - 0.3 - 0.8 v input high voltage v ih - 2. 4 - 5.5 v output low voltage (verify) v ol i ol = 2.1 ma - - 0.45 v output high voltage (verify) v oh i oh = - 0.4 ma 2.4 - - v a9 silicon i.d. voltage v id - 11.5 12.0 12.5 v v pp program voltage v pp - 11.75 12.0 12.25 v v cc supply voltage (program) v c p - 4.5 5.0 5.5 v ac programming/erase characteristics (v cc = 5.0v 10%, t a = 25 c 5 c) parameter sym. limits unit min. typ. max. oe /v pp pulse rise time t prt 50 - - ns data setup time t ds 2.0 - - m s ce program pulse width t pwp 95 100 105 m s ce erase pulse width t pwe 95 100 105 ms data hold time t dh 2.0 - - m s oe /v pp setup time t oes 2.0 - - m s oe /v pp hold time t oeh 2.0 - - m s data valid from ce t dv1 25 - 1 m s data valid from address change t dv2 25 - 1 m s ce high to output high z t dfp 0 - 130 ns address setup time t as 2.0 - - m s address hold time t ah 0 - - m s address hold time after ce high (erase) t ahc 2.0 - - m s oe /v pp valid after ce high t vs 2.0 - - m s oe /v pp r ecovery time t vr 2.0 - - m s address access time during erase verify (v cc = 3.75v) t acv - - 250 ns output enable access time during erase verify (v cc = 3.75v) t oev - - 150 ns note: v cc must be applied simultaneously or before v pp and removed si multaneously or after v pp .
w27 e512 - 8 - timing waveforms ac read waveform oe/vpp outputs high z high z valid output t oe t acc t oh t df v ih v il address ce address valid t ce v il v ih v ih v il erase waveform address data vcc v ih v il 5v read company sid read device sid a9=12.0v chip erase a9= 14.0v blank check read verify address valid t acc t acc da 08 data all one t as t ahc t acv d out t acv t acc t ds t dh t vcs 3.75v erase verify oe/vpp ce v ih v ih v il v il 14.0v t oe t oe t oes t prt t oeh t oev v ih t oe v ih t ce t vs t pwe t vr address valid address valid address valid always=v il il others=v il il others=v il a0=v ih d out d out others=v a0=v =250 ns =250 ns =150 ns
w27E512 publication release date: june 2000 - 9 - revision a9 timing waveforms, continued programming waveform address data oe/vpp ce v ih v il v ih v il v ih v il 12.0v v ih v il program program verify address stable address valid read verify data out data out data in stable data in stable t as t ah t as t ah t oh t ds t dh t ds t dh t dv1 t dv2 t dfp t acc t oh t oe t ce v il v il t vr t oeh t pwp t t prt ce should not be toggled during program verify period oes address valid address stable address stable
w27 e512 - 10 - smart programming al g orithm 1 start address = first location vcc = 5.0v oe/vpp = 12v program one 100 s pulse last address? address = first location x = 0 verify byte program one 100 s pulse vcc = 5.0v oe/vpp = v il compare all bytes to data original device passed pass yes increment address no increment address last address? no pass yes increment x fail x = 25 ? no device yes fail failed m m
w27E512 publication release date: june 2000 - 11 - revision a9 smart programming al gorithm 2 start address = first location vcc = 5.0v program one 100 s pulse compare all bytes to data original device passed pass increment address no increment x fail device failed m x = 0 pp x = 25? yes last address ? yes no pass fail fail pass oe/v = 12v oe/v = v pp il verify one byte oe/v = v pp il verify one byte
w27 e512 - 12 - smart erase algorith m start vcc = 5v oe/vpp = 14v increment x last address? vcc = 5v oe/vpp = v compare all bytes to ffs (hex) pass device increment address no fail fail fail device x = 0 a9 = 14v; a0 = v chip erase 100 ms pulse address = first location erase verify x = 20 ? no yes pass pass yes il vcc = 3.75v oe/vpp = v il il
w27E512 publication release date: june 2000 - 13 - revision a9 ordering information part no. access time ( n s) operating current max. ( m a) standby current max. ( m a) package w27E512 - 45 45 30 10 0 600 mil dip w27E512 - 55 55 30 100 600 mil dip w27E512 - 70 70 30 100 600 mil dip w27E512 - 90 90 30 100 600 mil dip w27E512 - 12 120 30 100 600 mil dip w27E512 - 15 150 30 100 600 mil dip w27E512s - 45 45 30 100 300 mil sop w27E512s - 55 55 30 100 300 mil sop w27E512s - 70 70 30 100 300 mil sop w27E512s - 90 90 30 100 300 mil sop w27E512s - 12 120 30 100 300 mil sop w27E512s - 15 150 30 100 300 mil sop w27E512q - 45 45 30 100 28 - pin tsop w27E512q - 55 55 30 100 28 - pin tsop w27E512q - 70 70 30 100 28 - pin tsop w27E512q - 90 90 30 100 28 - pin tsop w27E512q - 12 120 30 100 28 - pin tsop w27E512q - 15 150 30 100 28 - pin tsop w27E512p - 45 45 30 100 32 - pin plcc w27E512p - 55 55 30 100 32 - pin plcc w27E512p - 70 70 30 100 32 - pin plcc w27E512p - 90 90 30 100 32 - pin plcc w27E512p - 12 120 3 0 100 32 - pin plcc w27E512p - 15 150 30 100 32 - pin plcc notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for us e in applications where personal injury might occur as a consequence of product failure.
w27 e512 - 14 - package dimensions 28 - pin p - dip seating plane 1. dimensions d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. 1.63 1.47 0.064 0.058 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.540 0.550 0.545 13.72 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.460 1.470 37.08 37.34 0 15 0.090 2.29 0.650 0.630 16.00 16.51 4. dimension b1 does not include dambar protrusion/intrusion. 5. controlling dimension: inches. 15 0 e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 28 1 15 14 28 - pin so wide body 1. dimensions d max. & s include mold flash or tie bar burrs. 2. dimension b does not include dambar protrusion/intrusion. 3. dimensions d & e include mold mismatch and determined at the mold parting line. . 0.25 0.20 0.010 0.008 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm 0.014 0.36 0.112 2.85 0.004 0.093 0.014 0.098 0.016 0.103 0.020 2.36 0.36 0.10 2.49 0.41 2.62 0.51 0.059 0.004 0 10 0.713 0.067 0.733 0.075 1.50 18.11 1.70 18.62 1.91 0.477 0.465 0.453 12.12 11.81 11.51 0 10 0.10 8.53 8.41 8.28 0.336 0.331 0.326 0.71 0.91 1.12 0.028 0.036 0.044 4. controlling dimension: inches. 5. general appearance spec should be based on final visual inspection spec. 1.12 1.27 1.42 0.044 0.050 0.056 1.19 0.047 2 1 a 28 15 14 1 e s e h b seating plane a a y l l e c see detail f d e e 1 1 e detail f a b c d e h e l y a a l e 1 2 e s q q
w27E512 publication release date: june 2000 - 15 - revision a9 package dimensions, continued 28 - pin stand ard type one tsop a a a 2 1 l l 1 y c e h d d b e controlling dimension: millimeters min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 11.70 7.90 13.20 0.50 0.00 0 0.20 0.27 0.15 0.21 11.80 11.90 8.00 8.10 13.40 13.60 0.55 0.60 0.70 0.25 0.10 3 5 0.047 0.006 0.041 0.040 0.035 0.007 0.008 0.011 0.004 0.006 0.008 0.461 0.465 0.469 0.311 0.315 0.319 0.520 0.528 0.536 0.022 0.020 0.024 0.028 0.010 0.000 0.004 0 3 5 0.002 a a b c d e e l l y 1 1 2 a h d q dimension in mm q 1 32 - pin plcc l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.49 0 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: inches. 4. general appearance spec. should be based on final visual inspection spec. 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 q q
w27 e512 - 16 - version history version date page description a6 apr. 1997 1, 13, 14 add sop package a7 feb. 1998 1, 2, 3, 5, 6, 13 add 45/55 ns bining a8 nov. 1999 2, 3 modify functi on description ( v il and v ih ): v il ? low. v ih ? high. 4 modify a9 and v pp erase voltage (v id and v pp ): from 13.75v (min) to 13.25v (min) 6 modify v cc description a9 jun. 2000 5 modify input pulse levels in ac test conditions headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5796096 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min - sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 note: all data and specifications are subject to change withou t notice. headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5796096 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min - sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 note: all data and specifications are subject to change withou t notice.

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