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hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 1-1/1 no. dpbcl0001404-05 dec. 18, 2007 liquid crystal display module technical dat a TX06D103VM0AAA target specification 13-1/4 - 4/4 pa cking specifica tions 14-1/1 12-1/1 11-1/4 - 4/4 10-1/3 - 3/3 9-1/1 8-1/5 - 9/9 7-1/1 6-1/2 - 2/2 5-1/1 4-1/1 3-1/1 2-1/1 1-1/1 3284ps 2614-tx05d48vm1asa-1 3284ps 2613-tx05d48vm1asa-1 3284ps 2612-tx05d48vm1asa-1 3284ps 2611-tx05d48vm1asa-1 3284ps 2610-tx05d48vm1asa-1 dpbcl0001404-05 dpbcl0001404-05 dpbcl0001404-05 dpbcl0001404-05 dpbcl0001404-05 dpbcl0001404-05 dpbcl0001404-05 dpbcl0001404-05 dpbcl0001404-05 preca utions for use designa tion of lot ma rk preca utions in design visual inspection dimensiona l outline interfa ce block diagram optica l cha ra cteristics electrica l cha ra cteristics a bsolute ma ximum ra tings genera l da ta record of rev isions cov er page sheet no. item 14 13 12 11 10 9 8 7 6 5 4 3 2 1 no. contents (notes) 1. this document may, w holly or partially, be subject to change w ithout notice. 2. all rights are reserved ; no one is permitted to reproduce or duplicate, in any form, the w hole or part of this document w ithout hitachi's permission. 3. no one is permitted to explain contents of this document to third parties w ithout hitachi's permission. 4. hitachi w ill not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document, any previous reports or oral discussions. 5. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi's products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 6. no license is granted by implication or otherw ise under any patents or other rights of any third party or hitachi, ltd. 7 . l ife support a ppl ica tions : hitachi's products are not authorized for use in life support systems. tentative www..net
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 2-1/1 record of revisions summary sheet no. date
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 3-1/1 3. general data (1) product name (2) module dimensions (3) active area dimensions ( 4 ) pix e l pit c h (5) resolution (6) color pixel arrangement (7) display mode (8) number of colors (9) view ing direction (10) backlight (11) weight (12) pow er supply voltage (13) interface i/o pow er supply (14) lcd driver ic (15) interface TX06D103VM0AAA 42.62 (w) mm x 60.5(h) mm x 2.45 (t) mm 36.72 (w) mm x 48.96 (h) mm 0.153 (w) mm x 0.153 (h) mm 240 x 3 (r, g, b) (w) x 320 (h) dots rgb vertical stripe transmissive type, normally black mode, ips 65,536 colors (8-bit, 16-bit cpu - i/f) 262,144 colors (9-bit, 18-bit cpu - i/f) - light emitting diode (led) four leds connected in series 12.0g vcc = 2.8 v (typ) 1.75v < i/ov c c < vcc r61505u 8-bit / 9-bit / 16-bit / 18-bit cpu bus (80 cpu series)
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 4-1/1 4 . absol u te maximu m r atin gs 4. 1 electrical absolute maximum ratings of lcd 4. 2 environmental absolute maximum ratings notes (1) ta < 40 c: 85% rh max. ta > 40 c: absolute humidity must be low er than the humidity of 85%rh at 40 c. the polarizer quality is not assured by the above values. (2) background color slightly changes depending on ambient temperature and view ing angle. vss = 0 v notes (1) all voltage values are referred to gnd. (2) i/ovcc < vcc (3) applies to the reset*, rd*, wr*, cs*, rs,vsync*, im0, im3 and db17-0 pins. (4) ta = 25 deg c, per piece of led. (5) relationship betw een ambient temperature and allow able forw ard current the operating current should be decided after considering the ambient maximum temperature of leds. (6) 100 pf, 1.5 kohm, 25 c, 70% rh. static electricity discharge point is the center of lcd's surface. (1), (4) v 5 - vr led reverse voltage kv 2 - - ma 35 - iled v i/ov c c +0.3 -0.3 v in v 4.6 -0.3 i/ov c c v 4.6 -0.3 vcc unit max min symbol (4), (5) (6) (1), (3) (1), (2) (1), (2) note static electricity led forw ard current input voltage pow er supply for interface pow er supply for logic and analog item no condensation note ( 2) comment corrosive gas humidity ambient temperature item 80 c -30 c 70 c -20 c max min max min not acceptable not acceptable note (1) note (1) storage operating ambient temperature ta ( c) 30 20 10 0 0 20 40 60 80 100 40 50 8.5 allowable forward current if ( ma )
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 5-1/1 5. electrical characteristics electrica l cha ra cteristics of lcd ta = 25 c, v ss = 0 v notes (1) applies to the reset*, rd*, wr*, cs*, rs,vsync*, im0, im3 and db17-0 pins. (2) applies to the fmark and db17-0 pins. (3) vcc = i/ovcc = 2.8 v, fflm = 85 hz (4) partial pattern (5) vcc = i/ovcc = 2.8 v, standby mode (6) refer to item 4.1 40 lines: white 280 lines: black 40 lines: white 280 lines: black fflm = 85 hz 8-color mode (2) (1) power supply voltage f or intef ace i/ovcc - 1.75 - vcc - note (6) (5) (4) (3) a ma a 1.0 - -1.0 - ili input/output leak current note ma hz 85 - - fflm frame frequency v power supply voltage f or logic and analog - ma/led v v v 0 0.8 x i/ovcc 0.8 x i/ovcc 1.0 2.5 4.0 0.2 x i/ovcc 0.2 x i/ovcc i/ovcc 2.88 18 3.2 0.1 1.3 2.5 2.8 2.72 standby partial all white "l" lev el "l" lev el "h" lev el "h" lev el - 3.5 - - - - - - - - - - - - i led vled icc vo vi vcc unit max ty p min condition sy mbol led forward current led forward voltage power supply current output voltage f or logic circuits input voltage f or logic circuits item
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 optica l cha ra cteristics of lcd ( ba cklight on) 6. optical characteristics 6-1/2 notes (1) definition of brightness "b" sensor : topcon / bm-5a or equivalent measurement point : center of lcd's active area 500 mm sensor lcd module common conditions for measurement measurement environment ambient temperature sequence pow er supply voltage backlight current : dark room : ta = 25 c : follow item 8.4.2, sequence. : vcc = i/ovcc = 2.8 v : 18 ma (2) display image for measurement : white 80 - 0.38 0.32 0.26 0.37 0.31 0.25 0.17 0.11 0.05 0.20 0.14 0.08 0.65 0.59 0.53 0.40 0.34 0.28 0.39 0.33 0.27 0.69 0.63 0.57 70 40 - - 70 - 160 - - 160 - 400 200 - 250 170 max ty p min (1) (8) (2), (3), (5) (4), (6), (7) (1), (6) (1), (2) - ms % deg - cd/m 2 =0 =0 maximum gradient =0 , =0 ta=25 c =0 , =0 =90 , k> 10 =0 , k> 10 =0 , =0 =0 , =0 color tone (primary color) white blue green red y y y x x x y x tr + tf - 1 + 2 k b response time brightness uniformity view ing angle contrast ratio brightness note unit condition symbol item
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 6-2/2 (8) definition of optical response time black white black display data % t r: rise time 0 10 90 100 t f: fall time optical responce time k = brightness w hen displaying black raster brightness w hen displaying white raster (6) definition of contrast "k" (5) definition of the brightness uniformity (7) definition of view ing angle 1 and 2 = 0 sensor sensor : bm-5a or equivalent 2.0 1 2 1 < 0 < 2 view ing angle (4) definitions of and notes (3) measurement point 120 50 190 160 270 50 (pixel) p1 p2 p3 p4 p5 p6 p7 p9 p8 x y ( = 180 ) y' ( = 0 ) x' z 2 1
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 7-1/1 7. block diagram rs, cs*, wr*, rd*, v sy nc* gn d vcc reset* i/ov c c db17- db0 r61505u tft-lcd 240(h) x rgb x 320(v) r g b im0, im3 g1 g319 s720 s1 g320 g2 led an ca led led led gs=1 sm=1 ss=0 bgr1 fma rk
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 8-1/9 8. interface 8.1 internal pin connection (8 / 9 / 16/18-bit cpu bus corres pondence) suitable connector : hirose fh26-39s-0.3shw(5) line synchronous signal vsy nc* frame head pulse signal fma rk nc (no connection) nc gnd gnd 39 38 37 36 gnd f or led pow er supply for led nc (no connection) pow er supply for logic and analog pow er supply for interface chip select data/command identification write read data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) reset data bus (instruction & display data) data bus (instruction & display data) mpu interface sw itching mpu interface sw itching id(i/ovcc) gnd pow er supply for logic and analog pow er supply for interface gnd 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ca an nc v cc v cc i/ov c c i/ov c c cs* rs wr* rd* db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 reset* im3 im0 id gnd gnd function signal pin no. 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 function signal pin no.
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 8.2 cpu interfa ce mode setting 8-2/9 unused data bus pins are to be set at gnd or i/ovcc. 8.2.2 unused data bus connection 8.2.3 display data input select the interface mode and colors by setting bits of im0 and im3. 8.2.1 cpu interface mode selection g0 g3 b1 b2 b3 b4 g1 g2 g3 g4 b0 b1 b2 b3 b4 b5 g0 g1 g2 g3 g4 g5 g3 g4 b0 b1 b2 b3 b4 b5 g0 g1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - b1 b2 b3 b4 g4 g5 r1 r2 r3 r4 r5 r0 g2 g5 r0 r1 r2 r3 r4 r5 g5 r1 r2 r3 r4 r0 r1 b5 b0 b5 b0 g0 g1 g2 r5 r0 r2 r3 r4 r5 transfer 2 transfer 2 transfer 1 transfer 1 transfer 1 transfer 1 8-bit 9-bit 16-bit 18-bit data bus db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 gnd i/ovcc i/ovcc i/ovcc gnd gnd i/ovcc gnd im3 im0 5 4 65k colors 262k colors 65k colors 262k colors signal pin no. 8-bit 9-bit 16-bit 18-bit 80-system bus interface gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc gnd or i/ovcc db9-0 db8-0 db9,db0 - db17-10 db17-9 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 d b 11 db12 db13 db14 db15 db16 db17 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 db17-10 db8-1 db17-0 8-bit 9-bit 16-bit 18-bit signal pin no. unused data bus pins data bus pins bus interface
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 8-3/9 8.3.1 80-system bus interface timing characteristics <<18 bits / 16 bits>> 8.3 interface timing - - - - 11 0 ns ns tas tas read (rs to cs*, rd*) write (rs to cs*, wr*) set up time - - 132 ns tcycw write read data hold time read data delay time write data hold time write data set up time address hold time write/read rise/fall time read high-level pulse w idth write high-level pulse w idth read low -level pulse w idth write low -level pulse w idth read bus cycle time tdhr tddr th tdsw tah twrr, twrf pwhr pwhw pwl r pwl w tcycr ns ns ns ns ns ns ns ns ns ns ns item - - 142 - - - - - - - 23 - - - - - - - - - - - 6 - 11 27 3 - 263 74 179 48 473 min max ty p unit symbol [normal write mode (hwm = 0), i/ovcc = 1.75 to 2.8 v] vcc = 2.8 v [high-speed write mode (hwm = 1), i/ovcc = 1.75 to 2.8 v] vcc = 2.8 v - - - - 11 0 ns ns tas tas read (rs to cs*, rd*) write (rs to cs*, wr*) set up time - - 79 ns tcycw write read data hold time read data delay time write data hold time write data set up time address hold time write/read rise/fall time read high-level pulse w idth write high-level pulse w idth read low -level pulse w idth write low -level pulse w idth read bus cycle time tdhr tddr th tdsw tah twrr, twrf pwhr pwhw pwl r pwl w tcycr ns ns ns ns ns ns ns ns ns ns ns item - - 142 - - - - - - - 23 - - - - - - - - - - - 6 - 11 27 3 - 263 27 179 42 473 min max ty p unit symbol
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 8-4/9 8.3.2 80-system bus interface timing characteristics <<9 bits / 8 bits>> - - - - 11 0 ns ns tas tas read (rs to cs*, rd*) write (rs to cs*, wr*) set up time - - 74 ns tcycw write read data hold time read data delay time write data hold time write data set up time address hold time write/read rise/fall time read high-level pulse w idth write high-level pulse w idth read low -level pulse w idth write low -level pulse w idth read bus cycle time tdhr tddr th tdsw tah twrr, twrf pwhr pwhw pwl r pwl w tcycr ns ns ns ns ns ns ns ns ns ns ns item - - 142 - - - - - - - 23 - - - - - - - - - - - 6 - 11 27 3 - 263 27 179 32 473 min max ty p unit symbol [normal write mode (hwm=0)/high-speed write mode (hwm=1), i/ovcc=1.75 to 2.8v] vcc = 2.8 v 8.3.3 reset timing characteristics [ i/ovcc=1.75 to 2.8v] vcc = 2.8 v reset rise time reset low -level w idth trres tres us ms item 9 - - - - 2 min max ty p unit symbol
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 reset timing vil reset* vil tres vih trres notes (1) pwlw and pwlr are defined by the overlap period w hen cs* is low and w hen wr* or rd* is low . (2) fix unused db pins to either vcc or gnd level. vih vil vih vil write data voh 1 vol 1 voh 1 vol 1 read data tdhr tddr tdsw thwr tcycw,tcycr twrf twrr vih vil vih vil vih pwlw, pwlr pwhw, pwhr vil vih tas tah vih vil vih vil rs cs* wr* rd* db17-db0 db17-db0 bus timing note( 1) note (2) note (2) 8-5/9
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 8-6/9 8.4 register setting 8.4.1 state transition diagram of operation mode vcc, vci: on display: off fosc: on internal power supply: off vcc ,vci: on display: on 262k/65k-color full screen fosc: on internal power supply: on interval scan: off power supply of f (a) (b) (h) vcc, vci: on display: off fosc: off internal power supply: off (d) deep standby vcc, vci: on display: on 8-color partial 40-line display internal power supply: on interval scan: on (c) partial vcc, vci: on display: off fosc: on internal power supply: on (s) sleep
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 8-7/9 8.4.2 sequence 1 power supply on 2 3 4 5 reset wait 1 ms min 6 7 wait 2 ms 8 data transfer synchronization 9 10 11 1 power supply off 2 3 1 display off r07h 0x0072 2 wait 2 frame 3 r07h 0x0001 4 wait 8 line 5 r07h 0x0000 6 amplifier off r09h 0x0000 7 r10h 0x0080 8 r11h 0x0660 9 r12h 0x0000 10 wait 30 ms 11 r10h 0x0000 1 sleep r10h 0x0002 1 sleep mode cancellation r10h 0x0000 2wait 1 clock min last proporsal last proporsal vcc off last proporsal last proporsal last proporsal vcc on iovcc on vci on reset* = "l" reset* = "h" vci off iovcc off state (a) to (s) state (s) to (a) state (h) to (a) state (a) to (h) state (b) to (a), (c) to (a) rs=0,db=0x0000 rs=0,db=0x0000 rs=0,db=0x0000 rs=0,db=0x0000 last proporsal 1 display off r07h 0x0073 2 wait 2frame min 3 r02h 0x0400 4 r10h 0x17a0 5 horizontal ram start address r50h 0x0000 6 horizontal ram end address r51h 0x00ef 7 vertical ram start address r52h 0x0000 8 vertical ram end address r53h 0x0027 9 isc on r09h 0x0401 10 frame frequency control r90h 0x0015 11 wait 2frame min 12 r20h 0x0000 13 r21h 0x0000 14 write data to gram r22h - 15 240x40 size 16 display r07h 0x107b 17 image refresh r20h 0x0000 18 r21h 0x0000 19 write data to gram r22h - 20 240x40 size last proporsal 1 display off r07h 0x0073 2 wait 2frame min 3 isc off r09h 0x0000 4 power setting r02h 0x0400 5 r10h 0x17b0 7 vertical ram end address r53h 0x013f 8 frame frequency control r90h 0x0015 9 wait 2frame min 10 r20h 0x0000 11 r21h 0x0000 12 write data to gram r22h - 13 240x320 size 14 display r07h 0x0173 15 image refresh r20h 0x0000 16 r21h 0x0000 17 write data to gram r22h - 18 240x320 size display data write display data write display data write display data write state (c) to (b) state (b) to (c)
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 8-8/9 last proporsal last proporsal 1 ra4h 0x0001 1 ra4h 0x0001 2 wait 1ms 2 wait 1ms 3 power sequence control r07h 0x0021 3 power sequence control r07h 0x0021 4 wait 10 ms 4 wait 10 ms 5 r17h 0x0001 5 r17h 0x0001 6 wait 10 ms 6 wait 10 ms 7 r19h 0x0000 7 r19h 0x0000 8 power start (1) r10h 0x17b0 8 power start (1) r10h 0x17b0 9 r11h 0x0016 9 r11h 0x0016 10 r12h 0x019e 0x009e 10 r12h 0x019e 0x009e 11 r13h 0x1600 11 r13h 0x1600 12 r14h 0x8000 12 r14h 0x8000 13 wait 10 ms 13 wait 10 ms 14 power start (2) r12h 0x01be 0x00be 14 power start (2) r12h 0x01be 0x00be 15 wait 120 ms 15 wait 120 ms 16 driver output control r01h 0x0500 16 driver output control r01h 0x0500 17 lcd driving wave control r02h 0x0400 17 lcd driving wave control r02h 0x0400 18 entry mode r03h 0x1230 18 entry mode r03h 0x1230 19 display control (2) r08h 0x0808 19 display control (2) r08h 0x0808 20 isc control r09h 0x0000 20 isc control r09h 0x0401 21 display control (4) r0ah 0x0008 21 display control (4) r0ah 0x0008 22 r0ch 0x0000 22 r0ch 0x0000 23 r0dh 0x0000 23 r0dh 0x0000 24 gamma setting r30h 0x0704 0x0703 24 gamma setting r30h 0x0704 0x0703 25 r31h 0x0003 0x0001 25 r31h 0x0003 0x0001 26 r32h 0x0000 0x0004 26 r32h 0x0000 0x0004 27 r33h 0x0103 0x0102 27 r33h 0x0103 0x0102 28 r34h 0x0000 0x0300 28 r34h 0x0000 0x0300 29 r35h 0x0006 0x0103 29 r35h 0x0006 0x0103 30 r36h 0x001f 0x001f 30 r36h 0x001f 0x001f 31 r37h 0x0704 0x0703 31 r37h 0x0704 0x0703 32 r38h 0x0003 0x0001 32 r38h 0x0003 0x0001 33 r39h 0x0000 0x0004 33 r39h 0x0000 0x0004 34 r3ah 0x0103 0x0102 34 r3ah 0x0103 0x0102 35 r3bh 0x0000 0x0300 35 r3bh 0x0000 0x0300 36 r3ch 0x0006 0x0103 36 r3ch 0x0006 0x0103 37 r3dh 0x001f 0x001f 37 r3dh 0x001f 0x001f 38 horizontal ram start address r50h 0x0000 38 horizontal ram start address r50h 0x0000 39 horizontal ram end address r51h 0x00ef 39 horizontal ram end address r51h 0x00ef 40 vertical ram start address r52h 0x0000 40 vertical ram start address r52h 0x0000 41 vertical ram end address r53h 0x013f 41 vertical ram end address r53h 0x0027 42 r60h 0x2700 42 r60h 0x2700 43 r61h 0x0000 43 r61h 0x0000 44 r6ah 0x0000 44 r6ah 0x0000 45 r80h 0x0000 45 r80h 0x0000 46 r81h 0x0000 46 r81h 0x0000 47 r82h 0x0027 47 r82h 0x0027 48 frame frequency control r90h 0x0015 48 frame frequency control r90h 0x0015 49 r92h 0x0000 49 r92h 0x0000 50 r93h 0x0002 50 r93h 0x0002 51 r20h 0x0000 51 r20h 0x0000 52 r21h 0x0000 52 r21h 0x0000 53 write data to gram r22h - 53 write data to gram r22h - 54 240x320 size 54 240x40 size 55 display on r07h 0x0021 55 display on r07h 0x0021 56 wait 8 line min 56 wait 8 line min 57 r10h 0x17b0 57 r10h 0x17b0 58 r11h 0x0017 58 r11h 0x0017 59 r07h 0x0061 59 r07h 0x0061 60 wait 2 frame min 60 wait 2 frame min 61 r07h 0x0173 61 r07h 0x107b 62 image refresh r20h 0x0000 62 image refresh r20h 0x0000 63 r21h 0x0000 63 r21h 0x0000 64 r22h - 64 r22h - 65 240x320 size 65 240x40 size state (a) to (b) state (a) to (b) display data write display data write display data write display data write
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001404-05 8-9/9 1 deep standby r10h 0x0004 last proporsal 1 dstb mode cancellation (1) index write(data=8'h00) 2 dstb mode cancellation (2) index write(data=8'h00) 3 wait 1ms min 4 dstb mode cancellation (3) index write(data=8'h00) *1 5 dstb mode cancellation (4) index write(data=8'h00) 6 dstb mode cancellation (5) index write(data=8'h00) 7 dstb mode cancellation (6) index write(data=8'hf0) 8 wait 50 ms 1 dstb mode cancellation (1) cs="low" 2 dstb mode cancellation (2) index write(data=8'h00) 3wait1ms 4 dstb mode cancellation (3) cs="low" *2 5 dstb mode cancellation (4) cs="low" 6 dstb mode cancellation (5) cs="low" 7 dstb mode cancellation (6) cs="low" 8 wait 10 ms last proporsal *1 data transfer *2 data transfer state (a) to (d) state (d) to (a) cancel deep standby mode by inputting cs="low" (18-/ 16-/ 9-/ 8-bit interface) cancel deep standby mode by inputting cs="low" and wr="low" (9-/ 8-bit interface)

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