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| motorola semiconductor technical data this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc. 2004 document order number: MC34920 rev 1.0, 01/2004 34920 advance information simplified application diagram + + dc motor dc motor 34920 mcu v vb+ v v2 v v1 dr1a dr2a dr1b dr2b cp1 cp2 dr2pwm sdi dr1pwm sclk v2_fb v1_fb vb+ v1_switch v2_switch reset cs v b v vb+ + gnd ordering information device temperature range (t a ) package MC34920ei/fn/r2 0c to 70c 44 plcc 2.8 ? (typ) quad h-bridge motor driver the 34920 is a multifunctional analog asic. the 34920 integrates two circuits, four h-bridge driv ers, a reset circuit in a single ic, and two dc/dc switching voltage regulators. i nput voltage is 21 v to 42 v dc. each motor of the two driver blocks can be configured as either a dc motor driver with pulse width modulation (pw m)-control or a single bipolar step motor driver. in step motor mode, both drivers are capable of being operated in the quarter step mode. in dc motor mode, both bridges in a dr iver are in parallel, providing 2.4 a of drive current. in step motor mode, eac h bridge in a driver drives one phase. each phase is driven with a bipolar current mode drive. features ? individual thermal limit protection ? user-selectable motors: 2 dc motors (2.4 a/motor), 2 step motors (w1-2 phase control), 1 dc motor and 1 step motor ? 2 buck regulators (switching @ 200 khz) ?v v2 output voltage is programmable to 10 v to 15 v dc (externally set) ? low-voltage detection reset (v v1 and v vb+ ) ? pb-free packaging designated by suffix code ei 2.8 ? (typ) quad h-bridge motor driver ei (pb-free) suffix fn suffix case 777 44-terminal plcc 34920 simplified application diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34920 motorola analog integrated circuit device data 2 figure 1. 34920 simplified internal block diagram dr1a1 dr1b1 dr1sense1 dr1a2 dr1b2 dr1sense2 dr2a1 dr2b1 dr2sense1 dr2a2 dr2b2 dr2sense2 control logic-pwm drive v1 regulator oscillator v2 regulator boost voltage generator vb+ v1_switch v1_fb v2_switch v2_fb cp1 cp2 vb+ serial input port cs sclk sdi reset reset dr1pwm dr2pwm v b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 3 terminal function description terminal terminal name formal name definition 1v b output terminal to v v b terminal to connect to v v b capacitor. 2 cp2 capacitor to cp1 terminal for boost generator switch capacitor. 3 cp1 capacitor to cp2 terminal for boost generator switch capacitor. 4 reset reset output active low reset output. 5v cc v cc supply voltage v cc power input for internal use. the 34920 accepts either 3.3 v 10% or 5.0 v 5% for its logic voltage. 6, 7, 17, 18, 28, 29, 39, 40 gnd substrate ground ground connections for digital ic circuitry. 8 v1_fb v1 regulator feedback input voltage feedback for the v1 regulator. 9 dr1_mode mode select for driver 1 selects operational mode of driver 1; step = 1/dc = 0. 10 v1_switch internal mosfet source for v1 regulator switching output for v1 regulator. 11, 15, 16, 23, 30, 31, 35 vb+ vb+ (bulk) supply voltage high-voltage supply for motors and regulators. 12 dr2a1 driver 2, bridge 1, output a motor driver output. 13 dr2sense1 driver 2, bridge 1, i sense current sense for current mode. 14 dr2b1 driver 2, bridge 1, output b motor driver output. 19 dr1a1 driver 1, bridge 1, output a motor driver output. 20 dr1sense1 driver 1, bridge 1, i sense current sense for current mode. 21 dr1b1 driver 1, bridge 1, output b motor driver output. 22 dr1pwm driver 1 pwm input pwm input for driver 1. used only when dr1_mode terminal = 0. 24 dr2pwm driver 2 pwm input pwm input for driver 2. used only when dr2_mode terminal = 0. 25 dr1b2 driver 1, bridge 2, output b motor driver output. dr2sense1 dr2a1 vb+ v1_switch dr1_mode v1_fb gnd gnd 30 31 32 33 34 35 36 29 dr2b1 vb+ vb+ dr2sense2 dr2a2 vb+ v2_switch dr2_mode v2_fb gnd gnd dr2b2 vb+ vb+ dr2pwm vb+ dr1pwm dr1b1 dr1sense1 dr1a1 gnd gnd dr1b2 dr1sense2 dr1a2 agnd v b cp2 cp1 reset v cc gnd gnd cs sclk sdi 37 38 39 41 42 43 44 1 2 3 40 4 5 6 16 15 14 13 12 11 10 17 9 8 7 27 26 25 24 23 22 21 28 20 19 18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 4 26 dr1sense2 driver 1, bridge 2, i sense current sense for current mode. 27 dr1a2 driver 1, bridge 2, output a motor driver output. 32 dr2b2 driver 2, bridge 2, output b motor driver output. 33 dr2sense2 driver 2, bridge 2, i sense current sense for current mode. 34 dr2a2 driver 2, bridge 2, output a motor driver output. 36 v2_switch internal mosfet source for v2 regulator switching output for v2 regulator. 37 dr2_mode mode select for driver 2 selects operational mode of driver 2. step = 1/ dc = 0. 38 v2_fb v2 regulator feedback input switch output for v2 regulator. 41 sdi serial port data input serial input register serial data input. 42 sclk serial data port clock serial input register clock. 43 cs serial data port chip select serial input register chip select input. active low. 44 agnd analog ground ground connection for analog circuitry. terminal function description (continued) terminal terminal name formal name definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 5 maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit vb+ supply voltage v vb+ 45 v v cc voltage v cc(max) 7.0 v bridge output current i out 1.5 a maximum voltage on reset (note 1) v maxrst v cc - 0.5 v esd voltage human body model (note 2) machine model (note 3) v esd1 v esd2 1000 100 v storage temperature t stg -40 to 175 c operating ambient temperature t a 0 to 70 c operating junction temperature t j 135 c power dissipation (t a = 25 c) (note 4) p d 2.0 w terminal soldering temperature (note 5) t solder 220 c thermal resistance, junction to ambient (note 6) r ja 37 c/w notes 1. reset is an open drain (open collector) output with an internal pull-up resistor. 2. esd1 testing is performed in accordance with the human body model (c zap =100 pf, r zap =1500 ? ). 3. esd2 testing is performed in ac cordance with the machine model (c zap =200 pf, r zap =0 ? ). 4. maximum power dissipation at indicated ambient temperature in free air with no heatsink used. 5. terminal soldering temperature limit is for 10 seconds maxi mum duration. not designed for i mmersion soldering. exceeding thes e limits may cause malfunction or permanent damage to the device. 6. r ja is dependent on customer application and pcb layout. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 6 static electrical characteristics characteristics noted under conditions 21 v v vb+ 42 v, t a = 10 c to 55c, t j max = 135c, v cc = 5.25 v max unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under typical conditions unless otherwise noted. characteristic symbol min typ max unit power input v vb+ supply voltage v vb+ 21?42v v vb+ standby current v vb+ = 42 v, i cc load = 5.0 ma, no serial clock, no motor driver, no load on v v2 i vb+ 1.0 14 55 ma cmos logic level (note 7) input current, high-voltage state i ih ? 0.1 170 a input current, low-voltage state i il -170 -0.1 ? a input low input voltage state v cc + 3.3 v 10% v cc +5.0v 5% v il ? ? ? ? 0.8 1.5 v input high-voltage state v cc + 3.3 v 10% v cc +5.0v 5% v ih 2.1 3.3 ? ? ? ? v v1 and v2 voltage regulators regulator output voltage v out -4.0% nom +4.0% v regulator thermal shutdown junction temperature t j(shutdown) 155 ? 175 o c regulator thermal junction temperature t j(enable) 135 ? 155 o c overcurrent detect level (peak) for i v1_switch i oc_v1 1.5 2.0 2.5 a overcurrent detect level (peak) for i v2_switch i oc_v2 2.5 3.25 4.0 a short circuit detect level (peak) for i v1_switch in soft start and foldback modes i sc_v1 0.75 1.25 1.75 a short circuit detect level (peak) for i v2_switch in soft start and foldback modes i sc_v2 1.75 2.25 2.75 a v1 switching mosfet on resistance full on, typical value @ t j = 25c r ds(on)v1 ? 2.0 ? ? v2 switching mosfet on resistance full on, typical value @ t j = 25c r ds(on)v2 ? 0.75 ? ? regulator feedback input internal reference value of 2.50 v 2% v v1_fb , v v2_fb ? 2.5 ? v turn-off regulator v v1 output/v v2 output = 0 v voff v1_fb , voff v2_fb 3.0 ? ? v notes 7. applicable to all logic level input si gnals. inputs are to be designed to accept 3.3 v logic levels and be +5.0 v tolerant. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 7 static electrical charac teristics (continued) characteristics noted under conditions 21 v v vb+ 42 v, t a = 10 c to 55c, t j max = 135c, v cc = 5.25 v max unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under typical conditions unless otherwise noted. characteristic symbol min typ max unit v1 and v2 voltage regulators (continued) voltage overshoot external v cc load current from 0.01 to 0.500 a, t rise > 100 ns v ovrsht ? 5.0% ? ? load ripple 0.5 a maximum v outripple ? 100 ? mv vboost generator charge pump output voltage i load = 1.0 ma v vb- v vb+ 10 ? 14 v bipolar current regulate d step motor drive system peak step motor current, phase a or b motor not stalled i stepmotor peak ? ? 0.6 a maximum allowable voltage drop across any h-bridge switch i load = 0.6 a (from output to gnd) or i load = 0.6 a (from v vb+ to output) v drop ? ? 1.6 v comparator high threshold voltage curr_i0_phasex=0, curr_i1_phasex=0 v th 450 550 650 mv comparator medium threshold voltage curr_i0_phasex=1, curr_i1_phasex=0 v tm 300 ? 440 mv comparator low threshold voltage curr_i0_phasex=0, curr_i1_phasex=1 v tl 105 ? 255 mv v o off output leakage current for step motor driver outputs v o off = 5.0 v i o off -1.0 0.1 1.0 ma step motor driver thermal shutdown junction temperature t j(shutdown) 155 ? 175 o c step motor driver thermal enable junction temperature t j(enable) 135 ? 155 o c single mosfet typical value @ t j = 25c r ds(on) ? 1.43 ? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 8 static electrical charac teristics (continued) characteristics noted under conditions 21 v v vb+ 42 v, t a = 10 c to 55c, t j max = 135c, v cc = 5.25 v max unless otherwise noted. typical values noted reflect th e approximate parameter mean at t a = 25 c under typical conditions unless otherwise noted. characteristic symbol min typ max unit dc motor drive system maximum allowable voltage drop across any h-bridge switch i load = 0.75 a (from output to gnd) or i load = 0.75 a (from v vb+ to output) (using 2 h-bridges in parallel) v drop ? ? 1.3 v peak dc motor driver current motor not stalled (using 2 h-bridges in parallel) i dcmotor peak current ? ? 1.2 a dc motor overcurrent threshold (note 8) motor stalled (paralleled h-bridges used for dc motor drive) i dcmotor oct 1.6 2.0 2.5 a dc motor driver sustaining current value current allowed to sustain for a minimum of 100 ms (oct delay), current ripple 100 ma (peak-to-peak or less) i dc_sustain 1.6 2.0 2.4 a differential dc motor driver output voltage v vb+ + rising monotonically from 0 v to 42 v (1.0 s < t r < 10 ms) or v vb+ falling monotonically from 42 v to 0 v (1.0 s 34920 motorola analog integrated circuit device data 10 dynamic electrical characteristics characteristics noted under conditions 21 v v vb+ 42 v, t a = 10 c to 55c, t j max = 135c, v cc = 5.25 v max unless otherwise noted. typical values noted reflect th e approximate parameter mean at t a = 25 c under typical conditio ns unless otherwise noted. characteristic symbol min typ max unit serial input port timing serial clock frequency f clk ? 4.0 12 mhz sclk high width t clh 41.667 125 ? ns sclk low width t cll 41.667 125 ? ns delay cs falling to first sclk rising t cs -sclk 83.333 250 ? ns delay last sclk rising edge to cs rising t sclk-cs 83.333 250 ? ns data valid to sclk set-up time t dsu 41.667 125 ? ns data hold time t dhd 41.667 125 ? ns sdi rise time t rd 5.0 ? 10 ns sdi fall time t fd 5.0 ? 10 ns sclk rise/fall time t rfc 5.0 ? 10 ns cs off-time (t dhd + t dsu ) t ncs-off 83.333 250 ? ns v1 and v2 voltage regulators clock frequency overtemperature f op 175 200 225 khz v1 duty cycle v1_dc 35 37.5 40 % v2 duty cycle v2_dc 80 82.5 85 % bipolar current regulate d step motor drive system shoot-through delay t dead 15 200 350 ns off-time t off 20 29 38 s current blanking time t blank 300 ? 750 ns dc motor drive system pwm frequency t a = 25c f pwm ? 20 21 khz shoot-through delay t dead 15 180 350 ns overcurrent off-time t oc_off 10 40 70 s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 11 dynamic electrical characteristics (continued) characteristics noted under conditions 21 v v vb+ 42 v, t a = 10 c to 55c, t j max = 135c, v cc = 5.25 v max unless otherwise noted. typical values noted reflect th e approximate parameter mean at t a = 25 c under typical conditio ns unless otherwise noted. characteristic symbol min typ max unit reset reset delay v v1_fb v v1t+ t delay 15 33 50 ms v cc out-of-tolerance persistence time reset de-asserted, v v1_fb < v v1t - t persist 10 20 30 s reset rise time 10% to 90% (note 9) t r ? 630 750 ns reset fall time 90% to 10% (note 9) t f ? 11 50 ns notes 9. test circuit is 50 pf capacitor from reset to gnd. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 12 table 1. step motor truth table table 2. dc motor drive system truth table dir_ph_a curr_i0_ phasea curr_i1_ phasea iph_a (ma) dir_ph_b curr_i0_ phaseb curr_i1_ phaseb iph_b (ma) 0 0 0550 0 0 0 550 0 1 0367 0 1 0 367 0 0 1183 0 0 1 183 x 1 1off x 1 1 off 1 0 0 -550 1 0 0 -550 1 1 0 -367 1 1 0 -367 1 0 1 -183 1 0 1 -183 drx_dir_dcm drxpwm high-side a low-side a high-side b low-side b 0 0 on off on off 0 1 off on on off 1 0 on off on off 1 1 on off off on f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 13 timing diagrams figure 2. serial connectivity diagram figure 3. reset generation timing diagram (assumes v vb+ > v vb+t+ during entire period) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bi t 9 bit 10 bit 11 bit 12 bit 13 time sdi sdi stays at last value msb lsb sclk tdsu tend data latched on the rising edge of sclk ncs tcs + sclk tcs - sclk bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bi t 9 bit 10 bit 11 bit 12 bit 13 time sdi sdi stays at last value msb lsb sclk tdsu tend data latched on the rising edge of sclk ncs tcs + sclk tcs - sclk bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bi t 9 bit 10 bit 11 bit 12 bit 13 time sdi sdi stays at last value msb lsb sclk sclk sclk sclk tdsu tend data latched on the rising edge of sclk ncs tcs + sclk tcs - sclk cs sdi sclk bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 13* msb lsb *sdi stays at last value t dsu t dhd data latched on rising edge of sclk t cs -sclk t sclk-cs time tpersist delay n reset undefined undefined tdelay 15-50 ms (plus tpersist delay_ tpersist delay vcc short glitch below vtvcc for less than tpersist trip level vtvcc trip level vtvcc 1 v tdelay 15-50ms (plus tpersist delay) assumes vb+ > vtvb+ during the entire period power on ?glitch? response power off tpersist delay n reset undefined undefined undefined tdelay 15-50 ms (plus tpersist delay_ tpersist delay vcc short glitch below vtvcc for less than tpersist trip level vtvcc trip level vtvcc 1 v tdelay 15-50ms (plus tpersist delay) tdelay 15-50ms (plus tpersist delay) assumes vb+ > vtvb+ during the entire period power on ?glitch? response power off power on ?glitch? response power off power on ?glitch? response power off vcc reset 1.0 v short glitch below v v1t for less than t persist trip level v v1t trip level v v1t undefined undefined t delay 15?50 ms (plus t persist ) t persist t delay 15?50 ms (plus t persist ) t persist f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 14 system/application information introduction introduction the 34920 is a multifunctional analog ic that can be used in printer and scanner applications. it integrates two switching voltage regulator circuits, four h-bridge drivers, and a reset circuit in a single ic. all 34920 control lines are compatible with cmos type 3.3 v and 5.0 v logic. switching voltage regulator circuits two switching voltage regulators provide the following voltages from an unregulated input of 21 v to 42 v dc. both are buck-type switching regulators us ing a mosfet (internal to the 34920), current sense resistor (i nternal to the 34920), schottky diode (external to the 34920), external inductor, and filter capacitor. ? v1 voltage regulator ? this regulator is programmable, has a duty cycle of 37%, and provides either 3.3 v (+5%/ -4%) or 5.0 v (+5%/-4%) at a current of 10 ma (minimum) to 500 ma (maximum). ? v2 voltage regulator ? this regulator has a programmable output voltage (by means of an external resistor divider network) in the range of 10 v to 15 v 2% with a vb+ supply voltage range of 21 v to 42 v. the v2 voltage regulator is controlled by an enable bit in the serial register that allows software to turn this regulator on and off. however, the enable bit does not effect the v1 voltage regulator. the enable bit will disable the v2 voltage regulator and disable all motor driver circuits. motor drivers the two motor drivers can be selectable as either a bi- directional dc motor driver, with pwm control and peak currents of 2.4 a, or a bipolar step motor driver, with average current levels of 183 ma and 550 ma per phase, and quarter step mode capability. in step mode, both drivers are capable of being operated in t he quarter step mode. reset generation the 34920 provides an output, reset , that drives an external reset signal to the system microprocessor and/or the system digital logic ic. this signal is an active low logic level signal that is derived by monitoring the level of the vb+ and v1_fb terminals. when reset is asserted, either internally or from an external source, all 34920 motor driver outputs will be in their inactive states, and the serial input port will be loaded with the reset value. functional description input power supply (v vb+ ) the input voltage for the switching regulators and motor drivers. v vb+ is a voltage range of 21 v to 42 v. cmos logic level cmos logic level specifications are described on page 6 of the static electrical characteristics table. 34920 input table 3 , page 15, describes the 34920 input specifications. serial input port the 34920 provides a serial input port for bit depth of 13 bits of input. this port provides an interface between the 34920 and the digital controller ic. this port is write-only. the interface consists of three signal lines: chip select ( cs , active low), serial clock (sclk), and serial data input (sdi). the digital controller initiates a serial transfer by pulling low the chip select line ( cs ). it then generates 13 clock pulses on the sclk terminal while presenting the serial data on the serial data input (sdi). the 34920 presen ts the data on sdi one setup time (t dsu ) before the rising edge of sclk. the data is held constant for the data hold time (t dhd ) beyond the sclk rising edge. the data is shifted into the 34920 on the rising edge of sclk. the least significant bit (lsb) is the first to be shifted out of the 34920 on the rising edge of sclk, followed by the remaining bits to the last of the 13 bits, which is the most significant bit (msb). the cs line is then returned to a high state. the low-to-high transition of cs will load the data into the internal 34920 input register, wher e all the inputs are presented to their appropriate functions in a parallel fashion. note the minimum off-time ( cs signal equal to logic [1]) for the cs signal needs to be at least 1.0 t dsu delay + 1.0 t dhd delay. this will provide the time for the 34920 to clear the serial input data register (transfer the serial data in parallel to internal latches that use the data) and thereby avoid a data overrun condition and loss of data. see the serial input port timing data in the dynamic electrical characteristics table, page 10 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 15 table 3. 34920 input specifications name description v1_fb voltage feedback for the v1 regulator. vcc vcc power input for internal use. the 34920 accepts ei ther 3.3 v 10% or 5.0 v 5% for its logic voltage. v2_fb voltage feedback for the v2 regulator. cs serial input register chip select input. active low. sclk serial input register clock. sdi serial input register serial data input. drxpwm pwm input for the dc motor driver for either driver 1 or driver 2. drx_mode selects mode of each motor driver. step = 1/dc = 0. the following inputs are through the serial input register v2_enable enable bit to turn on and off the v2 regulator and the motor drivers. when low (= logic [0]), the v2 regulator and the motor drivers are turned off and the 34920 is placed in it s lowest possible power state. v1 is not affected by the enable bit. dr1_curr_i1_phasea second of two inputs that control the current level in the step motor phase a winding (driver 1/step mode). dr1_curr-i0_phasea first of two inputs that control the current level in the step motor phase a winding (driver 1/step mode). dr1_dir_ph_a controls the direction of the current flow through phase a of the step motor; i.e., logic [ 1] level causes conventional current flow from dr1a1 to dr1b1 (driver 1/step mode). dr1_curr_i1_phaseb second of two inputs that control the current level in the step motor phase b winding (driver 1/step mode). dr1_curr_i0_phaseb first of two inputs that control the current level in the step motor phase b winding (driver 1/step mode). dr1_dir_ph_b controls the direction of the current flow through phase b of the step motor. a logic [1] level causes conventional current flow from dr1a2 to dr1b2 (driver 1/step mode). dr2_curr_i1_phasea second of two inputs that control the current level in the step motor phase a winding (driver 2/step mode). dr2_curr_i0_phasea one of two inputs that control the current level in the step motor phase a winding (driver 2/step mode). dr2_dir_ph_a controls the direction of the current flow through phase a of the step motor. a logic [1] level causes conventional current flow from dr2a1 to dr2b1 (driver 2/step mode). dr2_curr_i1_phaseb second of two inputs that control the current level in the step motor phase b winding (driver 2/step mode). dr2_curr_i0_phaseb one of two inputs that control the current level in the step motor phase b winding (driver 2/step mode). dr2_dir_ph_b controls the direction of the current flow through phase b of the step motor. a logic [1] level causes conventional current flow from dr2a2 to dr2b2 (driver 2/step mode). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 16 serial input port bit definitions tables 4 through 7 define the bit definitions as they apply to the 13 bits of input that are br ought into the 34920 through the serial input port. these signals are listed in bit order from lsb (first bit to be shifted in) to msb (last bit to be shifted in). table 4. serial input port de finition for step/step mode name bit reset value description v2_enable 1 1 enable bit to turn on and off the v2 regulator and the motor drivers and place the 34920 in the minimum power consumption state. sdr2_curr_i1_phaseb 2 1 second of two inputs that control the current level in the sdr2 step motor phase b winding. sdr2_curr_i0_phaseb 3 1 one of two inputs that control the current level in the sdr2 step motor phase b winding. sdr2_dir_ph_b 4 0 controls the direction of the current flow through phase b of the sdr2 step motor. a logic [1] level causes conventional current flow from ph_b+ (source) to ph_b- (sink). sdr2_curr_i1_phasea 5 1 second of two inputs that control the current level in the sdr2 step motor phase a winding. sdr2_curr_i0_phasea 6 1 one of two inputs that control the current level in the sdr2 step motor phase a winding. sdr2_dir_ph_a 7 0 controls the direction of the current flow through phase a of the sdr2 step motor. a logic [1] level causes conventional current flow from ph_a+ (source) to ph_a- (sink). sdr1_curr_i1_phaseb 8 1 second of two inputs that control the current level in the sdr1 step motor phase b winding. sdr1_curr_i0_phaseb 9 1 one of two inputs that control the current level in the sdr1 step motor phase b winding. sdr1_dir_ph_b 10 0 controls the direction of the current flow through phase b of the sdr1 step motor. a logic [1] level causes conventional current flow from ph_b+ (source) to ph_b- (sink). sdr1_curr_i1_phasea 11 1 second of two inputs that control the current level in the sdr1 step motor phase a winding. sdr1_curr_i0_phasea 12 1 one of two inputs that control the current level in the sdr1 step motor phase a winding. sdr1_dir_ph_a 13 0 controls the direction of the current flow through phase a of the sdr1 step motor. a logic [1] level causes conventional current flow from ph_a+ (source) to ph_a- (sink). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 17 table 5. serial input port definiti on for dc motor/dc motor mode (note 10) name bit reset value description v2_enable 1 1 enable bit to turn on and off the v2 regulator and the motor drivers and place the 34920 in the minimum power consumption state. not used 2 x not used in this mode. not used 3 x not used in this mode. not used 4 x not used in this mode. not used 5 x not used in this mode. not used 6 x not used in this mode. dr2_dir_dcm 7 0 controls the direction of the current flow th rough the dc motor. a logic [1] level causes conventional current flow from dr2a1 (source)/dr2a2 (source) to dr2b1 (sink)/ dr2b2 (sink). not used 8 x not used in this mode. not used 9 x not used in this mode. not used 10 x not used in this mode. not used 11 x not used in this mode. not used 12 x not used in this mode. dr1_dir_dcm 13 0 controls the direction of the current flow th rough the dc motor. a logic [1] level causes conventional current flow from dr1a1 (s ource)/dr1a2 (source) to dr1b1 (sink)/ dr1b2 (sink). notes 10. dr1_mode and dr2_mode terminals = logic [0] for dc motor drive for both drivers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 18 table 6. serial input port definiti on for dr1=step/dr2=dc motor mode name bit reset value description v2_enable 1 1 enable bit to turn on and off the v2 regulator and the motor drivers and place the 34920 in the minimum power consumption state. not used 2 x not used in this mode. not used 3 x not used in this mode. not used 4 x not used in this mode. not used 5 x not used in this mode. not used 6 x not used in this mode. dr2_dir_dcm 7 0 controls the direction of the current flow th rough the dc motor. a logic [1] level causes conventional current flow from dr2a1 (source)/dr2a2 (source) to dr2b1 (sink)/ dr2b2 (sink). sdr1_curr_i1_phaseb 8 1 second of two inputs that control the current level in the sdr1dr1 step motor phase b winding. sdr1_curr_i0_phaseb 9 1 one of two inputs that control the current level in the sdr1 step motor phase b winding. sdr1_dir_ph_b 10 1 controls the direction of the current flow through phase b of the sdr1 step motor. a logic [1] level causes conventional current flow from ph_b+ (source) to ph_b- (sink). sdr1_curr_i1_phasea 11 0 second of two inputs that control the current level in the sdr1 step motor phase a winding. sdr1_curr_i0_phase 12 1 one of two inputs that control the current level in the sdr1 step motor phase a winding. sdr1_dir_ph_a 13 1 controls the direction of the current flow through phase a of the sdr1 step motor. a logic [1] level causes conventional current flow from ph_a+ (source) to ph_a- (sink). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 19 table 7. serial input port definiti on for dr1=dc motor/dr2 =step mode name bit reset value description v2_enable 1 1 enable bit to turn on and off the v2 regulator and the motor drivers and place the 34920 in the minimum power consumption state. sdr2_curr_i1_phaseb 2 1 second of two inputs that control the current level in the sdr2 step motor phase b winding. sdr2_curr_i0_phaseb 3 1 one of two inputs that control the current level in the sdr2 step motor phase b winding. sdr2_dir_ph_b 4 0 controls the direction of the current flow through phase b of the sdr2 step motor. a logic [1] level causes convent ional current flow from ph_b+ (source) to ph_b+ (sink). sdr2_curr_i1_phasea 5 1 second of two inputs that control the current level in the sdr2 step motor phase a winding. sdr2_curr_i0_phasea 6 1 one of two inputs that control the current level in the sdr2 step motor phase a winding. sdr2_dir_ph_a 7 0 controls the direction of the current flow through phase a of the sdr2 step motor. a logic [1] level causes conventional current fl ow from ph_a+ (source) to ph_a- (sink). not used 8 x not used in this mode. not used 9 x not used in this mode. not used 10 x not used in this mode. not used 11 x not used in this mode. not used 12 x not used in this mode. dr1_dir_dcm 13 0 controls the direction of the current flow through the dc motor. a logic [1] level causes conventional current flow from dr1a1 (s ource)/dr1a2 (source) to dr1b1 (sink)/ dr1b2 (sink). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 20 voltage regulators the 34920 contains two switching voltage regulators (see figure 4 ). both are buck-type voltage regulators using an internal switching mosfet. the v1 regulator provides either 3.3 v or 5.0 v at +5%/-4% tolerance. the v2 regulator?s output voltage, v v2 , is programmable through the use of an external resistor divider network. th e voltage tolerance on the v v2 output is 2% of the nominal voltage set point. the switching frequency of the v1 and v2 regulators is approximately 200 khz. the v1 and v2 regulators are designed with a dual-mode current limit circuit. the current limit threshold is lowered during the power-on period to allow for a softer start-up, thereby reducing electrical stress in the external components. v vb+ , the input voltage for the switching voltage regulators, ranges from 21 v to 42 v. to minimize the ripple current on v vb+ , the v1 regulator and the v2 r egulator switch out of phase. a boost voltage generator (v b generator), which acts as a single-stage charge pump, provid es gate drive voltage for the switching regulators. it uses an external capacitor to store the charge. output voltages v v1 and v v2 are set externally with a resistor (1% tolerance) divider network. input voltages at v1_fb and v2_fb should be chosen to provide a feedback voltage, for the required output regulated voltage, to equal the internal regulator reference voltages of 2.5 v 2%. figure 4. voltage regulator functions v1 regulator v2 regulator enable oscillator v b generator v vb+ (21 v to 42 v) cp2 cp1 v b 10 nf 50 v 22 f 25v v v2 34920 v2_fb v2_switch v v1 v1_fb v1_switch vb+ oscillator v vb+ (21 v to 42 v) vb+ f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 21 voltage regulator output requirements table 8 provides a listing of the output voltages and currents. both switchmode converters operate at approximately 200 khz 25 khz. the v1 and v2 regulators provide individual internal over- temperature sensing for protecti on. during an overtemperature event, when the device t j is at or above t j(shutdown) , the internal thermal protection circui t disables the drive outputs by driving all outputs to the zero current state until the device temperatures have dropped below the lower thermal threshold temperature t j(enable) , at which time the driver is re-enabled. the v1 and v2 voltage regulators may be shut down by applying a voltage in the range of 3.0 v to 6.0 v to the respective v1_fb and v2_fb terminals. this will result in the regulator output voltages to be equal to 0 v. overcurrent protection output voltages v v1 and v v2 are short circuit protected. the outputs respond to an overcurr ent situation by limiting the internal switching duty cycle. this can be reset by removing the main supply to the chip or when the short circuit condition is removed. refer to the respective i oc and i sc values for v1 and v2 voltage regulators on page 6 of the static electrical characteristics table. power-saving mode of operation the v2 voltage regulator can be disabled via the serial interface by setting the v2_enabl e bit (bit 1?lsb) to a value of 0. this provides a reduction in the bias current provided by the v1 supply. v1 voltage regulator implementation of the v1 swit ching voltage regulator is accomplished through the use of an internal switch mosfet, internal mosfet current sens e resistor, external schottky diode, external inductor, and filter capacitor. the frequency of operation of this regulator is controlled by the internal clock, which is 200 khz 25 khz. the duty cycle (on-time) for this internal regulator clock is a fixed 37.5%. this regulator switches out of phase from the v2 regulator to minimize ripple current on vb+. the line regulation range is 21 v < v vb+ < 42 v. the load side regulation is specified on page 6 of the static electrical characteristics table. this converter is designed so that the current limit threshold is lowered during the power-on period to allow for a ?softer? start-up, thereby reducing electr ical stress in the external components. this limiting is required for their safe operation. the voltage is set externally with a resistor (1% tolerance) divider network. the v1_fb input voltage should be chosen, using external voltage divider resistors, so as to provide a regulator feedback voltage, fo r the required output regulated voltage, to equal the internal regulator reference voltage of 2.50 v 2%. the v1 regulator is ideal for providing either 3.3 v or 5.0 v with a precision of +5%/-4%. output current sensing is implemented by sensing the voltage across an internal sense resistor connected between vb+ and the drain of the internal mosfet. current is measured on a cycle-by-cycle bas is. the purpose of this current sense is to prevent damage to the 34920 and its associated external components. v2 voltage regulator the v2 switching voltage regulat or is implemented as a buck regulator with an internal swit ch mosfet, internal mosfet current sense resistor, extern al schottky diode, external inductor, and filter capacitor. the frequency of operation of this regulator is controlled by the internal clock, which is 200 khz 25 khz. this regulator switches out of phase from the v1 regulator to minimize ripple current on vb+. this converter is designed so that the current limit threshold is lowered during the power-on period to allow for a ?softer? start-up, thereby reducing electr ical stress in the external components. this limiting is required for their safe operation. the output voltage is variable with 2% precision, with a v vb+ supply voltage range of 21 v to 42 v. the exact voltage will be set externally with a resistor (1% tolerance) divider network. the v2_fb input voltage should be chosen, using external voltage divider resistors, so as to provide a regulator table 8. voltage regulator output requirements voltage name minimum voltage maximum voltage load range v v1 -4.0% of nominal +4.0% of nominal 10 ma min, 500 ma max dc v v2 (note 11) -2.0% of nominal +2.0% of nominal 10 ma min, 1.3 a max dc (note 12) notes 11. this voltage is programmable within a range of 10 v to 15 v via external resistors. the voltage tolerance around any set point is 2% of the nominal. 12. maximum peak duration is 400 ms. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 22 feedback voltage, for the required output regulated voltage, to equal the internal regulator reference voltages of 2.50 v 2%. output current sensing is implemented by sensing the voltage across an internal sense resistor connected between vb+ and the drain of the internal mosfet. current is measured on a cycle-by-cycle basi s. the purpose of this current sense is to prevent any damage to the 34920 and its associated external components. note there is a v2_enable bit in the serial communication input register (bit 1). when this bit is set to logic [1], the v2 voltage regulator is enabled. when this bit = logic [0], the v2 voltage regulator is disabled. refer to tables 3 through 7 , pp. 15?19, for a description of this bit. the v2_enable bit will also disable the motor drivers. v b generator the boost voltage generator circuit is a charge pump circuit using two external capacitors to provide the necessary voltage to drive internal 34920 loads. this circuit is driven at a frequency of 200 khz 25 khz. the v b generator is utilized exclusively by the 34920. there is no provision for external loading. also, there is no disable feature for the v b generator. motor drive systems the 34920 provides two motor drivers. both drivers are mode selectable to be either a multi-current level bi-directional driver for bipolar step motors or a bi-directional dc motor driver with pwm control. the dr1_mode (mode1) and dr2_mode (mode2) terminals select whether the appropriate motor driver will drive a step motor (terminal = 1) or dc motor (terminal = 0). figures 5 and 6 depict the two motor configurations. figure 5. simplified step application di agram showing 1 of 2 step drive circuits dr1_mode vb+ phase a h-bridge phase b h-bridge dr1_dir_dcm sdr1_curr_i0 phasea sdr1_curr_i1 phasea sdr1_dir_ph a dr1a1 dr1sense1 dr1a2 dr1b2 sdr1_dir_ph_b sdr1_curr_i1_phaseb sdr1_curr_i0_phaseb dr1b1 dr1sense2 dr1pwm step motor 34920 dr1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 23 figure 6. simplified dc application diag ram showing 1 of 2 motor drive circuits bipolar current regulated step motor drive system the drive circuitry is powered by the v vb+ supply voltage. for example, with external cu rrent sense resistors of 0.910 ? 1%, the drive circuitry provides drive for a bipolar step motor at current levels of approximately 183 ma, 367 ma, and 550 ma. current mode operation supports quarter stepping. this drive enters the fast cu rrent decay mode when both the curr_i0_phasex and curr_i1_phasex inputs are set to the logic [1] level. in fast current decay mode, any residual motor winding current is forced into the v vb+ supply rail when going to a zero current state from a non-zero current level. this forces the motor winding current toward zero as quickly as possible. for each of the two h-bridge drivers, controlled crossover delay, a blanking period, and internal overtemperature sensing are provided. the crossover delay is controlled to provide sufficient time for cross-conduc tion suppression. at no time will both the upper and lower output device on the same side of the h-bridge be allowed to conduct simultaneously. also, following a turn-on event a blanking period is included to prevent false turn-offs owing to the initial turn-on current spike, which results from motor circuit capacitance. this drive has internal overtemperature sensing for protection. during an overtemperature event, when the device t j is at or above t j(shutdown) , the internal thermal protection circuit disables the drive outputs by driving all outputs to the zero current state until the device temperatures have dropped below the lower thermal threshold temperature t j(enable) , at which time the driver is re-enabled. note during power-on the step motor driver circuit inhibits its outputs when v vb+ is at 4.0 v or greater until reset is released. likewise, during power-down the step motor driver circuit inhibits its outputs from the point when reset goes low until v vb+ has dropped below 4.0 v. dc motor drive system this drive circuitry provides bi-directional drive to a dc motor via two inputs, dcm_pwm (an external terminal, cmos- compatible input) and drx_dir_dcm (a bit in the serial input port; refer to tables 5 through 7 , pp. 17?19). this drive is powered from vb+. the dc motor c ontrol circuitry uses voltage mode control. to drive a dc motor the 34920 outputs dr2a1 and dr2a2 must be connected together externally, then connected to the dc motor ?+? lead. likewise, the 34920 outputs dr2b1 and dr2b2 must be connected togeth er externally, then connected to the dc motor ?-? lead (see figure 6 ). this drive provides internal overtemperature sensing for protection. during an overtemperature event, when the device t j is at or above t j(shutdown) , the internal thermal protection dr2_mode vb+ phase a h-bridge phase b h-bridge dr2_dir_dcm sdr2_curr_i0 phasea sdr2_curr_i1 phasea sdr2_dir_ph a dr2a1 dr2a2 dr2b2 sdr2_dir_ph_b sdr2_curr_i1_phaseb sdr2_curr_i0_phaseb dr2b1 dr2pwm dc motor 34920 + - dr2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 24 circuit disables the drive outputs by driving both outputs to the high state until the device te mperatures have dropped below the lower thermal threshold temperature t j(enable) , at which time the drive is re-enabled. the crossover delay must be controlled to provide sufficient time for cross-condition suppres sion. at no time can both the upper and lower output devices on the same side of the h-bridge be allowed to conduct simultaneously. also, following a turn-on event a blanking period is included to prevent false turn-offs owing to the initial turn-on current spike, which results from motor circuit capacitance. note during power-on the dc motor driver circuit inhibits its outputs when v vb+ is at 4.0 v or greater until reset is released. likewise, during power-down of the machine the dc motor driver circuit inhibits its outputs from the point when reset goes low until v vb+ has dropped below 4.0 v. reset functionality the 34920 provides an output, reset , that drives an external reset signal to the system microprocessor and/or the system digital logic ic. this signal is an active low logic level signal that is derived by monitoring the level of the v cc terminal. this output is the equivalent of an open drain- (or open collector-) type output, wi th an internal 2.5 k ? pull-up to v cc . this output terminal can be driv en by other external sources and therefore the state of reset must be monitored by the 34920. note when reset is asserted either internally or from an external source, all 34920 motor drive outputs will be in their inactive states, and the serial input port will be loaded with the ?reset value? (refer to tables 4 through 7 ). the v2 voltage regulator will be enabled. during power-up this output asserts a logic low level, and it monitors the v1 regulator output voltage and detects the point that it reaches v v1t+ . the output will then remain low for a delay of 15 ms to 50 ms before releasing to a high state. a second case is if v v1_fb is at or above v v1t+ for a period longer than the delay period of t delay and v vb+ is still less than v vb+t - . in this situation reset will remain low until v vb+ is greater than v vb+t- , at which point reset will be released immediately and there will be no delay period. if v vb+ passes through v vb+t+ during the t delay period, reset will remain low until the end of the t delay period, which started at the time v v1_fb passed through the v v1t+ level. during power-down this output immediately asserts a logic low at the point when v v1_fb drops down to the trip point of v v1t - . also, if v vb+ drops below v vb+t - and v v1_fb is still at or above v v1t - , reset will be pulled low. reset behavior the following conditions describe the behavior of the reset circuit. a note on terminology assertion of reset is defined as the reset terminal outputting a logic low voltage, and de- assertion is when the terminal is pulled up to the v cc voltage. on the power-up condition, reset behaves as follows: ?if 1.0v < v v1_fb < v v1t+ or v vb+ < v vb+t+ , reset will be asserted. important if v v1_fb < 1.0 v, reset is undefined. ?if reset is asserted owing to v v1_fb < v v1t - , then when v v1_fb rises monotonically from below v v1t - to above v v1t+ , reset will de-assert after a duration of t delay . ?if reset is asserted owing to v vb+ < v vb+t+ and v v1_fb v v1t+ , then when v vb+ rises to the v vb+t+ level reset will de-assert with no delay. the only case where a delay would be seen is if the time period from where v v1_fb rises to the v v1t+ level to the point where v vb+ rises to the v vb+t+ level is less than the t delay period. then the delay in de-asserting reset would be the remaining t delay time, thereby maintaining the full t delay period, between the time when v v1_fb reaches v v1t+ and the de-assertion of reset , that is required for a reliable system reset. on the power-down condition, reset behaves as follows: ?if reset is not asserted, and the v v1_fb voltage monotonically decreases to a value below the negative- going threshold of v v1t - and remains below v v1t - for longer than t persist (10 s to 30 s ), reset will be asserted. reset will remain asserted while 1.0 v < v v1_fb < v v1t+ . if v v1_fb falls below 1.0 v, the reset signal is undefined. ? reset will also be asserted when v vb+ decreases below the v vb+t+ level. this will occur even if the v v1_fb level is still above v v1t - . on the v v1_fb glitch condition, reset behaves as follows: ? if the v v1_fb supply falls below v v1t - and remains there for less than t persist (10 s to 30 s), reset will not be asserted. however, if the condition lasts longer than t persist , reset will be asserted for a duration of t delay . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 25 environmental specifications ambient temperature and relative humidity table 9 lists the temperature and relative humidity for operating and storage conditions for the 34920. esd immunity refer to the maximu m ratings table, page 5 . overtemperature protection the 34920 implements overte mperature detection and shutdown functions. the overtem perature circuitry monitors the device?s internal temperature and activates thermal shutdown circuitry when the temperature exceeds t j(shutdown) (155c minimum, 175c maximum). the th ermal shutdown condition is maintained until the die temperature falls below t j(enable) (135c minimum, 155c maximum). each voltage regulator and motor driver circuit has its own individual shutdown circuit. applications logic voltage (v cc ) and reset interoperability the 3.3 v or 5.0 v v v1 output voltage should feed back to the v cc input terminal directly (see figure 7 ) to ensure that the 34920 can be properly reset during a power-down situation. if this typology is not the one impl emented, the user needs to be aware that the v cc terminal is not monitored for undervoltage. only the v1_fb and vb+ terminals are monitored for undervoltage. thus, it is possible for v cc to be under voltage without the 34920 issuing a reset. figure 7. voltage regulator functions table 9. ambient temperature and humidity condition temperature (c) % relative humidity operating 0 to 70 8.0 to 80 storage -40 to 150 5.0 to 80 v1 regulator v2 regulator enable oscillator v b generator v vb+ (21 v to 42 v) cp2 cp1 v b 10 nf 50 v 22 f 25v v v2 34920 v2_fb v2_switch v v1 v1_fb v1_switch vb+ oscillator v vb+ (21 v to 42 v) v cc vb+ f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34920 motorola analog integrated circuit device data 26 package dimensions notes: 1. datums -l-, -m-, and -n- are determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.25) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). -n- -l- -m- d y d k v w 1 44 brk b z u x view d-d s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t g1 s l-m s 0.010 (0.25) n s t k1 f h s l-m m 0.007(0.180) n s t z g g1 r a e j view s c s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t 0.004 (0.10) -t- seating plane view s dim min max min max millimeters inches a 0.685 0.695 17.40 17.65 b 0.685 0.695 17.40 17.65 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.650 0.656 16.51 16.66 u 0.650 0.656 16.51 16.66 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.610 0.630 15.50 16.00 k1 0.040 --- 1.02 --- s l-m s 0.010 (0.25) n s t s l-m m 0.007(0.180) n s t ei (pb-free) suffix fn suffix 44-terminal plcc plastic package case 777-02 issue c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 34920 27 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution: p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information cent er, 3-20-1 minami-azabu. minato-ku, tokyo 106-8573 japan. 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre , 2 dai king street, tai po industrial estate, tao po, n.t., hong kong. 852-26668334 technical information center: 1-800-521-6274 MC34920 motorola reserves the right to make changes without further noti ce to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limit ation consequential or incidental damages. ?typical? parameters can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not c onvey any license under its patent rights nor the rights of oth ers. motorola products are not designed, intended, or authorized for use as components in system s intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other appl ication in which the failur e of the motorola product could create a situation where persona l injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and h old motorola and its officers, employees, subsidiaries, affiliate s, and distributors harmless against all cl aims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal in jury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc . motorola, inc. is an equal opportunity/affirmative action employer. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2004 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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