View YMU769_857761.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary preliminary YMU769 ma-5s mobile audio 5 type s YMU769 catalog catalog no : 4mu769a1 2003.10 ? outline YMU769 has a virtual speaker image function, so that it is the most suitable lsi as a sound source output device which is used in mobile phones for high functional game sounds or high quality ringing melodies, and so on. synthesizer section in YMU769 adopts ?stereophonic hybrid synthesizer system? that is given advantages of both fm synthesizers and wave table synthesizers, makes it possible to generate up to 32 fm voices and 32 wave table voices simultaneously. since fm synthesizer is able to provide countless voices by specifying parameters with only several tens of bytes, memory capacity and communication band can be saved, and thus, the device exhibits the features in operating environment of mobile phones such as allowing distribution of arbitrary melodies with voices. on the other hand, wave table synthesizer can pronounce the voice stored in rom, and in addition it can handle arbitrary adpcm/pcm voices by sequencer. furthermore, the stream playback function, and the time-variant low pass filter function by al (analog lite) synthesizer are equipped. YMU769 has two-channel virtual speaker image functions based on dvx technology, so that natural stereo sounds can be realized even in an environment such as two adjacent speakers on a small body like mobile phones. integrated stereo speaker amplifiers make external components unn ecessary and consequently it saves space. in addition, YMU769 has a built-in circuit to control an led or a vibrator synchronously to music, and has a power down mode for saving supply current to a minimum. ? features ? simultaneous generation up to 64 tones by stereophonic hybrid synthesizer. ? equipped with time-variant low pass filter function by al (analog lite) synthesizer. ? stream replay with adpcm / pcm is possible. ? has built-in default voices for fm and wave table synthesizers in the rom, and the voices can be downloaded to sram. ? has built-in sd (stereo dipole) function by dvx technology. ? equipped with speaker amplifier and equalizer circuit. ? equipped with a stereophonic output pin for headphone. ? equipped with vibration control circuit, and led lighting control circuit. ? has built-in pll and inputting of master clock up to 20 mhz is possible and supports tcxo (temperature compensated crystal oscillator). ? contains a 16-bit stereophonic d/a converter. ? equipped with general-purpose i/o port (three parties) ? has a function upwardly compatible to ma-5 ? has power down mode. ? power supply for internal core 2.65v 3.30v ? power supply for cpu i/o 1.65v vdd ? power supply for speaker amplifier vdd 4.50v ? 48-pin qfn plastic package yamaha corporation the contents of this booklet are target specifications and they might be changed without notice. please confirm the finalized specifications again before the use of this lsi. ( datasheet : )
YMU769 2 preliminary ? pin configuration <48 pins qfn top view>
YMU769 preliminary 3 ? pin functions no. pin name i/o power supply function 1 /rd i iovdd cpu interface read-enable 2 clki ish vdd pin of input clock (1.5 mhz ~ 20 mhz *correspondence to tcxo 3 /rst ish iovdd hardware rest input 4 testi i iovdd test input (make sure, connecting with vss) 5 pllc a vdd connection of capacitor for built-in pll connect a series connection of 1000 pf capacitor and 3.3 k ? resistor between this pin and vss(*). (*)directly connect vss used here and vss of 8 th pin. 6 vdd power supply (2.65 3.30v) connect 0.1 f and 4.7 f capacitors between this pin and vss. 7 vss ground 8 vref a vdd analog reference voltage: connect 0.1 f capacitor between this pin and vss. 9 n.c. no connection (make sure to use without no connection) 10 spout2-l a spvdd-l lch speaker connection pin 2 11 spout1-l a spvdd-l lch speaker connection pin 1 12 n.c. no connection (make sure to use without no connection) 13 spvss-l analog ground for lch speaker amplifier 14 spvdd-l analog power supply for lch speaker amplifier (vdd ~ 4.50v) connect the condenser 0.1 f and 4.7 f into between main pins and spvss-l. 15 eq3-l a vdd lch equalizer pin 3 16 eq2-l a vdd lch equalizer pin 2 17 eq1-l a vdd lch equalizer pin 1 18 hpout-l / mono a vdd headphone output lch (it is possible to be mono output) 19 hpout-r a vdd headphone output rch. 20 eq1-r a vdd rch equalizer pin 1 21 eq2-r a vdd rch equalizer pin 2 22 eq3-r a vdd rch equalizer pin 3 23 spvdd-r analog power supply for rch speaker amplifier. (vdd ~ 4.50 v) connect the capacitor 0.1 f and 4.7 f into between main pins and spvss-r. 24 spvss-r analog ground for rch speaker amplifier. 25 n.c. no connection (make sure to use without no connection) 26 spout1-r a spvdd-r rch speaker connection pin 1 27 spout2-r a spvdd-r rch speaker connection pin 2 28 vdd power supply (2.65 ~ 3.30v) connecting the condenser 0.1 f and 4.7 f into between main pins and spvss-r. 29 iovdd power supply for pins (1.65 ~ vdd) 30 mtr o iovdd outside vibrator control pin (drive capability = 4ma) 31 led o iovdd outside led pin (drive capability = 4ma) 32 pio2 i/o iovdd general-purpose parallel i/o port 2 33 pio1 i/o iovdd general-purpose parallel i/o port 1 34 pio0 i/o iovdd general-purpose parallel i/o port 0 35 /irq o iovdd interruption output (drive capability = 1ma) 36 d7 i/o iovdd cpu interface, data bus 7 37 d6 i/o iovdd cpu interface, data bus 6 38 d5 i/o iovdd cpu interface, data bus 5 39 d4 i/o iovdd cpu interface, data bus 4 40 d3 i/o iovdd cpu interface, data bus 3 41 d2 i/o iovdd cpu interface, data bus 2 42 d1 i/o iovdd cpu interface, data bus 1 43 d0 i/o iovdd cpu interface, data bus 0 44 vss ground 45 iovdd power supply for pin (1.65 ~ vdd) 46 a0 i iovdd cpu interface, address signals 47 /cs i iovdd cpu interface, chip select 48 /wr 1 iovdd cpu interface write-enable a : analog pin ish : schmitt input
YMU769 4 preliminary ? block diagram this section outlines functions of blocks contained in this device and flow of signals. eq1-r eq vol eq vol mono eq1-l eq2-r eq3-r spout1-r spout2-r eq2-l eq3-l spout1-l spout2-l analog power supply dedicated to speaker amp spvss-r spvdd-r hp vol hp vol 16bitdac sp vol vref timing generator hybrid synthesizer pll sequencer intermediate register timer led control vibrator control interface register cpu interface vref vref lch rch lch rch instantaneous write path 64byte fifo 512byte fifo control register & sram / rom sp vol hpout-l /mono hpout-r pio0 pio1 pio2 spvss-l spvdd-l vref vss vdd iovdd testi pllc clki /cs a0 /wr /rd d0 - d7 /irq led mtr instantaneous read path delayed write path dvx arithmetic control
YMU769 preliminary 5 ? cpu interface cpu interface is an 8-bit parallel type. it assumes that a total of 13 pins of 4 control signals (/wr, /rd, /cs, a0 pin), 8 data bus (d0 to d7), and 1 interrupt pin (/irq) are connected to the external cpu. this block controls the writing and reading of data by the input polarity of control signal. ? interface register this register is able to access directly from the external cpu. there are 2 bytes spaces. the latter intermediate register can be accessed through the interface register. ? intermediate register this register is accessed through the interface register. the ?control register? and rom/sram, which describes below, can be accessed through this register. this register is called ?intermediate register? since this exists in the middle of the interface register and the control register. in the intermediate register, there are some registers to control various functions. ? control register, rom/sram the control register and rom/sram are accessed from ?instantaneous write register?, ?delayed write register?, and ?instantaneous read register? in the intermediate register. in the control register, there is a register to control the following synthesizer mainly. the voice parameter for fm (gm 128 voices + drum 40 voices) and wave data for wt are stored in rom. sram is used at the download of arbitrary fm voice parameter and wave data for wt. moreover, it is used as storing buffer at the stream playback of pcm/adpcm. ? fifo this is an abbreviation of ?first in first out? mean s the memory which data is read in order of written. there are 2 paths to write into fifo in the intermediate register. the ?instantaneous write path? is for accessing the control register and rom/sram immediately, also ?delayed write path? is for accessing the control register after managing time through the sequencer. fifo size of instantaneous path is 64-byte, and its size of delayed path is 512-byte. ? sequencer this is for interpreting the contents of data which is written into the ?delayed write path?. generally, ?music data? is written into the delayed write path. it interprets the contents of music data and controls the synthesizer after sequencer, and then plays the music. ? hybrid synthesizer this device contains a built-in polyphonic synthesizer that adopts a stereophonic hybrid system that generates up to 64 tones. fm synthesizer, wt (wave table) synthesizer, stream playback, and al (analog lite) synthesizer are available. ? dvx arithmetic control sd (stereo dipole) function that is based on dvx techno logy makes it possible to create natural stereo sound even in using adjacent two speakers.
YMU769 6 preliminary ? i/o port section there are three i/o ports. it is possible to read and write to / from the intermediate register. ? led, vibrator control it is possible to synchronize an led and vibrator with a play, and to control. a synchronous control to a play is also possible. ? clock generating block this device supports a clock input ranging from 1.5 mhz to 20 mhz. (stop = 0 hz is possible at power down.) it is a block to generate a clock which is needed inside of lsi in the pll. ? dac it converts digital signals from a synthesizer and a digital audio section into analog signals. the length of a data is 16bits. ? headphone output . this is an amplifier of stereophonic output for headphone. the monaural output is also possible. ? eq amplifier the change of filter characteristic and gain is possible by adjusting the resistors and external parts. ? speaker amplifier the two speakers amplifier, which has a maximum output power of 580 mw at spvdd_l/_r=3.6v, is integrated in this device. there is a volume to ad just output level in the first stage of amplifier.
YMU769 preliminary 7 ? electrical characteristics z absolute maximum rating item symbol min. max. unit spvdd-l pin, power supply voltage (speaker amplifier section) spvdd-l -0.3 6.0 v spvdd-r pin, power supply voltage (speaker amplifier section) spvdd-r -0.3 6.0 v vdd pin, power supply voltage vdd -0.3 4.2 v iovdd pin, power supply voltage iovdd -0.3 4.2 v spout1-l/-r, spout2-l/-r pin, applied voltage v insp -0.3 spvdd+0.3 v analog input voltage v ina -0.3 vdd+0.3 v digital input voltage 1 (*1) v ind1 -0.3 iovdd+0.3 v digital input voltage 2 (*2) v ind2 -0.3 vdd+0.3 v permissible loss (*3) pd 2487 mw storage temperature t stg -50 125 c vss = spvss = 0v (*1) target pin: d0 d7, /cs, a0, /wr, /rd, /rst (*2) target pin: clki (*3) top= 25 c, and glass epoxy pcb (30mm 100mm 1.0mm) is installed. operation with top= 25 c or higher degrees the permissible loss at the rate of 24.9mw per 1 c. z recommended operating conditions item symbol min. typ. max. unit spvdd-l/-r operating voltage (speaker amplifier section) spvdd-l/-r vdd 3.60 4.50 v vdd operating voltage vdd 2.65 3.00 3.30 v iovdd operating voltage iovdd 1.65 1.80 vdd v operating ambient temperature t op -20 25 85 c vss = spvss-l/-r = 0v z power consumption parameter conditions min typ max. unit power consumption of vdd+iovdd normal operation (*1) 39 ma at silent sound generated spvdd-l/-r side (*1) 8 ma at the time of output 400mw / 8ohm load spvdd-l/-r side (*1) 420 ma power down mode ta = +25c vdd+iovdd+spvdd-l/-r (*2) tbd tbd a power down mode ta = +85c vdd+iovdd+spvdd-l/-r (*2) tbd tbd a (*1) : vdd=iovdd=3.00v, spvdd=3.60v, t op =25c (*2) : vdd=iovdd=3.30v, spvdd=4.50v /cs input pin is fixed to v ih =iovdd, the other input pins are v il =vss and v ih =(io)vdd.
YMU769 8 preliminary z dc characteristics parameter symbol condition min. typ. max. unit input voltage ?h? level 1 v ih (*1) 0.65 iovdd v input voltage ?l? level 1 v il (*1) 0.35 iovdd v input voltage ?h? level 2 v ih (*2) 0.75 iovdd v input voltage ?l? level 2 v il (*2) 0.25 iovdd v input voltage ?h? level 3 v ih (*3) 0.70 vdd v input voltage ?l? level 3 v il (*3) 0.30 vdd v output voltage ?h? level v oh (*4) i oh = (*5) 0.80 iovdd v output voltage ?l? level v ol (*4) i ol = (*5) 0.20 iovdd v schmitt width 1 vsh1 /rst pin 0.10iovdd v schmitt width 2 vsh2 clki pin 0.10vdd v input leakage current il -1 1 a input capacity ci 10 pf t op =-20 85c, vdd=2.65 3.30v, iovdd=1.65 vdd[v], capacitor load=50 pf (*1) target pin: d0 d7, /cs, a0, /wr, /rd (*2) target pin: /rst (*3) target pin: clki (in the case of cmos mode) (*4) target pin: d0 d7, /irq, led, mtr, and pio0 2 (*5) /irq, d0 ~ d7, and pio0 2 are i oh = ?1 ma, i ol = +1 ma led, mtr are i oh = ?4 ma, i ol = +4 ma however, when iovdd is less than 2.65v, d0 d7, /irq, led, and mtr become i oh =-0.2ma and i ol =+0.2ma
YMU769 preliminary 9 z ac characteristics /rst, clki (cmos mode), other input signals item symbol min. typ. max. unit /rst ?l? pulse width t rstw 100 s /rst (indefinite l) setup time t rsts 0 s vdd - iovdd rise time difference t vskw 0 3 ms clki frequency 1 / tfreq 1.5 20 mhz clki rise / fall time trckc / tfckc 30 ns clki high time th 15 ns clki low time tl 15 ns input signals other than clki rise / fall time tr / tf 20 ns t op =-20 85c, vdd=2.65 3.30v, iovdd=1.65 vdd[v], capacitor load=50 pf ? the input to clock can be stopped (=0hz) during reset period and power down state (dp0=1). however, the input level is to be h or l, and input of intermediate level is prohibited. ? when vdd and iovdd are used by respectively different power supply, make sure to rise from vdd first. the reset width is defined as the time from the moment iovdd has risen to 1.65v. /rst has to be settled at ?l? level at the time vdd has risen to 50%.
YMU769 10 preliminary clki (tcxo mode) parameter symbol min. typ. max. unit clki frequency 1 / tfreq 1.5 20 mhz clki rise / fall time trckt , tfckt 250 ns clki amplitude h vmax - vcenter 0.30 0.35 vdd v clki amplitude l vcenter - vmin 0.30 0.35 vdd v wait time to stable operation (*1) twait 2 ms feedback resistance rck 30 45 63 k ? t op =-20 85c, vdd=2.65 3.30v, capacitor load=50pf (*1) : the value at the ac coupling of tcxo parts and the clki pin by the capacity of 1000pf. ? the voltage level which duty of clki becomes 50% (high time = low time) is defined as vcenter. ? trckt and tfckt are defined by the change time between vcenter + 0.30[v] and vcenter - 0.30[v]. ? the timing observation level of tfreq is to be vcenter (duty=50%).
YMU769 preliminary 11 z cpu interface the ac characteristics of a cpu interface are measured on condition as follows. the input conditions at the time of measurement : v ih = 0.8iovdd, v il =0.2iovdd the measurement points : v ih = 0.65iovdd, v il =0.35iovdd v oh = 0.65iovdd, v ol =0.35iovdd cpu interface 1 (in the case of iovdd R 2.65v) (write cycle) item symbol min max. unit address setup time t ads 50 ns address hold time t adh 0 ns chip select setup time t css 50 ns chip select hold time t csh 0 ns write pulse width t ww 50 ns data setup time t wds 30 ns data hold time t wdh 0 ns t op =-20 85c, vdd=iovdd=2.65 3.30v, capacitor load=50 pf (read cycle) item symbol min max. unit access time from /rd pin t accrd 70 ns access time from /cs pin t acccs 70 ns access time from /a0 pin t acca0 70 ns data hold time from /rd pin t dhrd 0 ns data hold time from /cs pin t dhcs 0 ns data hold time from a0 pin t dha0 0 ns high-impedance transition time from /rd pin t dzrd 30 ns high-impedance transition time from /cs pin t dzcs 30 ns t op =-20 85c, vdd=iovdd=2.65 3.30v, capacitor load=50 pf i oh = -1.0ma, i ol = +1.0ma (d0 d7 pin)
YMU769 12 preliminary cpu interface 2 (in the case of iovdd < 2.65) (write cycle) item symbol min max. unit address setup time t ads 50 ns address hold time t adh 0 ns chip select setup time t css 50 ns chip select hold time t csh 0 ns write pulse width t ww 50 ns data setup time t wds 50 ns data hold time t wdh 0 ns t op =-20 85c, vdd=2.65 3.30v, iovdd=1.65 less than 2.65v, capacitor load=30 pf (read cycle) item symbol min max. unit access time from /rd pin t accrd 80 ns access time from /cs pin t acccs 80 ns access time from /a0 pin t acca0 80 ns data hold time from /rd pin t dhrd 0 ns data hold time from /cs pin t dhcs 0 ns data hold time from a0 pin t dha0 0 ns high-impedance transition time from /rd pin t dzrd 50 ns high-impedance transition time from /cs pin t dzcs 50 ns t op =-20 85c, vdd=2.65 3.30v, iovdd=1.65 less than 2.65v, capacitor load=30 pf i oh = -0.2ma, i ol = +0.2ma (d0 d7 pin)
YMU769 preliminary 13 write cycle note : t adh : the hold time of a0 pin, which is defined with respect to the point where the rise of /wr has reached 0.65*iovdd under the condition that both two specifications (t csh , t wdh ) are secured more than minimum value (=0ns). t csh : the hold time of /cs pin, which is defined with respect to the point where the rise of /wr has reached 0.65*iovdd under the condition that both two specifications (t adh , t wdh ) are secured more than minimum value (=0ns). t wdh : the hold time of d0 d7 pins, which is defined with respect to the point where the rise of /wr has reached 0.65*iovdd under the condition that both two specifications (t adh , t csh ) are secured more than minimum value (=0ns). t ads : the hold time of a0 pin, which is defined with respect to the point where /wr has become invalid (0.35*iovdd) under the condition that all of three specifications (t css , t ww , t wds ) are secured more than minimum value. t css : the hold time of /cs pin, which is defined with respect to the point where /wr has become invalid (0.35*iovdd) under the condition that all of three specifications (t ads , t ww , t wds ) are secured more than minimum value.
YMU769 14 preliminary read cycle note : t acca0 : the access time until d0 d7 are defined (0.65*iovdd or 0.35*iovdd) after a0 is defined (0.65*iovdd or 0.35*iovdd). considers that /rd and /cs are defined beforehand (*1). t acccs : the access time until d0 d7 are defined (0.65*iovdd or 0.35*iovdd) after /cs is defined (0.35*iovdd). considers that a0 and /rd are defined beforehand (*1). t accrd : the access time until d0 d7 are defined (0.65*iovdd or 0.35*iovdd) after /rd is defined (0.35*iovdd). considers that a0 and /cs are defined beforehand (*1). t dhrd : the time (hold time) until d0 d7 output valid data after /rd becomes enable (=0.35*iovdd) under the condition that a0 and /cs secure sufficient hold time (*2). t dhcs : the time (hold time) until d0 d7 output valid data after /cs becomes enable (=0.35*iovdd) under the condition that a0 and /rd secure sufficient hold time (*2). t dha0 : the time (hold time) until d0 d7 output valid data after a0 becomes enable (0.65*iovdd or 0.35*iovdd) under the condition that /rd and /cs secure sufficient hold time (*2). t dzrd : the time until d0 d7 become high impedance status after /rd becomes disable (=0.65*iovdd) under the condition that a0 and /cs secure sufficient hold time (*2). t dzcs : the time until d0 d7 become high impedance status after /cs becomes disable (=0.65*iovdd) under the condition that a0 and /rd secure sufficient hold time (*2).
YMU769 preliminary 15 (*1) ? defined beforehand.? means, in the case of /cs : the status that /cs is defined (0.35*iovdd) before more than the time of t acccs with respect to the point where d0 d7 are defined (0.65*iovdd or 0.35*iovdd). in the case of /rd : the status that /rd is defi ned (0.35*iovdd) before more than the time of t accrd with respect to the point where d0 d7 are defined (0.65*iovdd or 0.35*iovdd). in the case of a0 : the status that a0 is defined (0.35*iovdd or 0.65*iovdd) before more than the time of t acca0 with respect to the point where d0 d7 are defined (0.65*iovdd or 0.35*iovdd). /cs or /rd valid d0 ~ d7 a0 more than the maximum value of t acca0 more than the maximum value of t acccs or t accrd (*2) ? sufficient hold time? means, at t dhrd measurement : the status that the enable time of a0 and /cs pins input are secured more than 0ns with respect to the point where d0 d7 can not hold valid data. at t dhcs measurement : the status that the enable time of a0 and /rd pins input are secured more than 0ns with respect to the point where d0 d7 can not hold valid data. at t dha0 measurement : the status that the enable time of /cs and /rd pins input are secured more than 0ns with respect to the point where d0 d7 can not hold valid data. (example: at t dhrd measurement) a0 /rd d0 d7 /cs more than 0ns valid valid t dhrd more than 0ns ~
YMU769 16 preliminary z analog characteristics conditions of t op =25c, vdd=3.00v, iovdd=1.80v and spvdd-l/-r=3.60v apply to all items. sp amplifier parameter min. typ. max. unit gain setting (fixed) 2 times min. load resistance (rl) 8 ? max. output voltage amplitude (rl=8 ? ) 6.0 vp-p max. output power (rl=8 ? , thd+n 1.0%) 580 mw thd + n (rl=8 ? , f=1 khz, output = 400mw) 0.025 % noise at no signal (a-filter: weighting filter) -90 dbv psrr (f=1 khz) 90 db amplitude center potential (vsel2, vsel1 =0, 0) 0.6vdd v (vsel2, vsel1 =0, 1) 0.5vdd v (vsel2, vsel1 =1, 0) 0.67vdd v differential output voltage 10 50 mv max. load capacity connectable to spout1 and spout2 pin (*) 1000 pf (*) : the maximum of 1000pf can be connected to spout1-l/-r pin, and the maximum of 1000pf can be connected to spout2-l/-r pin. eq amplifier item min. typical max. unit gain settable range 30 db max. output voltage amplitude 2.7 vp-p thd + n (f=1 khz) 0.05 % noise at no signal (a-filter) -90 dbv input impedance 10 m ? feedback resistance between eq2-l/-r and eq3-l/-r 20 k ? sp volume item min. typical max. unit volume setting range -30 0 db volume step width 1 db thd + n (f=1 khz) 0.05 % eq volume item min. typical max. unit volume setting range -30 0 db volume step width 1 db noise at no signal (a-filter) -90 dbv max. output current 120 a max. output voltage amplitude 1.5 vp-p output impedance 300 600 ?
YMU769 preliminary 17 hp volume item min. typical max. unit volume setting range -30 0 db volume step width 1 db noise at no signal (a-filter) -90 dbv max. output current 120 a max. output volt. amplitude 1.5 vp-p output impedance 300 600 ? vref item min. typical max. unit vref voltage 0.5vdd v dac item min. typical max. unit resolution 16 bit full scale output volt. 1.5 vp-p thd+n (f= 1 khz) 0.5 % noise at no signal (a-filter) -85 -80 dbv frequency response (f=50hz to 20 khz) -3.0 (*) +0.5 db (*): reduction of response in high frequency range caused by aperture effect
YMU769 18 preliminary ? external dimensions of package
YMU769 agency all rights reserved address inquiries to: semiconductor sales & marketing department head office 203, matsunokijima, toyooka-mura iwata-gun, shizuoka-ken, 438-0192, japan tel. +81-539-62-4918 fax. +81-539-62-5054 tokyo office 2-17-11, takanawa, minato-ku, tokyo, 108-8568, japan tel. +81-3-5488-5431 fax. +81-3-5488-5088 osaka office 3-12-12, minami senba, chuo-ku, osaka city, osaka, 542-0081, japan tel. +81-6-6252-6221 fax. +81-6-6252-6229 printed in japan 2003

▲Up To Search▲

Price & Availability of YMU769

	To Download YMU769 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .