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VP305/6 satellite channel decoder preliminary information dm5009-1.0 09/07/98 mitel confidential information technical manual this is an unpublished work the copyright in which vests in mitel. all rights reserved. the information contained herein is the property of mitel and is supplied without liability for errors or omissions. no part may be reproduced or used except as authorised by contract or other written permission. the copyright and the foregoing restriction on reproduction and use extend to all media in which the media may be embodied. the VP305/6 is a decoder for digital satellite television transmissions to the european broadcast union ets 300 421 specification (ref. 1). they receive digitised i and q signals from the tuner, demodulate the qpsk data and provide a complete forward error correction, (fec) and de- scrambling function. the output is in the form of packetised mpeg2 transport stream data. the VP305/6 also provides automatic gain control and synchronising signals to the rf front end devices. the VP305 has only a parallel interface port to the control microprocessor. the vp306 has both a serial i2c port and a parallel interface port to the control microprocessor.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 2 contents. 1. functional description. ..............................................................................................7 1.1. system overview. ..........................................................................................................7 1.2. the qpsk demodulator block. .....................................................................................9 1.2.1. input requirements. .............................................................................................10 1.2.3. matched filters.....................................................................................................10 1.2.4. decimation filters.................................................................................................10 1.2.5. carrier frequency synchronisation ......................................................................11 1.2.6. symbol synchronisation and tracking..................................................................12 1.3. the viterbi decoder block. ............................................................................................13 1.3.1. viterbi error count measurement.........................................................................14 1.3.2. viterbi error count coarse indication....................................................................15 1.4. the de-interleaver block. ..............................................................................................16 1.5. the reed solomon block. .............................................................................................18 1.6. the energy dispersal (descrambler) block. ..................................................................18 1.6.1. output stage........................................................................................................19 1.7. microprocessor interface. ..............................................................................................19 2. register details ............................................................................................................. 20 2.1. parallel interface register map. .....................................................................................20 2.2. serial interface register map. ........................................................................................23 2.3. bank: register bank address - parallel mode only......................................................25 2.4. radd: i2c register address - serial mode only. ..........................................................26 2.5. bank 0: monitor qpsk read registers..........................................................................27 2.5.1. id: identification register. ....................................................................................27 2.5.2. int_qpsk: interrupt for qpsk block, register....................................................27 2.5.3. int_fec: interrupt fec register.........................................................................28 2.5.4. status: status register. ....................................................................................29 2.5.5. agc_lvl: agc loop voltage meter register.......................................................30 2.5.6. cr_vcof u & l: measured vco frequency registers. ......................................30 2.5.7. ie_qpsk: interrupt enable qpsk register..........................................................31 2.6. bank 1: program qpsk registers. ...............................................................................32 2.6.1. sym_config: symbol configuration register. ...................................................32 2.6.2. sym_rp: symbol afc reference period register. ..............................................33 2.6.3. sym_nf u & l: symbol input nominal frequency registers................................33
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 3 2.6.4. sym_ratio: symbol input decimation factor register. ...................................... 34 2.6.5. agc_ref: reference agc level registers. ....................................................... 34 2.6.6. agc_bw: agc estimation bandwidth register................................................... 35 2.7. bank 2: program qpsk registers................................................................................ 36 2.7.1. scale: iout and qout outputs, scale factor register. .................................... 36 2.7.2. snr_ths: signal to noise ratio estimator threshold register. ............................ 36 2.7.3. cr_offset: carrier loop dc offset register..................................................... 37 2.7.3.1. acquisition phase. ................................................................................. 38 2.7.3.2. tracking phase...................................................................................... 39 2.7.4. cr_rp: carrier reference period register........................................................... 39 2.7.5. cr_kp: carrier loop filter gain (p term) register................................................. 40 2.7.6. cr_kd: carrier loop filter gain (d term) register. ............................................... 40 2.7.7. cr_thsl: carrier lock detector threshold register. ........................................... 41 2.8. bank 3: program qpsk registers................................................................................ 42 2.8.1. cr_swr: carrier sweep rate register................................................................ 42 2.8.2. cr_uswl u & l: carrier upper sweep limit registers....................................... 43 2.8.3. cr_lswl u & l: carrier lower sweep limit registers. ...................................... 44 2.8.4. cr_config: carrier configuration register. ...................................................... 44 2.8.5. config: configuration register.......................................................................... 45 2.9. bank 4: monitor fec read registers. ........................................................................... 46 2.9.1. vit_err_c h & l: viterbi error count registers................................................. 46 2.9.2. rs_ubc: reed solomon uncorrected block count register. .............................. 46 2.10. bank 5: program fec registers. ................................................................................. 47 2.10.1. vit_mode: viterbi mode register..................................................................... 47 2.10.2. vit_err h, m & l: viterbi error period registers. ............................................ 48 2.10.3. vi_max_err: viterbi maximum bit error count register. ................................. 48 2.10.4. vi_ber_per: viterbi bit error rate based synchronisation period register. ..... 49 2.10.5. vi_ber_lim: viterbi bit error rate based synchronisation limit register. .......... 49 2.11. bank 6: program fec and general control registers.................................................. 50 2.11.1. vit_ctrl1: viterbi control synchronisation byte register 1 ............................. 50 2.11.2. vit_ctrl2: viterbi control synchronisation byte register 2 ............................. 51 2.11.3. ie_fec: interrupt fec register......................................................................... 52 2.11.4. stat_en: status enable register..................................................................... 53 2.11.5. gen_ctrl: general control register. .............................................................. 54
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 4 2.11.6. gpp_ctrl: general purpose port control register. .........................................54 2.11.7. reset: reset register. .....................................................................................55 2.12. bank 7: program test registers. ...................................................................................56 2.12.1. test1: test 1 register - for diagnostic / qualification purposes only. ...............56 2.12.2. test2: test 2 register - for diagnostic / qualification purposes only. ...............56 2.12.3. test3: test 3 register - for diagnostic / qualification purposes only. ...............57 3. microprocessor control. .........................................................................................58 3.1. i2c bus interface.......................................................................................................... ..58 3.1.1. examples of i2c bus messages: ........................................................................59 3.2. parallel interface. ........................................................................................................ ..60 3.2.1. examples of writing to and reading from the parallel interface. ..........................60 3.2.2. parallel interface write cycle description. ...........................................................60 3.2.3. parallel interface read cycle description. ...........................................................63 4. timing information. ........................................................................................................65 4.1. i2c bus timing. ............................................................................................................ ...65 4.2. parallel interface write cycle timing. .............................................................................66 4.3. parallel interface read cycle timing. .............................................................................66 4.4. data input timing. ......................................................................................................... .67 5. mpeg packet data output...........................................................................................68 5.1. data output format......................................................................................................... 68 5.2. data output timing. ........................................................................................................ 70 6. VP305/6 operating conditions. ...................................................................................71 6.1. recommended operating conditions.............................................................................71 6.2. electrical characteristics................................................................................................7 2 6.3. crystal specification. ..................................................................................................... 73 6.4. absolute maximum ratings. ...........................................................................................73 6.5. pinout description......................................................................................................... .74 6.6. alphabetical listing of the pinout....................................................................................77 6.7. numerical listing of the pinout. ......................................................................................78 7. references. .................................................................................................................. ....80 8. appendix 1: features .....................................................................................................81 9. appendix 2: lock acquisition algorithm. ...............................................................82 9.1. pre conditions. ............................................................................................................ ..82 9.2. lock acquisition algorithm.............................................................................................82
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 5 list of figures. figure 1. VP305/6 block diagram................................................................................................ ... 7 figure 2. system application diagram . ........................................................................................... 9 figure 3. carrier and symbol synchronisation diagram.................................................................. 9 figure 4. qpsk constellation................................................................................................... ....... 10 figure 5. symbol filtering ..................................................................................................... ........... 10 figure 6. frequency sweep generator ............................................................................................ 11 figure 7. viterbi block diagram showing error count generation..................................................... 14 figure 8. viterbi error count measurement ..................................................................................... 1 5 figure 9. viterbi error count coarse indication ................................................................................ 16 figure 10. conceptual diagram of the convolutional de-interleaver block ...................................... 17 figure 11. energy dispersal conceptual diagram............................................................................ 18 figure 12. eye diagram......................................................................................................... .......... 34 figure 13. snr threshold vs es / no ........................................................................................... .. 36 figure 14. carrier sweep rise and fall times vs. cr_offset........................................................ 38 figure 15. carrier phase error detector gain................................................................................... 40 figure 16. carrier sweep rate for a delta frequency of 10mhz. .................................................... 43 figure 17. parallel interface write cycle action diagram.................................................................. 61 figure 18. parallel interface read cycle action diagram .................................................................. 63 figure 19. i2c bus timing...................................................................................................... ........... 65 figure 20. parallel interface write cycle timing diagram.................................................................. 66 figure 21. parallel interface read cycle timing diagram .................................................................. 66 figure 22. VP305/6 data input timing diagram................................................................................ 67 figure 23. VP305/6 transport packet header bytes ...................................................................... 68 figure 24. VP305/6 output data wave form diagram ...................................................................... 69 figure 25. VP305/6 data output timing diagram ............................................................................. 70 figure 26. crystal oscillator circuit. ......................................................................................... ........ 73 figure 27. pin connections - top view .......................................................................................... ... 79
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 6 list of tables. table 1. decimation ratios..................................................................................................... ..........11 table 2. viterbi decoder input format .......................................................................................... ....13 table 3. viterbi decoder code rate ............................................................................................. .....13 table 4. de-interleaver data sequence .......................................................................................... .17 table 5a. bank register ........................................................................................................ ........20 table 5b. register bank 0. bank[5:3] = 0 ......................................................................................2 0 table 5c. register bank 1. bank[5:3] = 8....................................................................................... 20 table 5d. register bank 2. bank[5:3] = 16 ....................................................................................21 table 5e. register bank 3. bank[5:3] = 24 ....................................................................................21 table 5f. register bank 4. bank[5:3] = 32 .....................................................................................2 1 table 5g. register bank 5. bank[5:3] = 40 ....................................................................................22 table 5h. register bank 6. bank[5:3] = 48 ....................................................................................22 table 5i. register bank 7. bank[5:3] = 56...................................................................................... 22 table 6a. qpsk register details................................................................................................ .....23 table 6b. fec register details ................................................................................................. ......24 table 7. bank address decodes for parallel mode ........................................................................25 table 9. viterbi bit error rate threshold...................................................................................... ......49 table 10. number of correct bits in the sync byte. .........................................................................50 table 11. number of correct sync bytes to retain lock ....................................................................50 table 12. number of consecutive sync bytes to establish block lock..............................................51 table 13. number of incorrect sync bytes to lose lock....................................................................54 table 14. enable / disable circuit blocks ...................................................................................... ...56 table 15. i2c bus timing ....................................................................................................... ...........65 table 16. parallel bus timing .................................................................................................. .........67 table 17. mpeg data output rates ............................................................................................... ...70 table 18. recommended operating conditions...............................................................................71 table 19. dc characteristics ................................................................................................... .......72 table 20. pinout details....................................................................................................... ............76 table 21. alphabetical listing of the pinout................................................................................... ...77 table 22. numerical listing of the pinout ...................................................................................... ...78
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 7 please note: this manual has the following convention: all numerical values are shown as decimal numbers, unless otherwise defined. 1. functional description. qpsk de-inter leaver viterbi reed solomon energy dispersal test microprocessor interface timing / sync pscal sys_clk iin5:0 qin5:0 3 3 symclk 8 8 8 mdoen mdo7:0 xti xto xtck irq dtack d7:0 sda a2:0 r/w as cs ser gpp0 reset res intqp intvi mclk mostrt cr_vco agc_out sym_vco 2 2 2 bkerr gpp4:1 4 verr moval clock status test1 test2 test3 fig. 1. VP305/6 block diagram. 1.1. system overview. the VP305/6 decoder, together with the sl1710 i/q down converter and the vp216/7 dual analog to digital converter (adc) devices will provide a dvb compliant, satellite receiver system, see figure 2 on page 9. before transmission, the data is processed using forward error correction techniques. energy dispersal is added to even out 'ones' and 'zeros' for the power handling of the satellite output transmission devices. the VP305/6 device decodes the signal by reversing all these encoding techniques. the VP305/6 contains three phase lock loop systems for control of the voltage controlled oscillators in the sl1710, the vp216/7 and an internal numerically controlled oscillator (nco) in the VP305/6. the nco can be set to provide a triangular wave form frequency search to establish symbol lock. there are also two agc systems in the VP305/6, one controlling the sl1710 gain and a second internal agc control of the output power levels from the qpsk block to the viterbi block. a crystal oscillator maintaining circuit is provided to sustain a stable frequency reference clock for the synthesiser loops. if a crystal is not used, the reference frequency signal may be input on the xti pin.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 8 a system clock (sys_clk) running at twice the symbol data rate is provided by the vco on the vp216/7 adc. the dual adc circuit digitises the in phase (i) and quadrature phase (q) analog signals providing two, six bit binary offset, data channels. the code range is, from 000000 = least positive valid output, to 111111 = most positive valid output. these six bit data channels are input to the VP305/6 on the iin and qin pins to the qpsk demodulator block, see figure 2 on page 9. there the data is decimated and filtered to obtain the soft decision symbol data to pass to the viterbi decoder. the qpsk block also generates a bit clock and resolves the p /2 demodulation phase ambiguity. the viterbi decoder recovers the data by a process of de-puncturing, probability analysis and bit error correction, to obtain the eight bit wide, data bit stream. it also rearranges the bit stream into bytes, providing a byte clock and packet start signal for the subsequent stages. an indication of the bit error rate in the data, is provided in the viterbi block, by comparing the delayed input data bit stream with the decoded output data bit stream. an actual bit error count may be read from registers and a coarse indication of the number of errors is provided to facilitate satellite receiver dish alignment. the data is then passed to the de-interleaver block where the data is reorganised in a series of fifos into the 204 byte blocks for the reed solomon decoder. the de-interleaver depth is 12. the reed solomon decoder is able to correct up to eight byte errors found in the byte data stream. if there are too many errors to be corrected, the packet will be flagged as uncorrectable. the 16 check bytes are removed and the 188 byte packet is passed to the next block. the final data processing block removes energy dispersion and inverts the inverted packet synchronisation byte which is used to mark every eighth 188 byte data packet. the data output from the VP305/6 is in the form of mpeg2 transport stream data packets on the mdo7:0 data bus, together with clock, data start, data valid and block error signals. the data rate is automatically varied, according to the puncture rate, to reduce the instantaneous data rate and the inter packet period.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 9 vco lpf lpf sl1710 i/q down convert vp216/7 dual adc iin qin sys_clk vco loop filter loop filter 479.5mhz pscal cr_vco sym_vco VP305/6 14.984375mhz agc loop filter saw sp5658 freq synth. from lnb microprocessor agc_out /32 fig. 2. system application diagram. 1.2. the qpsk demodulator block. the qpsk demodulator block performs the function of locking the receiver system to the incoming data stream. it controls the voltage controlled oscillators (vco) in the sl1710 i/q down converter and the vp216/7 dual analog to digital converter (adc). the carrier frequency vco is locked to maintain the intermediate frequency (if) of 479.5mhz. the symbol frequency vco synthesiser loop is locked to the twice the required symbol frequency (in the zero decimation case) and generates the system clock sys_clk which is running at the bit rate. /32 vco lpf lpf sym_rp sl1710 i/q down convert vp216/7 dual adc iin qin sys_clk xti vco loop filter loop filter 479.5mhz pscal cr_vco sym_vco VP305/6 14.984375mhz cr_rp sym_nf afc cr_u/lswl conv conv vco sweep gen fig. 3. carrier and symbol frequency synthesiser diagram.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 10 1.2.1. input requirements. the data input is digitised six bit i and q channel data in the form of either binary format or offset 2's complement data. the qpsk phase constellation representation is shown below. i = 0 q = 1 i = 0 q = 0 i = 1 q = 0 i = 1 q = 1 i q fig. 4. qpsk constellation. 1.2.3. matched filters the decimation filter and matched filter together have a 0.35 roll-off square-root-raised-cosine frequency response as in reference 1. 1.2.4. decimation filters in order to adjust to the wide range of symbol rates (5 to 30msym/s), the i and q data in may be decimated by varying degrees. the system also allows for the adc sample clock to be adjusted to within the range 30 to 62mhz. the sample rate at the input to the matched filter is equal to twice the symbol rate, 2rs. the sym_dr bits in the sym_config register can be programmed to allow for the following filtered symbol rates at the input to the VP305/6: 2rs, 3rs, 4rs, where rs = symbol rate. sym_ratio unfiltered decimation matched filter sym_rp filtered decimation iin qin fig. 5. symbol filtering. the sym_ratio register allows the input symbol rate to be extended further to cover 6rs, 8rs, 12rs, 16rs, 24rs, 32rs, 48rs and 64rs unfiltered decimation rates. the number of samples / symbol (m) can be calculated from the formula: m = (sym_dr over sample rate) * (2 sym_ratio ) the range of values of m is shown in the table below.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 11 sym_ratio01234 sym_dr m samples/sym m samples/sym m samples/sym m samples/sym m samples/sym 0 - (over sample 2) 2 4 8 16 32 1 - (over sample 4) 4 8 16 32 64 2 - (over sample 3) 3 6 12 24 48 table 1. decimation ratios. 1.2.5. carrier frequency synchronisation the sl1710 local oscillator frequency of 479.5mhz is maintained by a frequency synthesis loop on the VP305/6. the sl1710 voltage controlled oscillator (vco) frequency is divided internally by 32 to generate a push-pull feedback reference frequency signal. this is connected to the VP305/6 pscal pecl inputs and then to the cr_u/lswl dividers. the output from the cr_u/lswl dividers is compared with the crystal oscillator frequency divided by the cr_rp division ratio. a feedback signal (cr_vco) is output to an active filter to complete the loop and control the sl1710 vco, see fig. 3 on page 9. the internal frequency sweep generator is controlled by the cr_swr, cr_uswl,cr_lswl, cr_rp registers and turned on and off by the cr_sw bit in the config register. the diagram in fig. 3 on page 9 shows the registers which set up the dividers for both the carrier and symbol phase locked loops. f t upper sweep limit lower sweep limit sweep start point fig. 6. frequency sweep generator. the carrier frequency reference period (cr_rp register) sets the count of the crystal clock cycles (xti pin). this sets the reference for the measurement of the i/q down converter vco frequency (pscal pins). the register value sets the 4 most significant bits of a 14 bit counter. the actual count is cr_rp[3:0] * 1024.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 12 the comparison frequency, fcomp = fcrystal cr_rp * 1024 mhz. the upper and lower sweep boundaries are set by the cr_uswl and cr_lswl respectively. these registers actually set the division ratios for dividing the i/q down converter vco frequency. the value programmed must take account of any fixed prescaler in the i/q down converter, for the sl1710 this is divide by 32. the comparison frequency, fcomp = fvco 32 * cr_u/lswl mhz. therefore, fcrystal cr_rp * 1024 = fvco 32 * cr_u/lswl therefore, fcrystal * 32 * cr_u/lswl = fvco * cr_rp * 1024 therefore, fvco fcrystal = 32 * cr_u/lswl cr_rp * 1024 the upper and lower sweep limits can be expressed in terms of the above equations together with two further terms including the delta variation in frequency. let the delta variation in frequency = d f. then the frequency limits are fvco + d f and fvco - d f. therefore, cr_uswl = (fvco + d f) * cr_rp * 1024 fcrystal * 32 and cr_lswl = (fvco - d f) * cr_rp * 1024 fcrystal * 32 when the afc circuit achieves lock, as indicated by the cr_flock bit in the status register going high, the scaled carrier frequency can be read from the cr_vcof u & l registers. the actual carrier frequency is found from the following formula: fvco = 32 * fcrystal cr_rp * 1024 * cr_vcof mhz see page 30. 1.2.6. symbol synchronisation and tracking the vp216/7 local oscillator frequency must be programmed to be at least twice the required symbol rate and is maintained by a phase locked loop on the VP305/6. the adc sample frequency should be adjusted by setting the sym_nf and sym_rp division ratios to match the decimation rate chosen. the vp216/7 voltage controlled oscillator (vco) frequency is connected to the VP305/6 sys_clk input and then to the sym_nf divider. the output from the sym_nf divider is compared with the crystal oscillator frequency divided by the sym_rp division ratio. a push-pull feedback signal (sym_vco) is output to an active filter to complete the loop and control the vp216/7 vco, see fig. 3 on page 9.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 13 1.3. the viterbi decoder block. the viterbi decoder input data format uses three bit, two's complement coding representation of the data in the following form, (binary numbers): i or q value interpretation 011 most likely one 010 001 000 least likely one 111 least likely zero 110 101 100 most likely zero table 2. viterbi decoder input format. the first task for the viterbi decoder is to 'de-puncture' the data. this is a process of restoring data bits which have been removed (punctured), prior to transmission, to improve the transmission efficiency. the de-puncture code rate must be programmed into the vit mode register. the following patterns are used: vitcr[2:0] code rate input bit stream output bit stream 0 1/2 i = x 1 q = y 1 x = 1 y = 1 1 2/3 i = x 1 y 2 y 3 q = y 1 x 3 y 4 x = 1010 y = 1111 2 3/4 i = x 1 y 2 q = y 1 x 3 x = 101 y = 110 3 5/6 i = x 1 y 2 y 4 q = y 1 x 3 x 5 x = 10101 y = 11010 4 7/8 i = x 1 y 2 y 4 y 6 q = y 1 y 3 x 5 x 7 x = 1000101 y = 1111010 table 3. viterbi decoder code rate. the zeros in the above table represent unknown data bit values, effectively error bits. the decoder uses a trace back trellis technique to remove the uncertainty and recover the correct data. the trace back depth is 128.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 14 1.3.1. viterbi error count measurement. a measure of the effectiveness of the viterbi decoder in removing bit errors is provided in the VP305/6. the incoming data bit stream is delayed and compared with the decoded bit stream to obtain a count of errors corrected by the decoder, see the fig. 7 below. viterbi decoder delay comp error count data bit stream viterbi encoder fig. 7. viterbi block diagram showing error count generation. the measurement system has a programmable register to determine the number of data bits (the error count period) over which the count is being recorded. a read register indicates the error count result and an interrupt can be generated to inform the host microprocessor that a new count is available. the vit err h-m-l group of three registers is programmed with required number of data bits (the error count period) (vitep[23:0]). the actual value is four times vitep[23:0]. the count of errors found during this period is loaded by the VP305/6 into the vit err c h-l pair of registers when the bit count vitep[23:0] is reached. at the same time an interrupt is generated on the irq line. the actual error count value is four times verrc[15:0]. if a value of 65535 is read out, the error count is too large for the verrc[15:0] registers, so the error period in vitep[23:0] should be reduced. the interrupt is enabled by setting the ie_fec[2] bit in the ie_fec register, see page 52. verrc[15:0] is not cleared by reading the register, it is only loaded with the error count.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 15 vitep[23:0] data bits error count verrc[15:0] 0 0 irq fig. 8. viterbi error count measurement. figure 8 above shows the bit errors rising until the maximum programmed value of vitep[23:0] is reached, when an interrupt is generated on the irq line to advise the host microprocessor that a new value of bit error count has been loaded into the verrc[15:0] register. the irq line will go high when the ie_fec register is read by the host microprocessor. the error count may be expressed as a ratio: verrc[15:0] vitep[23:0] . 1.3.2. viterbi error count coarse indication. to assist in the process of aligning the receiver dish aerial, a coarse indication of the number of bit errors being received can be provided by monitoring the verr line with the following set up conditions. the frequency of the output wave form will be a function of the bit error count (triggering the maximum value programmed into the vi max err register (vmerr[7:0])) and the dish alignment on the satellite. this verr mode is enabled by setting the intvis bit in the test2 register. figure 9 below shows the bit errors rising to the maximum programmed value and triggering a change of state on the verr line.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 16 dat a bit s vit e r b i coar s e bit error cou nt vme r r [7:0] 0 0 ve r r fig. 9. viterbi error count coarse indication. 1.4. the de-interleaver block. before transmission, the data bytes are interleaved with each other in a cyclic pattern of twelve. this ensures the bytes are spaced out, so that successive message bytes are transmitted with a separation of at least 12 bytes. this system is used to avoid the possibility of a noise spike corrupting a group of consecutive message bytes. the diagram below shows conceptually how the convolutional de-interleaving system works. the synchronisation byte is always loaded into the first-in-first-out (fifo) memory in branch 0. the switch is operated at regular byte intervals to write successively received bytes into the next branch. after 12 bytes have been received, byte 13 is written next to the synchronisation byte in branch 0, etc. only when the fifos are full, will the read out of the 204 byte message be enabled. on the VP305/6, this function is realised in random access memory (ram) with some spare capacity to avoid messages being over written before they are read out.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 17 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 sync word route 17x1 17x2 bytes 17x3 bytes 17x4 bytes 17x5 bytes 17x6 bytes 17x7 bytes 17x8 bytes 17x9 bytes 17x10 bytes 17x11 bytes one byte per position fig. 10. conceptual diagram of the convolutional de-interleaver block. the byte sequence for the first 204 byte block is shown below. each row represents one branch fifo. 1 13 25 37 49 61 73 85 97 109 121 133 145 157 169 181 193 2 14 26 38 50 62 74 86 98 110 122 134 146 158 170 182 194 3 15 27 39 51 63 75 87 99 111 123 135 147 159 171 183 195 4 16 28 40 52 64 76 88 100 112 124 136 148 160 172 184 196 5 17 29 41 53 65 77 89 101 113 125 137 149 161 173 185 197 6 18 30 42 54 66 78 90 102 114 126 138 150 162 174 186 198 7 19 31 43 55 67 79 91 103 115 127 139 151 163 175 187 199 8 20 32 44 56 68 80 92 104 116 128 140 152 164 176 188 200 9 21 33 45 57 69 81 93 105 117 129 141 153 165 177 189 201 10 22 34 46 58 70 82 94 106 118 130 142 154 166 178 190 202 11 23 35 47 59 71 83 95 107 119 131 143 155 167 179 191 203 12 24 36 48 60 72 84 96 108 120 132 144 156 168 180 192 204 table 4. de-interleaver data sequence.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 18 1.5. the reed solomon block. in the transmission system, the mpeg2 message packet is encoded using the reed solomon rs(204,188, t=8) shortened code. this converts the 188 byte data packet into a reed solomon encoded block containing 204 bytes. the 16 check bytes allow the decoding system to search the packet for errors and correct up to eight bytes containing errors. if there are more than eight bytes containing errors, the packet is flagged as containing uncorrectable errors by pulling the bkerr pin low and setting the tei bit in the second byte of the packet header, see figure 21 on page 68. the number of blocks containing uncorrectable errors may be read from the rs ubc register which is reset to zero each time it is read. the 16 check bytes are discarded before the data packet is passed on to the energy dispersal block. sync byte 187 bytes 16 check bytes reed solomon encoded block. sync byte 187 bytes mpeg2 transport packet. 1.6. the energy dispersal (descrambler) block. before reed solomon encoding in the transmission system, the mpeg2 data stream is randomised using the configuration shown in figure 11 below. this is a pseudo random binary sequence (prbs) generator, with the polynomial: 1 + x 14 + x 15 the prbs registers are loaded with the initialisation sequence as shown, at the start of the first transport packet in a group of eight packets. this point is indicated by the inverted sync byte b8 hex . the normal sync. byte is 47 hex . the data starting with the first byte after the sync. byte is randomised. (the sync. bytes themselves are not randomised). in the decoder, the process of de-randomising or de scrambling the data is exactly the same as described above. 123456789101112131415 100101010000000 initialisation sequence xor fig. 11. energy dispersal conceptual diagram .
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 19 1.6.1. output stage. a complete transport stream data packet of 188 bytes is output on the mdo7:0 bus, clocked by the mclk signal. the mdo7:0 bus is enabled by pulling the mdoen low. the start sync byte is flagged by the mostrt signal going high and the moval signal will also go high to indicate a valid packet. if the packet contains uncorrectable bytes, a bkerr signal will go low on the first error byte and remain low until the end of the packet. the tei bit in the packet header can optionally be set automatically to indicate a packet with uncorrectable bytes. 1.7. microprocessor interface. this interface can be either a serial i2c bus or a parallel interface port, see section 3 starting on page 58.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 20 2. register details 2.1. parallel interface register map. the default state of almost all of the registers is zero, except the id register and unused registers. reserved or unused bits should be set to zero when writing to a register. nameadrd7d6d5d4d3d2d1d0r/w bank 0 reserved ad5 ad4 ad3 reserved w table 5a. bank register 0. (address byte = 0, data byte = next bank ) nameadrd7d6d5d4d3d2d1d0r/w id 0 id[7:0] chip identification r int_qpsk 1 int_qpsk[7:0] interrupt qpsk r int_fec 2 int_fec[7:0] interrupt fec r status 3 reserved status[6:0] r agc_lvl 4 agc_lvl[7:0] agc loop voltage meter r cr_vcof u 5 reserved cr_vcof[13:8] measured vco frequency (upper nibble) r cr_vcof l 6 cr_vcof[7:0] measured vco frequency (lower byte) r ie_qpsk 7 ie_qpsk[7:0] interrupt enable qpsk r/w table 5b. register bank 0. bank[5:3] = 0. note: in bank 0, the registers 1 to 6 are read only. writing to these addresses will have no effect. nameadrd7d6d5d4d3d2d1d0r/w id 0 id[7:0] chip identification r sym_config 1 reserved sym_config[5:0] symbol configuration r/w sym_rp 2 reserved sym_rp[3:0] symbol afc reference period r/w sym_nf u 3 sym_nf[15:8] symbol input nominal frequency (upper byte) r/w sym_nf l 4 sym_nf[7:0] symbol input nominal frequency (lower byte) r/w sym_ratio 5 reserved sym_ratio[2:0] r/w agc_ref 6 agc_ref[7:0] reference agc level r/w agc_bw 7 reserved int_dc agc_bw[2:0] r/w table 5c. register bank 1. bank[5:3] = 8.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 21 nameadrd7d6d5d4d3d2d1d0r/w id 0 id[7:0] chip identification r scale 1 scale[7:0] scale factor for iout and qout outputs r/w snr_ths 2 snr_ths[7:0] snr estimator threshold r/w cr_offset 3 cr_offset[7:0] carrier loop dc offset compensation value r/w cr_rp 4 reserved cr_rp[3:0] carrier reference period r/w cr_kp 5 cr_kp[7:0] carrier loop filter gain (p term) r/w cr_kd 6 cr_kd[7:0] carrier loop filter gain (d term) r/w cr_thsl 7 cr_thsl[7:0] carrier lock detector threshold r/w table 5d register bank 2. bank[5:3] = 16. nameadrd7d6d5d4d3d2d1d0r/w id 0 id[7:0] chip identification r cr_swr 1 cr_swr[7:0] carrier sweep rate r/w cr_uswl u 2 reserved cr_uswl[13:8] carrier upper sweep limit (upper nibble) r/w cr_uswl l 3 cr_uswl[7:0] carrier upper sweep limit (lower byte) r/w cr_lswl u 4 reserved cr_lswl[13:8] carrier lower sweep limit (upper nibble) r/w cr_lswl l 5 cr_lswl[7:0] carrier lower sweep limit (lower byte) r/w cr_config 6 cr_config[7:0] carrier configuration r/w config 7 config[7:0] configuration r/w table 5e. register bank 3. bank[5:3] = 24. nameadrd7d6d5d4d3d2d1d0r/w id 0 id[7:0] chip identification r vit_err_c h 1 verrc[15:8] - viterbi error count high byte r vit_err_c l 2 verrc[7:0] - viterbi error count low byte r rs_ubc 3 rsubc[7:0] - reed solomon uncorrected block count r not used 4 - 7 writing to these addresses will have no effect. reading will return 255 r/w table 5f. register bank 4. bank[5:3] = 32. note: in bank 4, the registers 1 to 3 are read only and registers 4 to 7 are not used. writing to these addresses will have no effect.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 22 nameadrd7d6d5d4d3d2d1d0r/w id 0 id[7:0] chip identification r vit_mode 1 iqswap f_lock reserved vitcr[2:0] - code rate r/w vit_err h 2 vitep[23:16] - viterbi error period high byte r/w vit_err m 3 vitep[15:8] - viterbi error period middle byte r/w vit_err l 4 vitep[7:0] - viterbi error period low byte r/w vi_max_err 5 vmerr[7:0] - viterbi max. bit error count r/w vi_ber_per 6 vbper[7:0] - viterbi bit error rate based synchronisation period r/w vi_ber_lim 7 vblim[7:0] - viterbi bit error rate based synchronisation limit r/w table 5g. register bank 5. bank[5:3] = 40. nameadrd7d6d5d4d3d2d1d0r/w id 0 id[7:0] chip identification r vit_ctrl1 1 bs_mode[1:0] vs_unlk[3:0] vbit_mv[1:0] r/w vit_ctrl2 2 reserved vs_lk[2:0] r/w ie_fec 3 ie_fec[7:0] interrupt enable fec r/w stat_en 4 stat_en[7:0] enable various outputs on status pin. r/w gen_ctrl 5 - - - mclkinv bso entei nsync[1:0] r/w gpp_ctrl 6 reserved gpp_ctrl[4:0] r/w reset 7 res - - - pr_ds pr_bs fr_qp pr_qp r/w table 5h. register bank 6. bank[5:3] = 48 . nameadrd7d6d5d4d3d2d1d0r/w id 0 id[7:0] chip identification r test1 1 reserved r/w test2 2 intvis - - - en[3:0] r/w test3 3 reserved r/w not used 4 - 7 writing to these addresses will have no effect. reading will return 255 r/w table 5i. register bank 7. bank[5:3] = 56 . note: in bank 7, the registers 4 - 7 are not used. writing to these addresses will have no effect. note: when writing to, or reading from registers which are part of a group, all registers in the group must be addressed for the data transfer to be sucessfully completed.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 23 2.2. serial interface register map. not available on VP305. the default state of all registers is reset to 0. reserved or unused bits should be set to zero when writing to a register. all values are shown as decimal numbers, unless otherwise defined. nameadrd7d6d5d4d3d2d1d0r/w radd iai ad6 ad5 ad4 ad3 ad2 ad1 ad0 w id 00 id[7:0] chip identification. writing to this address will have no effect. r int_qpsk 01 int_qpsk[7:0] interrupt qpsk r int_fec 02 int_fec[7:0] interrupt fec r status 03 reserved status[6:0] r agc_lvl 04 agc_lvl[7:0] agc loop voltage meter r cr_vcof u 05 reserved cr_vcof[13:8] measured vco frequency (upper nibble) r cr_vcof l 06 cr_vcof[7:0] measured vco frequency (lower byte) r not used 01-06 writing to these addresses will have no effect. w ie_qpsk 07 ie_qpsk[7:0] interrupt enable qpsk r/w id 08 id[7:0] chip identification. writing to this address will have no effect. r sym_config 09 reserved sym_config[5:0] symbol configuration r/w sym_rp 10 reserved sym_rp[3:0] symbol afc ref. period r/w sym_nf u 11 sym_nf[15:8] symbol input nominal frequency (upper byte) r/w sym_nf l 12 sym_nf[7:0] symbol input nominal frequency (lower byte) r/w sym_ratio 13 reserved sym_ratio[2:0] r/w agc_ref 14 agc_ref[7:0] reference agc level r/w agc_bw 15 reserved int_dc agc_bw[2:0] r/w id 16 id[7:0] chip identification. writing to this address will have no effect. r scale 17 scale[7:0] scale factor for iout and qout outputs r/w snr_ths 18 snr_ths[7:0] snr estimator threshold r/w cr_offset 19 cr_offset[7:0] carrier loop dc offset compensation value r/w cr_rp 20 reserved cr_rp[3:0] carrier reference period r/w cr_kp 21 cr_kp[7:0] carrier loop filter gain (p term) r/w cr_kd 22 cr_kd[7:0] carrier loop filter gain (d term) r/w cr_thsl 23 cr_thsl[7:0] carrier lock detector threshold r/w id 24 id[7:0] chip identification. writing to this address will have no effect. r cr_swr 25 cr_swr[7:0] carrier sweep rate r/w cr_uswl u 26 reserved cr_uswl[13:8] carrier upper sweep limit (upper nibble) r/w cr_uswl l 27 cr_uswl[7:0] carrier upper sweep limit (lower byte) r/w cr_lswl u 28 reserved cr_lswl[13:8] carrier lower sweep limit (upper nibble) r/w cr_lswl l 29 cr_lswl[7:0] carrier lower sweep limit (lower byte) r/w cr_config 30 cr_config[7:0] carrier configuration r/w config 31 config[7:0] configuration r/w table 6a. qpsk register details.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 24 nameadrd7d6d5d4d3d2d1d0r/w id 32 id[7:0] chip identification. writing to this address will have no effect. r vit_err_c h 33 verrc[15:8] - viterbi error count high byte r vit_err_c l 34 verrc[7:0] - viterbi error count low byte r rs_ubc 35 rsubc[7:0] - reed solomon uncorrected block count r not used 33-35 writing to these addresses will have no effect. w not used 36-39 writing to these addresses will have no effect. reading will return 255 r/w id 40 id[7:0] chip identification. writing to this address will have no effect. r vit_mode 41 iqswap f_lock reserved vitcr[2:0] - code rate r/w vit_err h 42 vitep[23:16] - viterbi error period high byte r/w vit_err m 43 vitep[15:8] - viterbi error period middle byte r/w vit_err l 44 vitep[7:0] - viterbi error period low byte r/w vi_max_err 45 vmerr[7:0] - viterbi max. bit error count r/w vi_ber_per 46 vbper[7:0] - viterbi bit error rate based synchronisation period r/w vi_ber_lim 47 vblim[7:0] - viterbi bit error rate based synchronisation limit r/w id 48 id[7:0] chip identification. writing to this address will have no effect. r vit_ctrl1 49 bs_mode[1:0] vs_unlk[3:0] vbit_mv[1:0] r/w vit_ctrl2 50 reserved vs_lk[2:0] r/w ie_fec 51 ie_fec[7:0] interrupt enable fec r/w stat_en 52 stat_en[7:0] enable various outputs on status pin. r/w gen_ctrl 53 - - - mclkinv bso entei nsync[1:0] r/w gpp_ctrl 54 reserved gpp_ctrl[4:0] r/w reset 55 res - - - pr_ds pr_bs fr_qp pr_qp r/w id 56 id[7:0] chip identification. writing to this address will have no effect. r test1 57 reserved r/w test2 58 intvis - - - en[3:0] r/w test3 59 reserved r/w not used 60-63 writing to these addresses will have no effect. reading will return 255 r/w table 6b. fec register details. note: when writing to, or reading from registers which are part of a group, all registers in the group must be addressed for the data transfer to be sucessfully completed.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 25 2.3. bank: register bank address - parallel mode only. registers are directly addressed via the address bus in banks of seven. in the bank register 0, the bits ad5, ad4 and ad3 are used to select the active register bank to be used until changed by writing to the bank register. for examples of use, see page 60. parallel mode - bank 0. address 0. type write. serial mode - see radd / id registers on pages 26 and 27. 76543210r/w reserved ad5 ad4 ad3 reserved w ad[2:0] reserved - not used. if these bits are written they are ignored by the VP305/6. this allows the microprocessor to write the bank address with the serial mode register address. ad[5:3] bank address these are the active bits in the register. see table 7 below for details. bank[5:0] decimal ad5 ad4 ad3 bank function 0 - 7 0 0 0 0 monitor interrupts and qpsk registers 8 - 15 0 0 1 1 program qpsk registers 16 - 23 0 1 0 2 program qpsk registers 24 - 31 0 1 1 3 program qpsk registers 32 - 39 1 0 0 4 monitor fec registers 40 - 47 1 0 1 5 program fec registers 48 - 55 1 1 0 6 program fec and general registers 56 - 59 1 1 1 7 program test registers table 7. bank address decodes for parallel mode . the register address in parallel mode may be calculated from the serial mode register address as follows: parallel address = serial address (mod 8) where mod = modulus example cr_config register: serial address =30, parallel = bank 3 address 6 bank address = 30 (serial address) alternatively, the bit value is: bank[5:3] = (30 - (30 mod 8)) = (30 - 6) = 24 this equates to bank 3, see table 7 above. ) parallel address = 30 mod 8 = 6.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 26 2.4. radd: i2c register address - serial mode only. not available on VP305. radd is the i2c register address. it is the first byte written after the vp306 i2c chip address when in write mode. to write to the chip, the microprocessor should send a start condition and the chip address with the write bit set, followed by the register address where subsequent data bytes are to be written. finally, when all the 'message' has been sent, a stop condition is sent to free the bus. to read from the chip from register address one, the microprocessor should send a start condition and the chip address with the read bit set, followed by the requisite number of scl clocks to read the bytes out. finally a stop condition is sent to free the bus. radd is not sent in this case. to read from the chip from an address other than one, the microprocessor should send the chip address with the write bit set, followed by the register address where subsequent data bytes are to be read from. then the microprocessor should send a start condition and the chip address with the read bit set, followed by the requisite number of scl clocks to read the bytes out. finally a stop condition is sent to free the bus. this case should also be used to read the chip identification number in register zero. a stop condition shall reset the radd value to 01. for examples of use, see page 59. serial mode - address none. type write. 76543210r/w iai ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ad[6:0] i2c register address, numbers in the range 0 to 63 are allowed. ad6 should be set to zero. iai high = inhibit auto increment. low = increment addresses. the iai bit and function is only available via the i2c port. when the address is incremented to 63 it stops and the bus will continue to write to or read from 'register' 63 until a stop condition is sent. since 'register' 63 does not exist, data writen to it is lost or it will read back 255.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 27 2.5. bank 0: monitor qpsk read registers. 2.5.1. id: identification register. parallel mode - bank 0-7. address 0.type read. serial mode - addresses 00, 08, 16, 24, 32, 40, 48, 56. 76543210r/w id[7:0] chip identification r id[7:0] identification: 0 = VP305/6 version. 2.5.2. int_qpsk: interrupt for qpsk block, register. these bits indicate the qpsk block event causing the interrupt signalled by the irq line going low. the irq line is reset high and the register is reset to zero when the int_qpsk register is read. the events can be masked from activating both the int_qpsk register bit and the irq line by setting the appropriate event masking bit low in the ie_qpsk (interrupt enable) register, see page 31. all bits in the ie_qpsk register should be set high. parallel mode - bank 0. address 1. type read. serial mode - address 01. 76543210 int_qpsk[7:0] int_qpsk[0] high = symbol afc lock is detected. this means that the number of clock vco cycles measured during the reference period set by sym_rp register is in the range sym_nf (register) 2 range. int_qpsk[1] high = symbol afc lock is lost. int_qpsk[2] high = carrier phase lock is detected. int_qpsk[3] high = carrier phase lock is lost. int_qpsk[4] high = carrier frequency lock is detected. int_qpsk[5] high = carrier frequency lock is lost. int_qpsk[6] high = frequency sweep has reached its lower limit. int_qpsk[7] high = frequency sweep has reached its upper limit.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 28 2.5.3. int_fec: interrupt fec register. these bits indicate the fec block event causing the interrupt signalled by the irq line going low. the irq line is reset high and the register is reset to zero when it is read. the events can be masked from activating the irq line by setting the appropriate event masking bit in the ie_fec (interrupt enable) fec register, see page 52. the masking of events does not affect the setting of the bits in the int_fec register. parallel mode - bank 0. address 2. type read. serial mode - address 02. 76543210 int_fec[7:0] int_fec[0] high = descrambler lock established. int_fec[1] high = descrambler lock is lost. int_fec[2] high = viterbi error monitor period has reached the value programmed in the vmerr[7:0] register. int_fec[3] reserved. int_fec[4] high = viterbi bit lock established. int_fec[5] high = viterbi bit lock is lost. int_fec[6] high = frame alignment lock established. (a frame is 8 blocks, each block is 204 bytes). int_fec[7] high = frame alignment lock is lost.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 29 2.5.4. status: status register. parallel mode - bank 0. addresses 3. type read. serial mode - address 03. 76543210 reserved status[6:0] the register is not reset to zero when it is read. each of these indicators can be output on the status pin by enabling the appropriate bit in the stat_en register, see page 53. status[0] high = sym_lcf, symbol afc within pull-in range. low = sym_lcf, symbol afc not within pull-in range. status[1] high = cr_lc, carrier loop in lock. low = cr_lc, carrier loop out of lock. status[2] high = cr_lcf, carrier frequency detector in lock. low = cr_lcf, carrier frequency detector out of lock. status[3] high = good snr. low = bad snr. status[4] high = descrambler lock detector in lock. low = descrambler lock detector out of lock. status[5] high = viterbi bit lock detector in lock. low = viterbi bit lock detector out of lock. status[6] high = frame align detector in lock. low = frame align detector out of lock.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 30 2.5.5. agc_lvl: agc loop voltage meter register. parallel mode - bank 0. address 4. type read. serial mode - address 04. 76543210 agc_lvl[7:0] agc loop voltage meter agc_lvl[7:0] agc loop voltage meter. the register is not reset to zero when it is read. the relationship between the loop voltage vagc and the agc_lvl register is: vagc = agc_lvl * vref / 256 the agc_out pin has an open drain buffer allowing an external vref of up to 5 volts to be used. 2.5.6. cr_vcof u & l: measured vco frequency registers. parallel mode - bank 0. addresses 5, 6. type read. serial mode - addresses 05, 06. 76543210 reserved cr_vcof[13:8] measured vco frequency (upper nibble) cr_vcof[7:0] measured vco frequency (lower byte) these two bytes together form the 14 bit number: cr_vcof[13:0] measured carrier vco frequency. the register is not reset to zero when it is read. the actual carrier frequency is found from the following formula: fvco = 32 * fcrystal cr_rp * 1024 * cr_vcof the incremental carrier step frequency is found by putting the value of cr_vcof = 1 in the equation: d fvco = 32 * fcrystal cr_rp * 1024 * 1 see page 12 for further discussion.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 31 2.5.7. ie_qpsk: interrupt enable qpsk register. when the bits of this register are set high, they enable an event to be signalled in the int_qpsk register to generate an interrupt on the irq pin. all bits should be set high, see page 27. parallel mode - bank 0. address 7. type read / write. serial mode - address 07. 76543210 ie_qpsk[7:0] interrupt enable qpsk ie_qpsk[7:0]interrupt enable qpsk. when : ie_qpsk[i] =1 : enable int_qpsk[i] ie_qpsk[i] =0 : disable int_qpsk[i] (default state) where i = 0 to 7. ie_qpsk[0] high = enable symbol afc lock detected indication in int_qpsk register. ie_qpsk[1] high = enable symbol afc lock lost indication in int_qpsk register. ie_qpsk[2] high = enable carrier phase lock detected indication in int_qpsk register. ie_qpsk[3] high = enable carrier phase lock lost indication in int_qpsk register. ie_qpsk[4] high = enable carrier frequency lock detected indication in int_qpsk register. ie_qpsk[5] high = enable carrier frequency lock lost indication in int_qpsk register ie_qpsk[6] high = enable frequency sweep has reached its lower limit indication in int_qpsk register. ie_qpsk[7] high = enable frequency sweep has reached its upper limit indication in int_qpsk register.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 32 2.6. bank 1: program qpsk registers. 2.6.1. sym_config: symbol configuration register. parallel mode - bank 1. address 1. type read / write. serial mode - address 09. 76543210 reserved sym_config[5:0] symbol configuration sym_config[1:0] sym_dr[1:0] filtered decimation ratio select. 00 = no decimation (over sampling ratio = 2) 01 = decimation by 1/2 (over sampling ratio = 4) 10 = decimation by 2/3 (over sampling ratio = 3) see also sym_ratio: input decimation factor register, page 34. sym_config[2] sym_vco _swap high = swap u and d output polarity, pins 96 and 97. low = normal sym_config[3] sym_lcf _supp high = suppress timing error detector. low = normal sym_config[4] sym_vco u/d high = tri-state d and u outputs. low = active outputs. sym_config[5] reserved set low. sym_config[6] reserved set low. sym_config[7] reserved set low.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 33 2.6.2. sym_rp: symbol afc reference period register. parallel mode - bank 1. address 2. type read / write. serial mode - address 10. 76543210 reserved sym_rp[3:0] symbol afc reference period sym_rp[3:0] symbol frequency reference period for the count of the crystal clock cycles ( xti pin). this sets the reference for the measurement of the adc vco frequency (sys_clk pin). the register value sets the 4 most significant bits of a 14 bit counter. the actual count is sym_rp[3:0] * 1024. 2.6.3. sym_nf u & l: symbol input nominal frequency registers. parallel mode - bank 1. addresses 3, 4. type read / write. serial mode - addresses 11, 12. 76543210 sym_nf[15:8] symbol input nominal frequency (upper byte) sym_nf[7:0] symbol input nominal frequency (lower byte) these two bytes together form the 16 bit number: sym_nf[15:0] symbol input nominal frequency. this is the division ratio for the symbol clock input from the adc vco.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 34 2.6.4. sym_ratio: symbol input decimation factor register. parallel mode - bank 1. address 5. type read / write. serial mode - address 13. 76543210 reserved sym_ratio[2:0] sym_ratio[2:0] input decimation factor for iin and qin inputs, no filtering. sym_ratio[2:0] decimation factor 0 no decimation 1 input every second sample 2 input every fourth sample 3 input every eighth sample 4 input every sixteenth sample 5 to 7 reserved 2.6.5. agc_ref: reference agc level registers. parallel mode - bank 1. address 6. type read / write. serial mode - address 14. 76543210 agc_ref[7:0] reference agc level agc_ref[7:0] reference agc level sets the ratio of the input signal range (s) to the adc range (r). the objective is to maintain this a constant ratio (s : r = 1 : 1.7). 0.0 0.3 0.5 -0.5 -0.3 s=0.6v input signal level -t/2 0 t/2 volts t = symbol period input signal level r=1v adc input range fig. 12. eye diagram. the agc_ref value is found from the following formula:
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 35 agc_ref = 233.3 * l * s 2 r 2 where: s = signal peak-to-peak level at the adc input r = input range of the adc. l = 1 for no filtered decimation, sym_config[1:0] = 0 or l = 4 for some filtered decimation, sym_config[1:0] = 1 or 2, (this adds 6db gain) therefore: for l = 1 agc_ref = 233.3 * 1 * 0.6 2 1 2 = 84. for l = 4 agc_ref = 233.3 * 4 * 0.3 2 1 2 = 84. 2.6.6. agc_bw: agc estimation bandwidth register. parallel mode - bank 1. address 7. type read / write. serial mode - address 15. 76543210 reserved int_dc agc_bw[1:0] agc_bw[1:0] agc estimation bandwidth. agc_bw[1:0] symbol rate rs msym/s 0>20 1 10 - 20 25 - 10 3 reserved the agc control signal drives the sigma delta modulated output agc_out pin. this output can drive an external passive rc filter feeding the agc stage. the rc time constant should be <63.6s. int_dc internal dc offset. high = enable internal dc offset compensation on i and q channels. low = disable internal dc offset compensation on i and q channels.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 36 2.7. bank 2: program qpsk registers. 2.7.1. scale: iout and qout outputs, scale factor register. parallel mode - bank 2. address 1. type read / write. serial mode - address 17. 76543210 scale[7:0] scale factor for iout and qout outputs scale[7:0] scale factor for iout and qout outputs. the value in the scale register adjusts the matched filter outputs before the signal is truncated to 3 bits. these signals are output from the qpsk block and fed direct to the viterbi block. for an agc_ref setting of 84, the scale value is recommended to be set to 158. 2.7.2. snr_ths: signal to noise ratio estimator threshold register. parallel mode - bank 2. address 2. type read / write. serial mode - address 18. 76543210 snr_ths[7:0] snr estimator threshold snr_ths[7:0] snr estimator threshold. the snr is compared internally to the value set in the snr_ths register. fig 14 on page 38 shows the relationship between the parameter and the symbol energy to noise power ratio (es / no). a value for snr_ths of 100 which corresponds to an es / no of 11dbs is recommended during tracking mode. after acquisition is complete, set the snr_ths value to zero. es / no (db) 0 50 100 150 200 250 agc_ref = 84 fig. 13 snr threshold vs. es / no.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 37 2.7.3. cr_offset: carrier loop dc offset register. parallel mode - bank 2. address 3. type read / write. serial mode - address 19. 76543210 cr_offset[7:0] carrier loop dc offset compensation value cr_offset[7:0] carrier loop dc offset compensation value. this is used to suppress internal dc offsets on the i and q channels. this feature is only enabled when the carrier loop is closed, cr_open bit must be set low in the cr_config register, see page 44. the cr_offset[7:0] value is a signed integer in the range -128 to +127. because of imperfections in the analog components in the loop filter, it is possible that the loop voltage shows a dc offset. this can have the following consequences: - during the acquisition phase, the frequency sweeping becomes asymmetric. the dc offset causes the sweep to slow down in one direction and speed up in the other direction. if sweeping is too slow, false locks can occur in high signal to noise ratio conditions. if sweeping is too fast, true locks can be missed in low signal to noise ratio conditions. - during the tracking phase, the static error of the loop is not a minimum, since the dc offset generates a frequency ramp that the loop has to compensate for. the following figure shows the effect the cr_offset value can have on the carrier sweep. the graph indicates a cross-over point at about -18 when t rise = t fall . moving cr_offset more negative lengthenes the t rise and shortens the t fall and visa versa.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 38 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 -140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 cr_offset time ms t rise t fall vp 305/6 carrier s weep function. fig. 14 carrier sweep rise and fall times vs. cr_offset.. 2.7.3.1. acquisition phase. to calculate the dc offset value required, the period of each ramp should be measured and used in the following formula: cr_offset = cr_swr 2 * tdwn - tup tdwn + tup where: tup = the ramp up time tdown = the ramp down time
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 39 the choice depends on the polarity of the vco u/d signals. select + if polarity is normal or - if polarity is swapped (inverted). this is set by the cr_config[6] bit, see page 44. the ramp times can be measured by observing the time intervals between the setting of interrupts int_qpsk[6] and int_qpsk[7]. these interrupts are generated when the lower and upper frequency limits are reached respectively, see page 27. the relationship between the offset voltage and the cr_offset parameter is as follows: voffset = cr_offset 32 * cr_kp * vdd see above for choice of . 2.7.3.2. tracking phase. during the tracking phase, the mean value of the phase error should be zero. the mean value is internally computed and subtracted from the phase error before the sigma-delta conversion. this system is only operational in the tracking mode, set by cr_config[1] = 0, see page 44. the maximum dc offset voltage which can be compensated by this method is: voffset_max = + cr_offset 32 * cr_kp * vdd e.g. for vdd = 3.3v, cr_offset = 127 for cr_kp = 255, voffset_max = 51mv (resolution 0.4mv) for cr_kp = 30, voffset_max = 437mv (resolution 3.4mv) 2.7.4. cr_rp: carrier reference period register. parallel mode - bank 2. address 4. type read / write. serial mode - address 20. 76543210 reserved cr_rp[3:0] carrier reference period cr_rp[3:0] carrier frequency reference period for the count of the crystal clock cycles ( xti pin). this sets the reference for the measurement of the i/q down converter vco frequency (pscal pins). the register value sets the 4 most significant bits of a 14 bit counter. the actual count is cr_rp[3:0] * 1024. see page 12 for further discussion.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 40 2.7.5. cr_kp: carrier loop filter gain (p term) register. parallel mode - bank 2. address 5. type read / write. serial mode - address 21. 76543210 cr_kp[7:0] carrier loop filter gain (p term) cr_kp[7:0] carrier loop filter gain (p term) this term, cr_kp * 2 determines the resolution of the sigma delta conversion. it should be >30 for six bits of resolution. es / no (db) 0 5 10 15 20 25 30 35 40 45 0db 2db 4db 6db 8db 10db 12db 14db 16db 18db 20db ddml bps k ddml qps k ndaml qps k fig. 15. carrier phase error detector gain kd_cr vs. es / no for agc_ref = 84. 2.7.6. cr_kd: carrier loop filter gain (d term) register. parallel mode - bank 2. address 6. type read / write. serial mode - address 22. 76543210 cr_kd[7:0] carrier loop filter gain (d term) cr_kd[7:0] carrier loop filter gain (d term) the loop damping factor is given by the following equation: z = 2 * cr_kd * w n rs where w n = natural frequency in radians / second rs = qpsk symbol rate.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 41 therefore cr_kd = z * rs 2 * w n 2.7.7. cr_thsl: carrier lock detector threshold register. parallel mode - bank 2. address 7. type read / write. serial mode - address 23. 76543210 cr_thsl[7:0] carrier lock detector threshold cr_thsl[7:0] carrier lock detector threshold. this should be set to correspond to the phase lock detector length set by bit 4 of the config register, see page 45. config[4] cr_thsl 031 172
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 42 2.8. bank 3: program qpsk registers. 2.8.1. cr_swr: carrier sweep rate register. parallel mode - bank 3. address 1. type read / write. serial mode - address 25. 76543210 cr_swr[7:0] carrier sweep rate cr_swr[7:0] carrier sweep rate. cr_swp = 64 * k dcr * q where: k dcr is the carrier phase detector gain, typically 10 for low eb / no of 4 db. q is the phase lock loop steady state error during acquisition. q should be lower than 5 expressed in radians. during the tracking phase, the loop drives the residual steady state error to 0. therefore, if k dcr = 10 and q = 3 = 0.052rad. cr_swp = 64 * 10 * 0.052 = 33 (rounded down). the frequency sweep rate is given by the following formula: f = 5 * cr_swp 128 * p *cr_kp * k vcocr r cr * c cr * vdd 5v hz/s for the sl1710 k vcocr = 11.56mrad/s/v. for vdd = 3.3v therefore f = 5 * 33 * 11.56 * 10 6 * 3.3 128 * p * cr_kp * r cr * c cr * 5 = 3.13 * 10 6 cr_kp * r cr * c cr
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 43 the sweep rate varies as a function of the value of cr_swr register and the delta frequency, effectively selected by the cr_uswl and cr_lswl registers. if the delta frequency is halved, the sweep rate doubles. if the receiver fails to lock, a higher value of cr_swr should be tried. if the value of cr_swr is too low, the frequency sweep may be stopped. the rise and fall times of the sweep can be adjusted to be equal by setting the value of cr_offset, see page 37. this becomes more critical at very low values of cr_swr where the sweep will stop unless the rise and fall times are equal. cr _ s w r 0 2 4 6 8 10 12 14 16 20 40 60 80 100 120 140 160 180 200 220 240 260 vp 305/6 carrier s weep function. fig. 16. carrier sweep rate for a delta frequency of 10mhz. 2.8.2. cr_uswl u & l: carrier upper sweep limit registers. parallel mode - bank 3. addresses 2, 3. type read / write. serial mode - addresses 26, 27. 76543210 reserved cr_uswl[13:8] carrier upper sweep limit (upper nibble) cr_uswl[7:0] carrier upper sweep limit (lower byte) these two bytes together form the 14 bit number: cr_uswl[13:0] carrier upper sweep limit. this is the division ratio (upper) for the prescaler input (pscal) from the sl1710. see page 12 for further discussion.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 44 2.8.3. cr_lswl u & l: carrier lower sweep limit registers. parallel mode - bank 3. addresses 4, 5. type read / write. serial mode - addresses 28, 28. 76543210 reserved cr_lswl[13:8] carrier lower sweep limit (upper nibble) cr_lswl[7:0] carrier lower sweep limit (lower byte) these two bytes together form the 14 bit number: cr_lswl[13:0] carrier lower sweep limit. this is the division ratio (lower) for the prescaler input (pscal) from the sl1710. 2.8.4. cr_config: carrier configuration register. parallel mode - bank 3. address 6. type read / write. serial mode - address 30. 76543210 cr_config[7:0] carrier configuration cr_config[0] cr_sw high = carrier loop sweep on. low = carrier loop sweep off. cr_config[1] cr_open high = carrier loop open. this is only used to get out of a false lock. low = carrier loop closed. cr_config[2] cr_ped_sel carrier phase error detector select. high = ndaml non-data aided maximum likelihood estimator (only available in qpsk mode). low = ddml decision directed maximum likelihood estimator. cr_config[3] reserved set low. cr_config[4] cr_vco1 d/u high = tri-state d and u outputs. low = active outputs. cr_config[5] cr_vco2 d/u high = tri-state d and u outputs. low = active outputs. cr_config[6] cr_vco_swap exchange polarity for both cr_vco1 and cr_vco2 d and u outputs. high = swapped (i.e. d and u inverted). low = normal.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 45 cr_config[7] cr_sweep_swap change carrier sweep direction. high = swapped. low = normal. 2.8.5. config: configuration register. parallel mode - bank 3. address 7. type read / write. serial mode - address 31. 76543210 config[7:0] config[0] iin and qin input format selector. high = 2's complement format. low = offset binary format. this is the normal format used with the vp216/7. code for six bit input offset binary offset 2's complement config[0] = 0 config[0] = 1 00 000000 100000 01 000001 100001 31 011111 111111 32 100000 000000 33 100001 000001 62 111110 011110 63 111111 011111 config[1] reserved set low. config[2] reserved set high. config[3] agc out. high = inverted. low = normal. config[4] fp_lock_len : frequency / phase lock detector length. high = short. low = normal - long. see also cr_thsl register on page 41. config[5] reserved set low.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 46 config[6] constellation selector. high = bpsk. low = qpsk.. config[7] snr estimator on/off. high = used. low = off. 2.9. bank 4: monitor fec read registers. 2.9.1. vit_err_c h & l: viterbi error count registers. parallel mode - bank 4. addresses 1, 2. type read. serial mode - addresses 33, 34. 76543210 verrc[15:8] - viterbi error count high byte verrc[7:0] - viterbi error count low byte these two bytes together form the 16 bit number: verrc[15:0] viterbi error count related to the period defined in the vit_err h-m-l registers, see page 48. when the count increments to the maximum value, it freezes at 65535. the actual count = 4 x verrc[15:0] data bits. the register is not reset to zero when it is read. see also figure 8 on page 15. 2.9.2. rs_ubc: reed solomon uncorrected block count register. parallel mode - bank 4. address 3. type read. serial mode - address 35. 76543210 rsubc[7:0] - reed solomon uncorrected block count rsubc[7:0] reed solomon uncorrected block count. when the count increments to the maximum value, it freezes at 255. the register is reset to zero when it is read.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 47 2.10. bank 5: program fec registers. 2.10.1. vit_mode: viterbi mode register. parallel mode - bank 5. address 1 type read / write. serial mode - address 41. 76543210 iqswap f_lock reserved vitcr[2:0] - code rate vitcr[2:0] viterbi code rate vitcr[2:0] code rate 01/2 12/3 23/4 35/6 47/8 51/2 61/2 71/2 f_lock false lock high = exit false lock state. this is automatically set low after use. low = normal. see section 2.10.5 on page 49 for an explanation on how to use this bit. iqswap i / q swap high = i lags q. low = i leads q.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 48 2.10.2. vit_err h, m & l: viterbi error period registers. parallel mode - bank 5. addresses 2, 3, 4. type read / write. serial mode - addresses 42, 43, 44. 76543210 vitep[23:16] - viterbi error period high byte vitep[15:8] - viterbi error period middle byte vitep[7:0] - viterbi error period low byte these three bytes together form the 24 bit number: vitep[23:0] viterbi error period, effectively the number of valid data bits, during which an error count is accumulated. at the end of the defined period, the error count is frozen and that value stored in the vit_err_c h-l registers, see page 46. also at the end of the defined period, an interrupt is generated on the irq line to advise the microprocessor that a new error count is available to be read. the interrupt is enabled by setting the ie_fec[2] bit in the ie_fec register, see page 52. the actual period = 4 x vitep[23:0] data bits. see also figure 8 on page 15. 2.10.3. vi_max_err: viterbi maximum bit error count register. parallel mode - bank 5. address 5. type read / write. serial mode - address 45. 76543210 vmerr[7:0] - viterbi max. bit error count vmerr[7:0] viterbi maximum bit error count. when the coarse count reaches the number programmed in vmerr[7:0], the count is reset to zero and an interrupt is generated on the verr line (provided the intvis bit is enabled in the test2 register, see page 56). this technique provides a visible indication of the frequency of bit errors in the signal. it may be used, via a suitable monitor device, to assist in receiver dish alignment. the actual count = 4 x vmerr[7:0] data bits. see also figure 9 on page 16.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 49 2.10.4. vi_ber_per: viterbi bit error rate based synchronisation period register. parallel mode - bank 5. address 6. type read / write. serial mode - address 46. 76543210 vbper[7:0] - viterbi bit error rate based synchronisation period vbper[7:0] viterbi bit error rate based synchronisation period. the actual period = 256 x vbper[7:0] data bits. 2.10.5. vi_ber_lim: viterbi bit error rate based synchronisation limit register. parallel mode - bank 5. address 7. type read / write. serial mode - address 47. 76543210 vblim[7:0] - viterbi bit error rate based synchronisation limit vblim[7:0] viterbi bit error rate based synchronisation limit. the actual limit = 128 x vblim[7:0] + 32 data bits. the viterbi bit error rate threshold is the ratio of the register values: threshold = vi_ber_lim / vi_ber_per the following table shows recommended threshold values for the various viterbi code rates. if the viterbi bit error rate threshold is set too low, the viterbi circuit will lock up on incorrect data. but conversely, if the threshold is set too high, the viterbi circuit will have difficulty in llocking up. a false lock may be exited by toggling f_lock (bit 6 of vit_mode register, see page 47). coding rate min. max. 1/2 0.090 0.120 2/3 0.055 0.070 3/4 0.035 0.050 5/6 0.020 0.035 7/8 0.010 0.025 table 9. viterbi bit error rate threshold. .
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 50 2.11. bank 6: program fec and general control registers. 2.11.1. vit_ctrl1: viterbi control synchronisation byte register 1 parallel mode - bank 6. address 1. type read / write. serial mode - address 49. 76543210 bs_mode[1:0] vs_unlk[3:0] vbit_mv[1:0] vbit_mv[1:0]viterbi synchronisation majority voting selection for the number of correct bits in a byte to have the byte labelled as a synchronisation byte. vbit_mv[1:0] no. correct bits in sync 05 16 ? recommended 27 38 table 10. number of correct bits in the sync byte . vs_unlk[3:0] viterbi sync majority voting selection for retaining sync lock. vit_ctrl1 (weighted) vs_unlk[3:0] no. syncs to keep lock 003 414 825 12 3 6 16 4 7 ? recommended 20 5 8 24 6 9 28710 32811 36912 40 10 13 44 11 14 48 12 15 52 13 16 56 14 17 60 15 18 table 11. number of correct sync bytes to retain lock .
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 51 bs_mode[0] byte sync mode bit 0 high = seeking lock low = normal bs_mode[1] byte sync mode bit 1 high = remaining in lock low = normal 2.11.2. vit_ctrl2: viterbi control synchronisation byte register 2 parallel mode - bank 6. address 2. type read / write. serial mode - address 50. 76543210 vit_ctrl2[7:3] - reserved vs_lk[2:0] vs_lk[2:0] viterbi synchronisation acquire. this defines the number of consecutive synchronisation bytes that need to be detected before block lock is established. vs_lk[2:0] no. syncs for lock 02 13 24 35 ? recommended 46 57 6 not valid 7 not valid table 12. number of consecutive sync bytes to establish block lock . vit_ctrl2[7:3] these bits are reserved for test applications. for normal operation, they must be set to zero.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 52 2.11.3. ie_fec: interrupt fec register. when the bits of this register are set high, they enable an event signalled in the int_fec register to generate an interrupt on the irq pin. they do not affect the setting of bits in the int_fec register, see page 28. parallel mode - bank 6. address 3. type read / write. serial mode - address 51. 76543210 ie_fec[7:0] interrupt enable fec ie_fec[7:0] interrupt enable fec when : ie_fec[i] =1 : enable int_fec[i] ie_fec[i] =0 : disable int_fec[i] (default state) where i = 0 to 7. ie_fec[0] high = enable descrambler lock established indication in int_fec register. ie_fec[1] high = enable descrambler lock lost indication in int_fec register. ie_fec[2] high = enable viterbi error period indication in int_fec register. ie_fec[3] reserved set low. ie_fec[4] high = enable viterbi bit lock established indication in int_fec register. ie_fec[5] high = enable viterbi bit lock lost indication in int_fec register. ie_fec[6] high = enable frame alignment lock established indication in int_fec register. (a frame is 8 blocks, each block is 204 bytes). ie_fec[7] high = enable frame alignment lock lost indication in int_fec register.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 53 2.11.4. stat_en: status enable register. parallel mode - bank 6. address 4. type read / write. serial mode - address 52. 76543210 stat_en[7:0] enable various outputs on status pin. this register allows various indicator signals to be output on the status pin. the signals are equivalent to the corresponding bits in the status register, see page 29, or to events signalled in the int_fec register, see page 28. note: only one bit should be programmed high at any one time, otherwise a meaningless output on the status pin will result! stat_en[0] high = enable symbol afc lock detect signal on the status pin. stat_en[1] high = enable carrier phase lock detect signal on the status pin. stat_en[2] high = enable carrier frequency lock detect signal on the status pin. stat_en[3] high = enable snr quality signal on the status pin. stat_en[4] high = enable descrambler lock detect signal on the status pin. stat_en[5] high = enable viterbi bit lock detect signal on the status pin. stat_en[6] high = enable frame alignment lock detect signal on the status pin. stat_en[7] high = enable symbol clock signal on the status pin.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 54 2.11.5. gen_ctrl: general control register. parallel mode - bank 6. address 5. type read / write. serial mode - address 53. 76543210 - - - mclkinv bso entei nsync[1:0] nsync[1:0] the number of successive incorrect synchronising bytes in n successive blocks before byte lock in the descrambler is lost. the value programmed is related to n as shown in the following truth table. nsync[1:0] no. incorrect sync bytes 02 13 ? recommended 24 35 table 13. number of incorrect sync bytes for descrambler to lose lock . entei high = enable automatic setting of transport_error_indicator (tei) bit in the mpeg packet header byte 2 when the block contains an uncorrectable byte error. bso high = bit serial output of the mpeg data on mdo0 pin. mclkinv high = mclk clock output inverted. low = mclk clock output normal. 2.11.6. gpp_ctrl: general purpose port control register. parallel mode - bank 6. address 6. type read / write. serial mode - address 54. 7654321 0 reserved gpp_ctrl[4:1] external outputs control. gpp_ctrl[0] gpp_ctrl[i] bit drives the output pin gpp[i] where i = 1, 2, 3 or 4. note: gpp_ctrl[0] reads the logic level of the input pin gpp0. writing to this bit has no effect.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 55 2.11.7. reset: reset register. parallel mode - bank 6. address 7. type read / write. serial mode - address 55. 76543210 res - - - pr_ds pr_bs fr_qp pr_qp pr_qp high = partial reset of the qpsk block, except for the registers. low = no reset. fr_qp high = full reset of the qpsk block, including the registers. low = no reset. pr_bs high = partial reset of the byte synchronising mechanism. low = no reset. pr_ds high = partial reset of the de scramble block with its synchronising function. low = no reset. res high = reset the complete chip, except for the microprocessor interface, to its default state. low = no reset.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 56 2.12. bank 7: program test registers. 2.12.1. test1: test 1 register - for diagnostic / qualification purposes only. parallel mode - bank 7. address 1. type read / write. serial mode - address 57. 76543210 reserved test1[7:0] set all bits low for normal operation. 2.12.2. test2: test 2 register - for diagnostic / qualification purposes only. parallel mode - bank 7. address 2. type read / write. serial mode - address 58. 76543210 intvis - - - en[3:0] en[3:0] enable / disable functions en3,2,1,0 qpsk viterbi deint rs descr 0 enenenenen ? default state 3 en en dis dis dis ? test viterbi output all other states reserved. table 14. enable / disable circuit blocks. in the mode 3, digitised i and q data is input in the normal way to the qpsk decoder block. the output from the viterbi block is then connected directly to the mdo7:0 pins, bypassing the remaining blocks. intvis high = enable the toggled verr output when vmerr (viterbi max. error count) is reset. see also figure 9 on page 16. this is the mode to assist in aligning the satellite dish. low = verr pin held low.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 57 2.12.3. test3: test 3 register - for diagnostic / qualification purposes only. parallel mode - bank 7. address 3. type read / write. serial mode - address 59. 76543210 reserved test3[7:0] set all bits low for normal operation.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 58 3. microprocessor control. selection of the microprocessor interface type is controlled by the ser pin. ser interface type 0 i2c bus interface 1 parallel interface 3.1. i2c bus interface. not available on VP305. the i2c bus serial interface (ref. 2.) uses pins: sda serial data, the most significant bit is sent first. scl serial clock (d0). the i2c bus address is 0001 110 r/ w . the circuit works as a slave transmitter with the eighth bit set high or as a slave receiver with the eighth bit set low. in receive mode, the first data byte is written to radd register, which forms the register sub-address. bit 7 of the radd register, iai is an increment auto inhibit function. when the iai bit is set high, the automatic incrementing of register addresses is inhibited. iai set low is the normal situation so that data bytes sent on the i2c bus after the radd register data are loaded into successive registers. this automatic incrementing feature avoids the need to individually address each register. following a valid chip address, the i2c bus stop command resets the radd register to 01. if the chip address is not recognised, the vp306 will ignore all activity until a valid chip address is received. the i2c bus start command does not reset the radd register to 01. this allows a combined i2c bus message, to point to a particular read register with a write command, followed immediately with a read data command. if required, this could next be followed with a write command to continue from the latest address. radd would not be sent in this case. finally a stop command should be sent to free the bus. when the i2c bus is addressed (after a recognised stop command) with the read bit set, the first byte read out shall be the content of register 01. to access the chip identification in register 00, the microprocessor should send the chip address with the write bit set, followed by the register address 00, then a restart with the read bit set, followed by a data read.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 59 3.1.1. examples of i2c bus messages: key: s start condition w write (= 0) p stop condition r read (= 1) a acknowledge na not acknowledge italics VP305/6 output write operation - as a slave receiver. s device w a radd a data a data a p address (n) (reg n) (reg n+1) read operation - VP305/6 as a slave transmitter. s device r a data a data a data na p address (reg 1) (reg 2) (reg 3) write/read operation with repeated start - VP305/6 as a slave transmitter. s device w a radd a s device r a data a data na p address (n) address (reg n) (reg n+1) write/read/write operation with repeated start and auto increment off with iai set high - VP305/6 as a slave transmitter. this example uses the gpp_ctrl register which has a read bit 0 and write bits 1 to 4. register address is 54 + 128 (iai). s device w a radd a s device r a data na s device w a data a p address (182) address (reg 54 ) address (reg 54) note: the serial register map is not continuous. the increment function will address the non- used addresses, so when writing a sequence of data, dummy data will need to be inserted at the appropriate points for the non-used addresses. similarly, when reading a sequence of data, the value 255 will be read out from the non-used addresses.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 60 3.2. parallel interface. the parallel interface is selected by a logic '1' on the ser pin. this uses pins: d7-0 data input/output bus a2-0 address input bus cs chip select as address select dtak data acknowledge r/ w read / write control registers are directly addressed via the address bus. there is no register incrementing feature as on the i2c bus interface. 3.2.1. examples of writing to and reading from the parallel interface. to write the value 64 to the config register 7 in bank 3, send the following sequence: set r/ w to write addr[0],data[24] this writes 24 (bank 3) to the bank register addr[7],data[64] this writes 64 to register 7 (of bank 3) (config) to read the value of the rs_ubc register 3 in bank 4, send the following sequence: set r/ w to write addr[0],data[32] this writes 32 (bank 4) to the bank register set r/ w to read addr[3],data[?]. this reads register 3 (of bank 4) (rs_ubc) it is not necessary to write the value of the bank register if writing to / or reading from a group of registers in the same bank. for example, to read the registers 1 to 6 of bank 0: set r/ w to write addr[0],data[0] this writes 0 to the bank register set r/ w to read addr[1],data[?]. this reads register 1 (of bank 0) (int_qpsk) addr[2],data[?]. this reads register 2 (of bank 0) (int_fec) addr[3],data[?]. this reads register 3 (of bank 0) (status) addr[4],data[?]. this reads register 4 (of bank 0) (agc_lvl) addr[5],data[?]. this reads register 5 (of bank 0) (cr_vcof u) addr[6],data[?]. this reads register 6 (of bank 0) (cr_vcof l) 3.2.2. parallel interface write cycle description. a write cycle starts with the master indicating its intent by setting r/ w to write and placing a valid address on a2:0 and asserting as . the VP305/6 takes the assertion of as as the start of a cycle and latches the address on a2:0 by the falling edge as . this event also causes VP305/6 to respond to the request by the master to send data, when it can, by asserting dtack . the
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 61 master requests to send data by asserting cs , data may be placed on the data bus before or after asserting cs . notice that there is no maximum time specified from the assertion of as to the assertion of dtack . it is assumed that the master will insert wait states/cycles until dtack is recognised. when the master negates cs the VP305/6 will latch the data on d7:0 on the rising edge of cs . when the master negates cs the VP305/6 will then negate dtack . valid valid a2:0 r/w as cs dtack d7:0 fig. 17. parallel interface write cycle action diagram .
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 62 write cycle flowchart. bus master VP305/6 address the VP305/6 set r/w to write place address on a2:0 assert address strobe place data on d7:0 assert chip select ? receive the address latch/decode the address assert data transfer acknowledge transfer the data de-assert chip select ? acquire the data store data on d7:0 terminate the cycle de-assert address strobe remove data from d7:0 set r/w to read ? terminate the cycle de-assert data transfer acknowledge start next cycle
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 63 3.2.3. parallel interface read cycle description. a read cycle starts with the master indicating its intent by setting r/ w to read and placing a valid address on a2:0 and asserting as . the VP305/6 takes the assertion of as as the start of a cycle and latches the address on a2:0 by the falling edge as . this event also causes VP305/6 to respond to the data request, when it can, by placing valid data on the data bus and asserting dtack , informing the master that it may proceed. the master then requests data by asserting cs . notice that there is no maximum time specified from the assertion of as to the assertion of dtack . it is assumed that the master will insert wait states/cycles until dtack is recognised. the master will then read the data on d7:0 and negate cs and as . the negation of cs causes the VP305/6 to remove the data from d7:0 and then negate dtack . valid valid a2:0 r/w as cs dtack d7:0 fig. 18. parallel interface read cycle action diagram .
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 64 read cycle flowchart. bus master VP305/6 address the VP305/6 set r/w to read place address on a2:0 assert address strobe assert chip select ? output the data latch/decode the address place data on d7:0 assert data transfer acknowledge acquire the data latch data de-assert chip select de-assert address strobe ? terminate the cycle remove data from d7:0 de-assert data transfer acknowledge start next cycle
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 65 4. timing information. 4.1. i2c bus timing. p s sr p low t t r t hd;sta hd;dat t t f high t t su;dat su;sta t sda scl t buff t su;sto fig. 19. i2c bus timing. where: s = start sr = restart, i.e. start without stopping first. p = stop. parameter symbol value unit min max. scl clock frequency f scl 0 450 khz bus free time between a stop and start condition. t buff 200 ns hold time (repeated) start condition. t hd;sta 200 ns low period of scl clock. t low 450 ns high period of scl clock. t high 600 ns set-up time for a repeated start condition. t su;sta 200 ns data hold time (when input). t hd;dat 100 ns data set-up time t su;dat 100 ns rise time of both scl and sda signals. t r note 1 ns rise time of both scl and sda signals, (100pf to ground). t f 20 ns set-up time for a stop condition. t su;sto 200 ns table 15. i2c bus timing . note 1. the rise time depends on the external bus pull up resistor.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 66 4.2. parallel interface write cycle timing. valid valid a2:0 r/w as cs dtack d7:0 avasl asdtl t t t wvasl dvcsh t cshdi t cshai t ashwi t cshdth t fig. 20. parallel interface write cycle timing diagram. 4.3. parallel interface read cycle timing. valid valid a2:0 r/w as cs dtack d7:0 avasl asdtl t t t rvasl dvcsh t cshdi t ashdi t ashri t cshdth t fig. 21. parallel interface read cycle timing diagram .
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 67 symbol characteristic min. max. units t avasl address valid to address strobe low ns t rvasl read valid to address strobe low ns t wvasl write valid to address strobe low ns t ashdth address strobe high to dtack high ns t asldtl address strobe low to dtack low ns t dvcsh data valid to chip select high ns t cshai chip select high to address invalid ns t ashri address strobe high to read invalid ns t ashwi address strobe high to write invalid ns t cshtdh chip select high to dtack high ns t cshdi chip select high to data invalid ns table 16. parallel bus timing . 4.4. data input timing. sys_clk iin qin id t fig. 22. VP305/6 data input timing diagram . parameter symbol min. typ. max. units data intput delay t id 2.0 6.0 ns
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 68 5. mpeg packet data output. 5.1. data output format. tei 01000111 1st byte 2nd byte transport packet header 4 bytes 184 transport packet bytes 188 byte packet output mdo[7] mdo[0] fig. 23. VP305/6 transport packet header bytes . after decoding, the 188 byte mpeg packet is output on the mdo pins in 188 consecutive clock cycles. additionally, when the entei bit in the gen_ctrl register is set high, any decoded packets with uncorrectable bytes will automatically set the tei bit in the mpeg header, see page 54.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 69 mdo7:0 mclk mostrt moval bkerr tp ti 1st byte packet n 188th byte packet n 1st byte packet n+1 fig. 24. VP305/6 output data wave form diagram. mclk will be a continuously running clock once symbol lock has been achieved in the qpsk block and is derived from the symbol clock. mclk is the output interface byte rate clock, running at a rate given by the table on page 70. the maximum jitter in the packet synchronisation byte is limited to one output clock period. all output data and signals (mdo7:0, mostrt, moval, bkerr ) change on the negative edge of mclk to present stable data and signals on the positive edge of the clock. a complete packet of data is output on mdo7:0 on 188 consecutive clocks and the mdo7:0 pins will remain low during the inter packet gaps. mostrt goes high for the first byte clock of a packet. moval will go high on the first byte of a packet and remain high until the 188 th byte has been clocked out. bkerr will go low on the first byte of a packet where uncorrectable bytes are detected and remain low until the 188 th byte has been clocked out. tp is equivalent to 188 clock cycles irrespective of the code rate. ti depends on the inner code rate (1/2, 2/3, 3/4, 5/6 or 7/8). the following table shows data output timing and an example of the data rate on mdo7:0 for a maximum input symbol rate (rs) of 30msym/sec.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 70 viterbi code rate t clkp s t clkh s t clkl s e.g. mdo7:0 mbyte/sec 1/2 16/2rs 8/2rs 8/2rs 3.7500 2/3 12/2rs 6/2rs 6/2rs 5.0000 3/4 11/2rs 6.2rs 5/2rs 5.4545 5/6 10/2rs 5/2rs 5/2rs 6.0000 7/8 9/2rs 5/2rs 4/2rs 6.6667 table 17. mpeg data output rates . the viterbi code rate is programmed in the vit_mode register, see page 47. 5.2. data output timing. clkl t mcl k mos t r t moval mdo7:0 bkerr od t clkp t fig. 25. VP305/6 data output timing diagram. parameter symbol min. typ. max. units data output delay t od 20 ns
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 71 6. VP305/6 operating conditions. 6.1. recommended operating conditions. parameter symbol min. typ. max. units power supply voltage v dd 2.97 3.30 3.63 v power supply current i dd 410 ma input clock frequency 1 xti 9.99 16.00 mhz pscal input frequency pscal 15.00 25.00 mhz sytem clock input frequency sys_clk 60.00 mhz scl clock frequency f scl 450 khz ambient operating temperature 0 70 c table 18. recommended operating conditions . note 1. when not using a crystal, xti may be driven from an external source over the frequency range shown.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 72 6.2. electrical characteristics. test conditions (unless otherwise stated): as specified in recommended operating conditions. dc characteristics parameter conditions symbol min. typ. max. units digital inputs cmos compatible input high voltage v ih 0.8v dd 5.5 v input low voltage v il 0.2v dd v digital inputs ttl compatible input high voltage v ih 2.0 5.5 v input low voltage v il 0.8 v leakage current - all inputs except test1,2,3, xti input high v in = 5.5v i ih 110a input low v in = v ss i il 1-10a leakage current - test1,2,3, xti input high v in = 3.63v i ih 110a input low v in = v ss i il 1-10a digital outputs cmos compatible output high voltage i oh = -1ma v oh 0.8v dd v output low voltage i ol = +1ma v ol 0.4 v digital outputs open drain output high voltage v oh 5.5 v output low voltage i ol = +6ma v ol 0.4 v pecl inputs common mode input range @ v dd v ir v dd -1.9 v dd -0.4 v input voltage swing v is 250 mv table 19. dc characteristics.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 73 6.3. crystal specification. parallel resonant fundamental frequency (preferred) 9.99 to 16.00mhz. tolerance over operating temperature range 25ppm. tolerance overall 50ppm. nominal load capacitance 30pf. equivalent series resistance <35 w 33pf 33pf xti xto gnd fig. 26. crystal oscillator circuit. 6.4. absolute maximum ratings. supply voltage -03v to +3.63v all 5v compatible inputs -03v to 5v+03vv dd all 3.3v compatible inputs -03v to v dd +03v operating temperature 0c to +70c storage temperature -65c to 150c note: stresses exceeding these listed under absolute maximum ratings may induce failure. exposure to absolute maximum ratings for extended periods may reduce reliability. functionality at or above these conditions is not implied.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 74 6.5. pinout description. pin no name pin description i/o note v ma 1 ser a logic 1 selects the 8 bit interface, a logic 0 selects i2c interface. not connected on VP305. icmos5 4 pscal input from sl1710 (differential prescaler true output). i pecl d 1 5 pscal input from sl1710 (differential prescaler inverted output). i pecl d 1 6-11 iin5:0 in phase data input from the adc digitiser. i ttl 5 14-19 qin5:0 quadrature phase data input from the adc digitiser. input format is selected by bit config[0]. i ttl 5 22 sys_clk system clock input. i ttl 5 23 as address select strobe. the address on pins a2:0 is latched on the negative going edge. icmos5 24 cs chip select for the microprocessor interface, a logic 0 makes the interface active. data on pins d7:0 is latched on the positive going edge. icmos5 25-27 a2:0 address pins for the internal registers used with the 8 bit interface. icmos5 30 dtack data acknowledge. a logic 0 indicates data has been transferred. o open drain 56 31 r/ w a logic 1 indicates a read operation, a logic 0 a write operation. icmos5 32 irq a low output on this pin indicates an event has occurred and the microprocessor should read the interrupt registers. a read of both interrupt registers resets this pin. o open drain 56 33,35-39, 42-43 d7:0 data port for read or write data. d0 = scl clock input for i2c when ser = logic 0. i/o open drain 56 44 sda data i/o pin for i2c. not available on VP305 version. i/o open drain 56 45 reset active high reset input, with 100k pull down resistor. i cmos 5 48 xto crystal output. an internal feedback resistor to xti is included. ocmos3.3 49 xti crystal clock input or external reference clock input for qpsk block. icmos3.3 50 status output pin for various functions selected by register bits. o cmos 3.3 1 51 mclk mpeg clock output at the data byte rate. o tri- state 3.3 1 63-60, 57-54 mdo7:0 mpeg transport packet data output bus. o tri- state 3.3 1 64 mdoen logic 1 = mpeg data and clock outputs disable - tristate. logic 0 = mpeg data and clock outputs enable. icmos5 pin no name pin description i/o note v ma
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 75 67 moval mpeg data output valid. this pin is high during the mclk clock cycles when valid data bytes are being output. o tri- state 3.3 1 68 bkerr flag for packets which have uncorrectable byte errors. the pin goes low for the whole of the packet containing uncorrectable errors. o tri- state 3.3 1 69 mostrt mpeg output start signal, high on the first byte of a packet. o tri- state 3.3 1 75 test1 for factory test only. this pin must be connected to vss in normal operation. icmos3.3 76 verr viterbi error indication. o tri- state 3.3 1 77 test2 for factory test only. this pin must be connected to vss in normal operation. icmos3.3 80 gpp0 general purpose port input. controlled by the gpp register. icmos5 84-81 gpp4:1 general purpose port outputs. controlled by the gpp register. o open drain 56 87 agc_out sigma delta modulated agc true output. a logic 0 = minimum gain. o open drain 56 88 cr_vco2d carrier vco positive feedback output 2 down. a logic 1 decreases and a logic 0 increases the carrier vco frequency. o tri- state 3.3 1 89 cr_vco1d carrier vco positive feedback output 1 down. a logic 1 decreases and a logic 0 increases the carrier vco frequency. o tri- state 3.3 1 90 cr_vco2u carrier vco positive feedback output 2 up. a logic 1 increases and a logic 0 decreases the carrier vco frequency. o tri- state 3.3 1 91 cr_vco1u carrier vco positive feedback output 1 up. a logic 1 increases and a logic 0 decreases the carrier vco frequency. o tri- state 3.3 1 96 sym_vcou symbol pulse width modulated true output. a logic 1 increases and a logic 0 decreases the symbol vco frequency. o tri- state 3.3 1 97 sym_vcod symbol pulse width modulated inverted output. a logic 1 decreases and a logic 0 increases the symbol vco frequency. o tri- state 3.3 1 100 test3 for factory test only. this pin must be connected to vss in normal operation. icmos3.3
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 76 pin no name pin description i/o note v ma 2,12,20, 28,34,41, 47,53,59, 65,70,74, 78,86,93, 98 vdd +3.3v power supply. all pins must be connected. 3,13,21, 29,40,46, 52,58,66, 72,79,85, 92,99 vss 0v power ground. all pins must be connected. table 20. pinout details . the remaining pins 71, 73, 94 and 95 are n/c - not connected internal to the VP305/6. they may be connected external to the VP305/6.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 77 6.6. alphabetical listing of the pinout. function pin function pin function pin function pin a0 27 iin0 11 qin0 19 vdd 47 a1 26 iin1 10 qin1 18 vdd 53 a2 25 iin2 9 qin2 17 vdd 59 agc_out 87 iin3 8 qin3 16 vdd 65 as 23 iin4 7 qin4 15 vdd 70 bkerr 68 iin5 6 qin5 14 vdd 74 cr_vco1d 89 irq 32 r/ w 31 vdd 78 cr_vco2d 88 mclk 51 reset 45 vdd 86 cr_vco1u 91 mdo0 54 sda 44 vdd 93 cr_vco2u 90 mdo1 55 ser 1vdd98 cs 24 mdo2 56 status 50 verr 76 d0 (scl) 43 mdo3 57 sym_vcod 97 vss 3 d1 42 mdo4 60 sym_vcou 96 vss 13 d2 39 mdo5 61 sys_clk 22 vss 21 d3 38 mdo6 62 test1 75 vss 29 d4 37 mdo7 63 test2 77 vss 40 d5 36 mdoen 64 test3 100 vss 46 d6 35 mostrt 69 xti 48 vss 52 d7 33 moval 67 xto 49 vss 58 dtack 30 n/c 71 vdd 2 vss 66 gpp0 80 n/c 73 vdd 12 vss 72 gpp1 81 n/c 94 vdd 20 vss 79 gpp2 82 n/c 95 vdd 28 vss 85 gpp3 83 pscal 4 vdd 34 vss 92 gpp4 84 pscal 5 vdd 41 vss 99 table 21. alphabetical listing of the pinout.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 78 6.7. numerical listing of the pinout. pin function pin function pin function pin function 1 ser 26 a1 51 mclk 76 verr 2 vdd 27 a0 52 vss 77 test2 3 vss 28 vdd 53 vdd 78 vdd 4 pscal 29 vss 54 mdo0 79 vss 5 pscal 30 dtack 55 mdo1 80 gpp0 6 iin5 31 r/ w 56 mdo2 81 gpp1 7 iin4 32 irq 57 mdo3 82 gpp2 8 iin3 33 d7 58 vss 83 gpp3 9 iin2 34 vdd 59 vdd 84 gpp4 10 iin1 35 d6 60 mdo4 85 vss 11 iin0 36 d5 61 mdo5 86 vdd 12 vdd 37 d4 62 mdo6 87 agc_out 13 vss 38 d3 63 mdo7 88 cr_vco2d 14 qin5 39 d2 64 mdoen 89 cr_vco1d 15 qin4 40 vss 65 vdd 90 cr_vco2u 16 qin3 41 vdd 66 vss 91 cr_vco1u 17 qin2 42 d1 67 moval 92 vss 18 qin1 43 d0 (scl) 68 bkerr 93 vdd 19 qin0 44 sda 69 mostrt 94 n/c 20 vdd 45 reset 70 vdd 95 n/c 21 vss 46 vss 71 n/c 96 sym_vcou 22 sys_clk 47 vdd 72 vss 97 sym_vcod 23 as 48 xti 73 n/c 98 vdd 24 cs 49 xto 74 vdd 99 vss 25 a2 50 status 75 test1 100 test3 table 22. numerical listing of the pinout.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 79 1 30 31 50 51 80 81 100 gh10 0 fig. 27. pin connections - top view.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 80 7. references. 1. european digital video broadcast standard, ets 300 421 december 1994. ets secretariat 06921 sophia antipolis cedex france. 2. purchase of mitel i2c components conveys a licence under the philips i2c patent rights to use these components in i2c systems, provided that the systems conform to the i2c standard specification as defined by philips.
draft - preliminary data VP305/6 the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 81 8. appendix 1: features general conforms to ebu specification for dvb-s. parallel 8 bit or i2c bus microprocessor interface. demodulator bpsk or qpsk selectable. variable symbol data rate from 5 to 30msym/sec. decimation filter with over sampling ratios of 2, 3, 4. adc decimation ratios of 1, 2, 4, 8, 16. viterbi selectable decoder rates 1/2, 2/3, 3/4, 5/6, 7/8. 3 bit soft decision decoder input from qpsk. constraint length k=7. trace back depth 128. on chip error rate monitor. synchronisation control automatic synchronisation. de-interleaver forney with depth 12. reed solomon conforms to ebu specification. descrambler ebu specification descrambler. ordering information. vp306 s / cg / gp1n.
VP305/6 draft - preliminary data the duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 82 9. appendix 2: lock acquisition algorithm. 9.1. pre conditions. set the frequency sweep limits in cr_uswl and cr_lswl registers, also the reference period cr_rp, see page 12. set the carrier threshold cr_thsl = 72 and the carrier sweep rate cr_swr = 150. 9.2. lock acquisition algorithm. the symbol loop phase lock acquisition is automatically handled in the VP305/6. it is initiated by turning on the carrier sweep function with the carrier loop open. the ndaml carrier phase detector is enabled. these three items are selected in cr_config[2:0] register 30. next the carrier loop is closed and a program loop started to detect when lock occurs. the carrier phase lock acquisition is indicated in the status register (3) by cr_lc (bit 1) going high. when this event occurs, the carrier sweep is turned off. the lock condition is checked five times to ensure it is stable then the program loop is exited. example of pseudo code fragment (using decimal number representation): write cr_config = 39 to register address 30. (sweep on, loop open, ndaml) write cr_config = 37 to register address 30. (sweep on, loop closed, ndaml) initialise variables: trend = 0, a_flag = 0, loop: for a_loop = 0 to 200 do loop_stat = read cr_lc from status[1] register address 3. if loop_stat = 1 then trend = trend + 1 write cr_config = 36 to register address 30. (sweep off, loop closed, ndaml) if trend > 5 then a_flag = 1 goto ex_acq end if end if if loop_stat = 0 then trend = 0 end if next a_loop ex_acq: sucess if sucessful, the loop exits with a_flag = 1, otherwise, a_flag = 0.

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