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L9857
High voltage high-side driver
Features

High voltage rail up to 450 V dV/dt immunity 50 V/nsec in full temperature range Driver current capability: 500 mA source, 500 mA sink Switching times 100 ns rise/fall with 2.5 nF load CMOS/TTL Schmitt trigger inputs with hysteresis and pull down Under voltage lock out Clamping on VCC Non inverting input Reset circuitry SO8 package It has the capability of driving N channel PowerMOS transistors. The upper (floating) section is enabled to work with voltage rail up to 450 V. The logic inputs are CMOS/TTL compatible for ease of interfacing with controlling devices.. SO-8

Description
The L9857 is an high voltage device, manufactured with the BCD "off-line" technology. Table 1. Device summary
Op. temp range, C -40 to +125 -40 to +125
Order code L9857-TR L9857-TR-LF
Package SO-8 SO-8
Packing Tape and reel Tape and reel
October 2009
Doc ID 12896 Rev 2
1/11
www.st.com 11
Content
L9857
Content
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 2.4 2.5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Reset functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 4 5
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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Doc ID 12896 Rev 2
L9857
Block diagram and pin description
1
1.1
Figure 1.
Block diagram and pin description
Block diagram
Block diagram
VB Undervoltage RESET VB to VS VCC Undervoltage RESET VCC to GND Pulse Filter FLIP FLOP Break before Make
HO
VS
RESLogic Pulse Filter IN GND
Level Shifter "ON" Level Shifter "OFF"
1.2
Pin description
Figure 2. Pin connection (top view)
VCC IN GND RESET1 2 3 4 8 7 6 5 VB HO VS NC
Table 2.
Pin # 1 2 3 4 5 6 7 8
Pin function
Pin name VCC IN GND RESETNC VS HO VB Driver supply, typically 17V Driver control signal input (positive logic) Ground Driver enable signal input (negative logic) No connection (no bondwire) MOSFET source connection MOSFET gate connection Driver output stage supply Description
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Electrical specifications
L9857
2
2.1
Electrical specifications
Thermal data
Table 3.
Symbol Rth(j-amb)
Thermal data
Parameter Thermal resistance junction-to-ambient Max. Value 150 Unit C/W
2.2
Absolute maximum ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND, all currents are defined positive into any lead. This is a stress only rating and operation of the device at these or any conditions exceeding those indicated in the operational sections of this specifications is not implied. Table 4. Absolute maximum ratings
Parameter Symbol VBS VB VS VHO VCC VIN IIN VRES Vesd VCDM dV/dt Tj Tstg TL Definition High side floating supply voltage High side driver output stage voltage High side floating supply offset voltage Output voltage gate connection Supply voltage Input voltage Input injection current. Full function, no latch-up; (guaranteed by design). Test at 10 V and 17 V on eng. samples. Reset input voltage Electrostatic discharge voltage (human body model) Charge device model CDM, EOS/ESD ass. std 5.3. number of discharges per pin: 6 Allowable offset voltage slew rate Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) 3 times Bosch soldering profil acc. to Bosch soldering conditions, gen. spec. Min. -0.3 -0.3 VB - 20 VS - 0.3 -0.3 -0.3 -0.3 2k 500 -50 -55 -55 Value Units Max. 20 300 300 VB + 0.3 20 VCC + 0.3 +1 VCC + 0.3 50 150 150 C 300 V V V V V V mA V V V V/nsec
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Doc ID 12896 Rev 2
L9857
Electrical specifications
2.3
Recommended operating conditions
For proper operations the device should be used within the recommended conditions. Table 5. Recommended operating conditions
Parameter Symbol VB VS VHO VCC VIN VRES FS Tamb Definition High side driver output stage voltage -5 V transient 0.1s High side floating supply offset voltage - 20 V transient 0.1s Output voltage gate connection Supply voltage Input voltage Reset input voltage Switching frequency Ambient temperature Min. VS+10 (1) -5 VS 10 0 0 -40 Value Units Max. VS+18 300 VB 18 VCC VCC 200 125 V V V V V V kHz C
1. Reset-Logic functional for VB-VS=2V, independent from VCC-level
2.4
Electrical characteristics
Unless otherwise specified, VCC = 15 V, VBS = 15 V, VS = 0 V, IN = 0 V, RES = 5 V, load R = 50 , C = 2.5 nF. Unless otherwise noted, these specifications apply for an operating junction temperature range of -40 C Tj 125 C
Table 6.
Symbol VCC supply VCCUV VCCUVHYS
Electrical characteristics
Parameter Test condition Min. Typ. Max. Unit
VCC supply undervoltage VCC supply undervoltage lockout hysteresis Undervoltage lockout response time VCC supply current
VCC rising from 0 V VCC dropping from 10 V VCC steps either from 10 V to 6 V or from 6 V to 10 V -
7.2 0.02 0.5 -
0.2 -
9.6 0.4 20 400
V V s A
tdUVCC
IQCC
VBS supply VBSUV tdUVBS VBS supply undervoltage Undervoltage lockout response time VBS rising from 0 V VBS dropping from 10 V VBS steps either from 10 V to 6 V or from 6 V to 10 V 7.2 0.5 9.6 20 V s
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Electrical specifications Table 6.
Symbol VBSUVHYS IQBS1 VBS supply current IQBS2 VBS VBS drop due to output turn-on
L9857
Electrical characteristics (continued)
Parameter VBS supply undervoltage lockout hysteresis static mode, VBS = 10 V, IN = 0 V or 5 V static mode, VBS = 18 V, IN = 0 V or VCC VBS = 17 V, CBS = 1 F, tdIG-IN = 3 s, tTEST = 100 s Test condition Min. 0.02 Typ. 0.2 Max. 0.4 100 200 210 Unit V A A mV
Gate driver characteristics IPKSo1 IPKSo2 Peak output source current IPKSo3 IPKSo4 IHOH,off tr1 tr2 tr3 tr4 IPKSi1 IPKSi2 Peak output sink current IPKSi3 IPKSi4 tf1 tf2 tf3 tf4 tplh Output fall time Output rise time HOH off-state leakage current VBS = 17 V, Tj = 25 C PW 10 s VBS = 17 V, PW 10 s Guaranteed by design VBS = 10 V, Tj = 25C VBS = 10 V VBS = 17 V, Tj = 25 C VBS = 17 V IN = VCC, Tj = 25 C VBS = 10 V, PW < 10 s IN = VCC, VBS = 10V , PW < 10 s IN = VCC, Tj = 25 C VBS = 17 V, PW < 10 s IN = VCC, VBS = 17 V, PW < 10 s VBS = 10 V, Tj = 25 C VBS = 10 V VBS = 17 V, Tj = 25 C VBS = 17 V Input-to-output turn-on propogation delay (50 % input level to 10 % output level) 250 150 120 70 250 150 500 300 0.2 0.3 0.1 0.15 250 150 500 300 0.2 0.3 0.1 0.15 0.1 1 0.4 0.5 0.2 0.3 mA 0.4 0.5 0.2 0.3 0.3 s s s A VBS = 10 V , Tj = 25 C PW 10 s VBS = 10 V PW 10 s 120 70 250 150 mA
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Doc ID 12896 Rev 2
L9857 Table 6.
Symbol tphl
Electrical specifications Electrical characteristics (continued)
Parameter Input-to-output turn-off propogation delay (50 % input level to 90% output level) RES-to-output turn-off propogation delay (50% input level to 90% output levels) RES-to-output turn-on propogation delay (50% input level to 10% output levels) Test condition Min. Typ. 0.1 Max. 0.2 Unit
tphl_res
-
0.1
0.3
s
tplh_res
-
-
0.1
0.8
Input characteristics VINH VINL RIN IIN VH_RES VL_RES High logic level input threshold Low logic level input threshold High logic level input resistance (Pull-down resistor) Low logic level input current High logic level RES input threshold Low Logic Level RES input threshold High logic level RES input resistance (Pull-down resistor) Low logic level input current VIN = 0 Reset signal comes from a 5 V system! R eset signal comes from a 5V system! Reset signal comes from a 5 V system with pull-up resistor 3.8 k to 5 V. (1) VRES = 0 9.5 60 3.5 V 6 300 5 V 1.4 k A
RRES IRES
60 -
-
300 5
k A
1. 4 HS-driver reset- inputs and other IC with their input pull-down resistors are connected in parallel with the RESET wire. The enable input RES- is an active low input, that means a logic low turns the external Power MOSFET off. The input circuitry has to make sure, that the MOSFET is off, when the pin is open or floating. In the application the RES- pin is tied to a bipolar open collector transistor or MOSFET open drain transistor with pull-up resistor 3.8K to +5V together with other RES- inputs of other IC.
2.5
Reset functional diagram
The diagram is guaranteed for the following condition. VCC = 10 V; VBS = 10 V @ -40 C, VCC = 17 V; VBS = 17 V @ +25 C and 125 C Figure 3. Reset functional diagram
IN RESET HO-VS: -40C HO-VS: 25C HO-VS: 125C
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Timing diagrams
L9857
3
Timing diagrams
Figure 4. Input/output timing diagram
IN RES Vs
Figure 5.
IN
Reset timing diagram
90%
90%
RES HOH,L
tplh_res tphl_res
10% tr tf 10%
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L9857
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 6.
DIM. MIN. A A1 A2 b c D (1) E E1
(2)
SO-8 mechanical data and package dimensions
mm TYP. MAX. 1.750 0.100 1.250 0.280 0.170 4.800 5.800 3.800 4.900 6.000 3.900 1.270 0.250 0.400 1.040 0 8 0.100 0 0.500 0.0098 1.270 0.0157 0.0409 8 0.0039 0.250 0.0039 0.0492 0.480 0.0110 0.230 0.0067 0.0189 0.0091 MIN. inch TYP. MAX. 0.0689 0.0098
OUTLINE AND MECHANICAL DATA
5.000 0.1890 0.1929 0.1969 6.200 0.2283 0.2362 0.2441 4.000 0.1496 0.1535 0.1575 0.0500 0.0197 0.0500
e h L L1 k ccc
Notes: 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm in total (both side). 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side.
SO-8
0016023 D
Doc ID 12896 Rev 2
9/11
Revision history
L9857
5
Revision history
Table 7.
Date 20-Nov-2006 07-Oct-2009
Document revision history
Revision 1 2 Initial release. Updated Table 1: Device summary. Changes
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Doc ID 12896 Rev 2
L9857
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Doc ID 12896 Rev 2
11/11

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