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19-5543; Rev 2; 1/11
TION KIT EVALUA BLE AVAILA
High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator
General Description
The MAX9611/MAX9612 are high-side current-sense amplifiers with an integrated 12-bit ADC and a gain block that can be configured either as an op amp or comparator, making these devices ideal for a number of industrial and automotive applications. The high-side, current-sense amplifiers operate over a wide 0V to 60V input common-mode voltage range. The programmable full-scale voltage (440mV, 110mV, and 55mV) of these amplifiers offers wide dynamic range, accurate current measurement, and application flexibility in choosing sense resistor values. A choice of either an internal op amp or a comparator is provided to the user. The internal amplifier can be used to limit the inrush current or to create a current source in a closed-loop system. The comparator can be used to monitor fault events for fast response. An I2C controlled 12-bit, 500sps analog-to-digital converter (ADC) can be used to read the voltage across the sense resistor (VSENSE), the input common-mode voltage (VRSCM), op-amp/comparator output (VOUT), op-amp/ comparator reference voltage (VSET), and internal die temperature. The I2C bus is compatible with 1.8V and 3.3V logic, allowing modern microcontrollers to interface to it. The MAX9611 features a noninverting input-to-output configuration while the MAX9612 features an inverting input-to-output configuration. The MAX9611/MAX9612 operate with a 2.7V to 5.5V supply voltage range, are fully specified over the -40NC to +125NC automotive temperature range, and are available in a 3mm x 5mm, 10-pin FMAXM package.
Features
S 0V to +60V Input Common-Mode Voltage Range S 2.7V to 5.5V Power-Supply Range, Compatible with 1.8V and 3.3V Logic S 5A Software Shutdown Current S Integrated 12-Bit ADC S 13V Current-Sense ADC Resolution S 500V (max) Current-Sense ADC Input Offset Voltage S 0.5% (max) Current-Sense ADC Gain Error S I2C Bus with 16 Addresses S Small, 3mm x 5mm 10-Pin MAX Package S -40NC to +125NC Operating Temperature Range
MAX9611/MAX9612
Ordering Information/ Selector Guide
PART MAX9611AUB+ MAX9612AUB+ OUTPUT Noninverting Inverting PIN-PACKAGE 10 FMAX 10 FMAX
Note: All devices operate over the -40NC to +125NC temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Application Circuit
0V TO 60V
RSENSE
Applications
Hybrid Automotive Power Supplies Server Backplanes Base-Station PA Control Base-Station Feeder Cable Bias-T Telecom Cards Battery-Operated Equipment
0.1F VIN
RS+ VCC
RSA0 A1
LOAD
OUT SET
MAX9611 MAX9612 SCL SCL
C
1.8V LOGIC GND SDA SDA
FMAX is a registered trademark of Maxim Integrated Products, Inc.
Functional Diagrams appear at end of data sheet.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator MAX9611/MAX9612
ABSOLUTE MAXIMUM RATINGS
VCC to GND.............................................................-0.3V to +6V RS+, RS-, OUT to GND .........................................-0.3V to +65V Differential Input Voltage, RS+ - RS- ................................. Q65V All Other Pins to GND .............................................-0.3V to +6V OUT Short-Circuit to GND .........................................Continuous Continuous Current into Any Pin ..................................... Q20mA Continuous Power Dissipation (TA = +70NC) 10-Pin FMAX (derate 8.8mW/NC above +70NC)...........707mW FMAX Package Junction-to-Ambient Thermal Resistance (BJA) (Note 1)............................113NC/W Operating Temperature Range ........................ -40NC to +125NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal consideration, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 3.3V, VRS+ = VRS- = +12V, VSENSE = (VRS+ - VRS-) = 0V, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER Input Common-Mode Range SYMBOL CONDITIONS Guaranteed by CMRR TA = +25NC, gain = 8x TA = -40NC to +125NC, gain = 8x Input Offset Voltage ADC Path (Note 3) VOS TA = +25NC, gain = 4x TA = -40NC to +125NC, gain = 4x TA = +25NC, gain = 1x TA = -40NC to +125NC, gain = 1x TA = +25NC, gain = 8x TA = -40NC to + 85NC, gain = 8x TA = -40NC to +125NC, gain = 8x Gain Error (Note 3) GE TA = +25NC, gain = 4x TA = -40NC to +125NC, gain = 4x TA = +25NC, gain = 1x TA = -40NC to +125NC, gain = 1x Differential Input Resistance Common-Mode Input Resistance Input Bias Current Input Offset Current (Note 4) RINDM RINCM IRS+, IRS(IRS+) - (IRS-) TA = +25NC TA = -40NC to +125NC TA = +25NC TA = -40NC to +125NC 3 300 12 1 2 5 6 6 1 0.4 0.1 0.1 0.045 MIN 0 0.045 TYP MAX 60 0.5 2 0.5 2 0.8 2.6 0.5 1.8 2.5 1.7 3.1 4 4.7 kI MI FA nA % mV UNITS V CURRENT-SENSE AMPLIFIER DC CHARACTERISTICS
2
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.3V, VRS+ = VRS- = +12V, VSENSE = (VRS+ - VRS-) = 0V, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS Gain = 8x, VSENSE = 50mV VRS- = 0V to 60V, TA = +25NC Gain = 4x, VSENSE = 100mV Gain = 1x, VSENSE =400mV Gain 8x, VSENSE = 50mV VRS- = 0V to 60V, TA = -40NC to +125NC Gain 4x, VSENSE = 100mV Gain 1x, VSENSE = 400mV Gain = 8x, VSENSE = 50mV Power-Supply Rejection Ratio PSRR VCC = 2.7V to 5.5V Gain = 4x, VSENSE = 100mV Gain = 1x, VSENSE = 400mV Full-Scale Sense Voltage FS Used in gain error measurement Gain = 8x LSB Step Size LSB Gain = 4x Gain = 1x ANALOG PATH, CSA + AMPLIFIER/COMPARATOR Input Offset Voltage SET Input Bias Current Maximum SET Input Voltage Range Signal Bandwidth Gain Bandwidth Propagation Delay Internal Hysteresis Output Sink Current Output Leakage Current Output Voltage Low VOL BW GBW tPD VHYS In comparator mode, 10mV overdrive In comparator mode, nonlatching VOUT = 4V VOUT = 36V ISINK = 8mA, TA = -40C to +85C ISINK = 8mA, TA = -40NC to +125NC 0.5 Gain = 1x, RS- = 11.6V VOS IB TA = +25NC TA = -40NC to +125NC 1 1.126 4 2.5 1.5 8 20 1.7 3 1 1.5 0.350 4 10 50 mV nA V MHz MHz Fs mV mA FA V Gain = 8x Gain = 4x Gain = 1x MIN 106 106 100 94 94 84 57 56 48 72 67 57 55 110 440 13.44 26.88 107.50 FV mV dB TYP 120 120 120 dB MAX UNITS
MAX9611/MAX9612
Common-Mode Rejection Ratio
CMRR
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator MAX9611/MAX9612
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.3V, VRS+ = VRS- = +12V, VSENSE = (VRS+ - VRS-) = 0V, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER Full-Scale Input Voltage LSB Step Size Gain Error Input Offset Voltage SYMBOL CONDITIONS MIN TYP 57.3 14 0.8 14 MAX UNITS V mV 6 7 110 160 57.3 LSB GE VOSOUT VRSCM = (VRS+ - VRS-)/2 TA = +25NC TA = -40NC to +125NC 1.10 268 GE VOSOUT INL DNL VRSCM = (VRS+ - VRS-)/2 TA = +25NC TA = -40NC to +125NC 1 0.2 0.48 -40 LSB 0.48 12 2 VIL VIH VHYS VCC = 2.7V to 5.5V VCC = 2.7V to 5.5V 1.45 0.05 x VCC 1 1/4 x VCC 1/2 x VCC 3/4 x VCC 1 200 0.4 +125 TA = +25NC TA = -40NC to +125C 0.3 0.2 5 6 10 14 TA = +25NC TA = -40NC to +125C 14 14 0.3 6 7 80 160 % mV OUT VOLTAGE MEASUREMENT (VOUT) LSB GE VOSOUT VRSCM = (VRS+ - VRS-)/2 TA = +25NC TA = -40NC to +125NC TA = +25NC TA = -40NC to +125C
COMMON-MODE VOLTAGE MEASUREMENT (VRSCM) Full-Scale Input Voltage LSB Step Size Gain Error Input Offset Voltage V mV % mV
SET VOLTAGE MEASUREMENT (VSET) Full-Scale Input Voltage LSB Step Size Gain Error Input Offset Voltage Integral Nonlinearity Differential Nonlinearity TEMPERATURE MEASUREMENT Accuracy Typical Measurement Range LSB Step Size ANALOG-TO-DIGITAL CONVERTER Resolution Conversion Time SCL/SDA LOGIC LEVELS Input Voltage Low Input Voltage High Input Hysteresis Input Leakage Current A1/A0 LOGIC LEVELS Logic State 00-01 Threshold Logic State 01-10 Threshold Logic State 10-11 Threshold Input Leakage Current V V V nA V V V 200 nA Bit ms NC NC NC V FV % mV LSB LSB
4
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.3V, VRS+ = VRS- = +12V, VSENSE = (VRS+ - VRS-) = 0V, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER Power-Supply Input Range Quiescent Current Shutdown Current Serial-Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time, (Repeated) START Condition SCL Clock Low Period SCL Clock High Period Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SDA/SCL Receiving Rise Time SDA/SCL Receiving Fall Time SDA Transmitting Fall Time STOP Condition Setup Time Bus Capacitance Pulse Width of Spike Suppressed SYMBOL VCC ICC ISHDN fSCL tBUF tDH,STA tLOW tHIGH tSU,STA tDH,DAT tSU,DAT tR tF tF tSU,STO CB tSP 50 (Note 5) (Note 5) (Note 5) No activity on SCL 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 400 300 300 250 Fs pF ns ns 900 CONDITIONS Guaranteed by PSRR MIN 2.7 1.6 5 TYP MAX 5.5 2.6 10 400 UNITS V mA FA kHz Fs Fs Fs Fs Fs Fs ns POWER-SUPPLY CHARACTERISTICS
MAX9611/MAX9612
I2C TIMING CHARACTERISTICS (COMPATIBLE WITH SMBus)
Note 2: All devices are 100% production tested at TA = +25NC. Temperature limits are guaranteed by design. Note 3: VOS and gain error of current-sense amplifier extrapolated from from a two-point measurement made at VSENSE = (VRS+ VRS-) = 5mV to 50mV in gain of 8x, 5mV to 100mV in gain of 4x, and 10mV to 400mV in gain of 1x. Note 4: Guaranteed by design. Note 5: CB is in pF.
I2C Timing Diagram
SDA tSU,DAT tHD,DAT tHIGH tSU,STA tBUF tHD,STA tSU,STO
tLOW SCL tHD,STA
tR
tF REPEATED START CONDITION STOP CONDITION START CONDITION
START CONDITION
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator MAX9611/MAX9612
Typical Operating Characteristics
(VCC = 3.3V, VCM = 12V, TA = +25NC, unless otherwise noted.)
CSA HISTOGRAM
MAX9611 toc01
MAX9611 CSA OFFSET VOLTAGE vs. COMMON-MODE VOLTAGE
MAX9611 toc02
TOTAL OFFSET VOLTAGE vs. COMMON-MODE VOLTAGE
ANALOG PATH 3 2 VOS (mV) TA = -40C
MAX9611 toc03
30 25 20 COUNTS 15 10 5 0
GAIN = 8x
700 600 500 400 VOS (V) 300 200 100 0 -100 -200 -300 0
8x ADC PATH TA = +125C
4
TA = +85C
1 0 -1
TA = +25C
TA = -40C
TA = +25C
-2 -3 -4 50 60 0
TA = +85C
TA = +125C
-300
-240
-180
-120
-60
0
60
120
180
240
300
10
20
30 VCM (V)
40
10
20
30 VCM (V)
40
50
60
VOFFSET_CSA (V)
CSA OFFSET VOLTAGE vs. SUPPLY VOLTAGE
MAX9611 toc04
TOTAL OFFSET VOLTAGE vs. SUPPLY VOLTAGE
OP-AMP PATH
MAX9611 toc05
200 150 100 50 VOS (V) 0 -50 -100 -150 -200 -250 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 ADC PATH GAIN = 8x
800 700 600 VOS (V) 500 400 300 200
5.5
2.5
3.0
3.5
4.0 VCC (V)
4.5
5.0
5.5
RS- BIAS CURRENT vs. COMMON-MODE VOLTAGE
MAX9611 toc06
RS+, RS- OFFSET CURRENT vs. COMMON-MODE VOLTAGE
MAX9611 toc07
5 4 3 2 1 0 0 10 20 30 VCM (V) 40 50 TA = +25C TA = -40C TA = +125C TA = +85C
2.5 2.0 IOFFSET (nA) 1.5 1.0 0.5 0
IBIAS (mA)
60
0
10
20
30 VCM (V)
40
50
60
6
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator
Typical Operating Characteristics (continued)
(VCC = 3.3V, VCM = 12V, TA = +25NC, unless otherwise noted.)
MAX9611/MAX9612
MAX9611 CSA GAIN ERROR vs. COMMON-MODE VOLTAGE
MAX9611 toc08
TOTAL GAIN ERROR vs. COMMON-MODE VOLTAGE
MAX9611 toc09
SDA/SCL VOL vs. SINKING CURRENT
MAX9611 toc10
1.00 0.80 0.60 GAIN ERROR (%) 0.40 0.20 0 -0.20 -0.40 -0.60 -0.80 -1.00 0
0.4 0.2 GAIN ERROR (%) 0
8x ADC PATH +25C -40C
ANALOG PATH
0.05 0.04 SDA VOL (V) 0.03 0.02 0.01 0 0 0.5 1.0 1.5 2.0 2.5
-0.2 -0.4 -0.6
+85C +125C
-0.8 -1.0
10
20
30 VCM (V)
40
50
60
0
10
20
30 VCM (V)
40
50
60
3.0
SDA SINKING CURRENT (mA)
OUTPUT LOW VOLTAGE vs. OUTPUT SINK CURRENT
3.5 OUTPUT LOW VOLTAGE (V) 3.0 ICC (mA) 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 OUTPUT SINK CURRENT (mA)
MAX9611 toc11
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9611 toc12
4.0
2.0 1.7 1.4 1.1 0.8 0.5 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0
5.5
CSA GAIN vs. FREQUENCY (RS+/RS- TO OUT PATH)
MAX9611 toc13
OP-AMP GAIN vs. FREQUENCY (SET TO OUT)
10 5 0 GAIN (dB) -5 -10 -15 -20 RS+ - RS- = 220mV VIN = 100mVP-P 1 10 100 FREQUENCY (kHz) 1,000 10,000
MAX9611 toc14
15 10 5 0 GAIN (dB) -5 -10 -15 -20 -25 -30 1 RS+ - RS- = VSENSE + VDC = 200mVP-P + 300mV 10 100 FREQUENCY (kHz) 1,000
15
-25 -30
10,000
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator MAX9611/MAX9612
Typical Operating Characteristics (continued)
(VCC = 3.3V, VCM = 12V, TA = +25NC, unless otherwise noted.)
CMRR vs. FREQUENCY CSA ADC PATH
MAX9611 toc15
CMRR vs. FREQUENCY ANALOG OP-AMP PATH
-75 -80 -85 CMRR (dB) -90 -95 -100 -105 -110 -115 -120 NOISE (5V/div)
MAX9611 toc16
P-P NOISE (RS+/RS- TO OUT)
MAX9611 toc17
0 -20 -40 CMRR (dB) -60 -80 -100 -120 -140 1 10
VCM = 12V VAC = 10VP-P
-70
100
1000
0.01
0.1
1
10
100
1000
TIME (10s/div)
FREQUENCY (kHz)
FREQUENCY (kHz)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (SET INPUT)
MAX9611 toc18
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE (SET INPUT)
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX9611 toc19
0.5 0.3 0.1 -0.1 INL (LSB) -0.3 -0.5 -0.7 -0.9 -1.1 -1.3 -1.5 0
1.0
512 1024 1536 2048 2560 3072 3584 4096 DIGITAL CODE
0
512 1024 1536 2048 2560 3072 3584 4096 DIGITAL CODE
ADC NOISE HISTOGRAM ON VSET = 0.5V
MAX9611 toc20
ADC NOISE HISTOGRAM ON VSENSE = 20mV (GAIN = 8x)
900 800 700 600 500 400 300 200 100 0 N
MAX9611 toc21
1000 900 800 700 600 500 400 300 200 100 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 0 N
1000
DIGITAL CODE
8
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1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 DIGITAL CODE
High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator
Typical Operating Characteristics (continued)
(VCC = 3.3V, VCM = 12V, TA = +25NC, unless otherwise noted.)
MAX9611/MAX9612
HOT-SWAP OPERATION WITH p-CHANNEL FET MODE 000
MAX9611 toc22
WATCHDOG LATCH RETRY MODE 111
MAX9611 toc23
WATCHDOG LATCH RETRY MODE 111
MAX9611 toc24
VPULLUP VOLTAGE (5V/div) VOLTAGE (5V/div)
DTIM = 0, RTIM = 0 VSET = 600mV PULSE WIDTH < 1ms
DTIM = 0, RTIM = 1 VSET = 600mV PULSE WIDTH > 1ms
VOUT (UNREGULATED)
VCSAIN
200mV/div
VCSAIN
200mV/div
VOUT (REGULATED) ROUT = 8I TIME (100s/div)
VOUT
5V/div
VOUT
5V/div
TIME (400s/div)
TIME (4ms/div)
WATCHDOG LATCH MODE 111
MAX9611 toc25
WATCHDOG LATCH MODE 111
MAX9611 toc26
200mV/div VCSAIN VCSAIN 200mV/div
VOUT
10V/div DTIM = 1, RTIM = 1 VSET = 600mV PULSE WIDTH > 1ms TIME (100s/div) VOUT
5V/div DTIM = 0, RTIM = 1 VSET = 600mV PULSE WIDTH > 1ms TIME (1ms/div)
WATCHDOG LATCH RETRY MODE 111
MAX9611 toc27
WATCHDOG LATCH RETRY MODE 111
MAX9611 toc28
DTIM = 0, RTIM = 0 VSET = 600mV PULSE WIDTH > 1ms
VCSAIN
DTIM = 0, RTIM = 1 VSET = 600mV PULSE WIDTH > 1ms
200mV/div VCSAIN 200mV/div
VOUT
5V/div VOUT 5V/div TIME (10ms/div)
TIME (10ms/div)
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator MAX9611/MAX9612
Pin Configuration
TOP VIEW
+
OUT 1 RS+ RSSET GND 2 3 4 5
10 VCC 9 A0 A1 SDA SCL
MAX9611 MAX9612
8 7 6
MAX
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME OUT RS+ RSSET GND SCL SDA A1 A0 VCC Internal Amplifier/Comparator Output Positive Current-Sensing Input. Power side connects to external sense resistor. Negative Current-Sensing Input. Load side connects to external sense resistor. External Set-Point Voltage Ground I2C Interface Clock Input I2C Interface Data Input/Output Address Input 1 Address Input 0 Supply Voltage Input. Bypass VCC to GND with a 0.1FF and a 4.7FF capacitor in parallel. FUNCTION
10
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator
Functional Diagrams
RS+ RSVCC
MAX9611/MAX9612
CSA
MAX9611
2.5x
1x, 4x, 8x
A0 DECODER A1
OUT
OP AMP/ COMP
TEMP
MUX
12-BIT ADC
I2C REGISTERS
SCL SDA
SET
GND
RS+
RS-
VCC
CSA
MAX9612
2.5x
1x, 4x, 8x
A0 DECODER A1
OUT
OP AMP/ COMP
TEMP
MUX
12-BIT ADC
I2C REGISTERS
SCL SDA
SET
GND
NOTE: ANALOG PATH IN BOLD.
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator MAX9611/MAX9612
Detailed Description
The MAX9611/MAX9612 are high-side, current-sense amplifiers with an integrated 12-bit ADC and an internal selectable op amp/comparator. These devices are ideal for a variety of industrial and automotive applications. The MAX9611/MAX9612's high-side, current-sense amplifiers operate over a wide 0V to 60V input common-mode voltage range. The programmable full-scale voltage (440mV, 110mV, and 55mV) allows for a wide dynamic range current measurement and application flexibility in choosing sense resistor values. The I2C bus is 1.8V and 3.3V logic compatible and can interface with modern microcontrollers. An internal 12-bit, 500sps integrating analog-to-digital converter (ADC) allows the user to read analog signals such as die temperature, VOUT, VSET, VRSCM, and VSENSE. At power-up, the selectable op-amp/comparator block is configured in the op-amp mode. The op amp has an effective 60V Class A-type output stage and can be used to limit inrush currents and create a current source when used in a closed-loop system. When the internal comparator is selected, the MAX9611/MAX9612 can be configured to have a latched and retry functionality, allowing a 60V open-drain transistor output, ideal to operate high-side relay-disconnect FETs. The MAX9611 has a noninverting input-to-output configuration while the MAX9612 has an inverting input-to-output configuration. The MAX9611/MAX9612 feature a precision current-sense amplifier with a 0V to 60V input common-mode voltage range. An internal negative charge pump eliminates input stage crossover distortion, typical in most rail-to-rail input current-sense amplifiers. Low input bias currents and low input offset currents allow a wide selection of input filters to be designed without degrading the accuracy of the current-sense amplifier. The current-sense amplifier inputs feature both a -0.3V/+65V common-mode absolute maximum rating as well as a Q65V differential absolute maximum rating, allowing a wide variety of fault conditions to be withstood easily by the device without damage. The current-sense amplifier has a gain of 2.5V/V and connects directly to the output op-amp/comparator inputs. The ADC path features a 1x, 4x, and 8x programmable gain providing for 440mV, 110mV, and 55mV fullscale sense voltage. The MAX9611/MAX9612 feature an internal dual-slope integrating 12-bit ADC that has a 2ms conversion time and a 1.8V and 3.3V logic-compatible I2C bus. An internal mux allows the following on chip variables to be read: input sense voltage, input common-mode voltage, SET voltage, OUT voltage, and die temperature. Temperature Measurement Die temperature can be read by the ADC over the entire operating range (-40NC to +125NC) with 0.5NC resolution. Die temperature can be used for application calibration and thermal monitoring and is available in a 9-bit, two's complement format. Readings outside of normal operating temperature range (-40NC to +125NC) are inaccurate and should be considered invalid. See Table 1 for binary and hex values.
Analog-to-Digital Converter (ADC)
Current-Sense Amplifier
Table 1. Binary and Hex Digital Output Values for Temperature Measurements
TEMPERATURE (NC) +122.4 +24 +0.48 0 -0.48 -24 -40 DIGITAL OUTPUT BINARY 0111 1111 1xxx xxxx 0001 1001 0xxx xxxx 0000 0000 1xxx xxxx 0000 0000 0xxx xxxx 1111 1111 1xxx xxxx 1110 0111 0xxx xxxx 1101 1001 1xxx xxxx HEX 7F8x 190x 008x 000x FF8x E70x D98x
12
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator
SET Voltage Measurement The SET voltage serves as a reference voltage for the internal op amp or comparator around which a control loop can be designed. The low bias current for SET allows high-impedance resistor-dividers and currentoutput DACs to be used, making it easy to interface without introducing additional errors. The SET input can also serve as an auxiliary input port to the ADC, if the op amp or comparator is not utilized in the application. Its full-scale input range extends from 0V to 1.10V. OUT Voltage Measurement The internal amplifier/comparator output voltage can be monitored over the entire 0V to 57.3V range by the ADC. An internal high-value resistor divider on OUT reduces leakage current effects. Common-Mode Voltage Measurement The input common-mode voltage is defined as the average of the voltage at RS+ and RS-. A high value resistordivider allows measurement of the input common-mode voltage over the 0V to 57.3V range. Sense Voltage Measurement Three programmable gains allow for a wide range of currents to be read by the ADC. The current-sense amplifier gain can be set to 1x, 4x, or 8x. The full-scale sense voltages are then 440mV, 110mV, and 55mV, respectively. The MAX9611/MAX9612 feature an internally selectable op amp and comparator where one of the inputs is connected to the 2.5x current-sense amplifier, and the other input is connected to the SET input. The op amp or the comparator output can be selected and connected to OUT. The output stage is an open-drain 60V nFET, that requires a suitable pullup resistor for proper operation. The op amp then behaves like a Class-A output stage. Select op amp or comparator function in Control Register 1 (0x0A) bit 7 (see Tables 4 and 5). Watchdog/Latch/Retry Functionality Internal digital circuitry is used to implement a watchdog feature that can be useful to handle normal application transients that are not true fault conditions. This feature applies both to the op amp and comparator modes of part operation. A watchdog delay time is internally set to 1ms by default but can be changed to 100Fs. The retry delay time is internally set to 50ms by default, but can be changed to 10ms (see Tables 6 and 7). In normal operation mode, (Control Register 1 (0x0A) 000x xxxx), the amplifier output responds to the difference between its inputs, i.e., the CSA output voltage and the SET voltage. In open-loop configuration, the op amp can be used as a comparator. In a watchdog-latch-retry mode (Control Register 1 (0x0A) 111x xxxx), the output of the comparator waits for a watchdog delay time (to ensure the CSA output continues to stay above the SET voltage for this duration) before responding, and then latches onto this state. After a retry delay time, it resets the comparator state and the cycle repeats. Similar functionality is implemented for the op-amp mode as well (Control Register 1 (0x0A) 000x xxxx to 011x xxxx). A RESET bit is defined in Control Register 1 (0x0A) to reset a latched state when commanded by the user.
MAX9611/MAX9612
Output Amplifier/Comparator
I2C Interface
The MAX9611/MAX9612 I2C interface consists of a serial-data line (SDA) and serial-clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX9611/MAX9612 and the master at rates up to 400kHz. The MAX9611/MAX9612 are slave devices that transfer and receive data. The master (typically a microcontroller) initiates data transfer on the bus and generates the SCL signal to permit that transfer.
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator MAX9611/MAX9612
A bus master initiates communication with a slave device by issuing a START (S) condition followed by a slave address. When idle, the MAX9611/MAX9612 continuously wait for a START condition followed by their slave address. When the MAX9611/MAX9612 recognize a slave address, it is ready to accept or send data. The MAX9611/MAX9612 offer 16 different slave addresses using two address inputs, A1 and A0. See Table 2 for different slave address options. The least significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from the MAX9611/ MAX9612 (R/W = 0 selects a write condition, R/W = 1 selects a read condition). After receiving the address, the MAX9611/MAX9612 (slave) issue an acknowledge by pulling SDA low for one clock cycle. A write operation (Figure 1) begins with the bus master issuing a START condition followed by seven address bits and a write bit (R/W = 0). If the address byte is successfully received, the MAX9611/MAX9612 (slave) issue an acknowledge (A). The master then writes to the slave and the sequence is terminated by a STOP (P) condition for a single write operation. For a burst write operation, more data bytes are sent after the register address before the transaction is terminated.
Slave Address
In an I2C read operation (Figure 2), the bus master issues a write command first by initiating a START condition followed by seven address bits, a write bit (R/W = 0) and the 8-bit register address. The master then issues a Repeated START (Sr) condition, followed by seven address bits, a read bit (R/W = 1). If the address byte is successfully received, the MAX9611/MAX9612 (slave) issue an acknowledge (A). The master then reads from the slave. For continuous read, the master issues an acknowledge bit (AM) after each received byte. The master terminates the read operation by sending a not acknowledge (NA) bit. The MAX9611/MAX9612 then release the data line SDA allowing the master to generate a STOP condition.
I2C Read Operation
I2C Write Operation
SINGLE WRITE S
ACKNOWLEDGE FROM MAX9611/MAX9612 SLAVE ADDRESS R/W 0 A REGISTER ADDRESS
A
DATA
A
P
BURST WRITE S
STOP ACKNOWLEDGE FROM MAX9611/MAX9612 SLAVE ADDRESS R/W 0 A REGISTER ADDRESS
A A
DATA 1 DATA 3
A A
DATA 2 DATA N A STOP P
Table 2. MAX9611/MAX9612 Address Description
A1 0 0 0 0 1/3 x VCC 1/3 x VCC 1/3 x VCC 1/3 x VCC 2/3 x VCC 2/3 x VCC 2/3 x VCC 2/3 x VCC VCC VCC VCC VCC 14 A0 0 1/3 x VCC 2/3 x VCC VCC 0 1/3 x VCC 2/3 x VCC VCC 0 1/3 x VCC 2/3 x VCC VCC 0 1/3 x VCC 2/3 x VCC VCC DEVICE WRITE ADDRESS (hex) 0xE0 0xE2 0xE4 0xE6 0xE8 0xEA 0xEC 0xEE 0xF0 0xF2 0xF4 0xF6 0xF8 0xFA 0xFC 0xFE DEVICE READ ADDRESS (hex) 0xE1 0xE3 0xE5 0xE7 0xE9 0xEB 0xED 0xEF 0xF1 0xF3 0xF5 0xF7 0xF9 0xFB 0xFD 0xFF
Figure 1. I2C Write Operation
SINGLE READ S
ACKNOWLEDGE FROM MAX9611/MAX9612 SLAVE ADDRESS R/W SLAVE ADDRESS R/W ACKNOWLEDGE FROM MAX9611/MAX9612 0A 1 A R/W SLAVE ADDRESS R/W DATA AM DATA N NO READ-ACKNOWLEDGE FROM MASTER NA P 0A REGISTER ADDRESS DATA ACKNOWLEDGE FROM FROM MASTER REGISTER ADDRESS DATA
A Sr BURST READ S
1
A
AM P
SLAVE ADDRESS
A Sr REPEAT START AM
Figure 2. I2C Read Operation
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator
The MAX9611/MAX9612 include five 12-bit data register banks and two 8-bit control registers. The two control registers are read/write registers used to configure the ADC for different modes of operation.
Registers
Table 3 lists all the registers, their corresponding POR values and their addresses.
MAX9611/MAX9612
Table 3. Internal Register/Addresses
REGISTERS CSA DATA BYTE 1 (MSBs) CSA DATA BYTE 1 (LSBs) RS+ DATA BYTE 1 (MSBs) RS+ DATA BYTE 1 (LSBs) OUT DATA BYTE 1 ( MSBs) OUT DATA BYTE 1 (LSBs) SET DATA BYTE 1 (MSBs) SET DATA BYTE 1 (LSBs) TEMP DATA BYTE 1 (MSBs) TEMP DATA BYTE 1 (LSBs) CONTROL REGISTER 1 CONTROL REGISTER 2 POR VALUES (hex) 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x800 0x000 0x000 0x000 REGISTER ADDRESS (hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B
Data Registers The five 12-bit data registers banks comprise two 8-bit registers for 8 MSBs and 4 LSBs. The 12-bit data is split between the two 8-bit data bytes as seen in Figure 1. They are read-only registers that hold the converted data. Do not issue a STOP command until both bytes are read. Instead use a Repeated START command to read the second byte.
Byte 1
BIT 7 MSB12 BIT 6 MSB11 BIT 5 MSB10 BIT 4 MSB09 BIT 3 MSB08 BIT 2 MSB07 BIT 1 MSB06 BIT 0 MSB05
Byte 2
BIT 7 LSB05 BIT 6 LSB03 BIT 5 LSB02 BIT 4 LSB01 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0
Control Register 1 Control Register 1 is an 8-bit write/read register that configures the MAX9611/MAX9612 for different modes of operation. Tables 4 and 5 show the bit location and function for Control Register 1.
Table 4. Control Register 1 Bit Location
BIT NUMBER BIT NAME POR VALUE 7 MODE2 0 6 MODE1 0 5 MODE0 0 4 LR 0 3 SHDN 0 2 MUX2 0 1 MUX1 0 0 MUX0 0
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator MAX9611/MAX9612
Table 5. Control Register 1 Bit Description
BIT BIT NAME FUNCTION 000 Channel A: Read current-sense amplifier output from ADC, gain = 1x 001 Channel A: Read current-sense amplifier output from ADC, gain = 4x 010 Channel A: Read current-sense amplifier output from ADC, gain = 8x 011 Channel B: Read average voltage of RS+ (input common-mode voltage) from ADC 100 Channel C: Read voltage of OUT from ADC 101 Channel D: Read voltage of SET from ADC 110 Channel E: Read internal die temperature from ADC 111 Read all channels in fast-read mode, sequentially every 2ms. Uses last gain setting. Power-on state = 0 0 = Normal operation 1 = Shutdown mode 0 = Normal operation 1 = Reset if comparator is latched due to MODE = 111. This bit is automatically reset after a 1 is written. 000 = Normal operation for op amp/comparator 111 = Comparator mode. OUT remains low until CSA output > VSET for 1ms, OUT latches high for 50ms, then OUT autoretries by going low. The comparator has an internal 10mV hysteresis voltage to help with noise immunity. For MAX9612, the polarity is reversed. 011 = Op-amp mode. OUT regulates pFET for 1ms at VSET, OUT latches high for 50ms, then OUT autoretries by going low. For MAX9612, the polarity is reversed.
2, 1, 0
MUX2, MUX1, MUX0
3
SHDN
4
LR
7, 6, 5
MODE2, MODE1, MODE0
Control Register 2 Control Register 2 is an 8-bit write/read register that provides the different time delay options for asserting the comparator output when monitoring fault events. Tables 6 and 7 show the bit location and function for Control Register 2.
Table 6. Control Register 2
BIT NUMBER BIT NAME POR VALUE 7 X 0 6 X 0 5 X 0 4 X 0 3 DTIM 0 2 RTIM 0 1 X 0 0 X 0
Table 7. Control Register 2 Bit Descriptions
BIT 7, 6, 5, 4 3 BIT NAME X DTIM Set to 0 Watchdog delay time 0 = 1ms 1 = 100Fs Watchdog retry delay time 0 = 50ms 1 = 10ms Set to 0 FUNCTION
2 1, 0
RTIM X
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator
The MAX9611/MAX9612 include power-on reset circuitry that ensures all registers reset to a known state on power-up. Once VCC goes above 2.4V, the POR circuit releases the registers for normal operation.
Power-On Reset
Applications Information
The MAX9611 can be used as an inrush current limiter for a number of applications as shown in Figure 3. Note that the sense resistor can be placed on either side of the pFET. Since the input common-mode voltage of the MAX9611 extends to ground, the sense resistor can be placed at the load side as well, allowing current to be sensed even when there is a dead-short on the load. The inrush current limiting circuit reads and measures the load-current during normal operation and can limit the load current to a user-set value. In normal operation, the load current is below the set threshold. The pFET is fully turned on because the op-amp output is at 0V. In the event of an overcurrent situation at the load, the op-amp controls the pFET's gate-voltage so it transitions to a linear region, thus limiting the load current. In this case, the op-amp output voltage is between 0V and VBAT, as required for current-limiting.
Choose a suitable sense resistor and a low RDS-on pFET to ensure the best efficiency during normal operation. Choose a pFET with large power dissipation to ensure compliance with safe operating area of the pFET. The MAX9611 comes equipped with a variety of watchdog options to help with this design (see Control Register 2, Table 7). Choose resistor values R1 and R2 to ensure that the pFET is fully on in normal operating conditions and to ensure that the VGS maximum rating is not exceeded. Also, R1 and R2 help limit the current in the open-drain output stage of the internal op amp. RCOMP and CCOMP help roll-off high-frequency gain of the feedback control system. R2 and CCOMP set a pole, for which 10kHz is a good choice. RCOMP and CCOMP set a zero, for which 100kHz is a good choice. With the internal gain of the current-sense amplifier (2.5V/V), the inrush current-limit threshold can be set using resistor-divider R3 and R4 as follows: VCC x R3 = ILIMIT R2 + R3)(2.5 x R SENSE ) ( Note: The inrush current limiter can be changed to a high-side relay-disconnect circuit by using the MAX9611 set to comparator mode (MODE 111).
MAX9611/MAX9612
Inrush Current Limiter
INRUSH CURRENT LIMITER
RSENSE
VBAT
CCOMP R2 P RCOMP 2.7V TO 5.5V RS+ VCC 0.1F R1 R4 MAX9611 OUT 0.1F R3 1F SET SCL SDA I2C CLOCK INPUT I2C DATA INPUT/OUTPUT RSLOAD
A0 A1
GND
(OUTPUT SET TO OP-AMP MODE)
Figure 3. Inrush Current Limiter ______________________________________________________________________________________ 17
High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator MAX9611/MAX9612
While the MAX9611 is designed to control high-side pFETs, the MAX9612 can be similarly used to control low-side nFETs. For example the MAX9612 can be used to control the DC bias point of power amplifier LDMOS or GaN nFETs in base-station applications. The circuit shown in Figure 4 also allows the option to apply negative bias voltages to the PA FET, which is required for certain types of transistors for proper operation. In the circuit shown, the nFET is in a linear mode of operation to allow it to amplify high-frequency RF signals, while the MAX9612 sets the DC operating point. The gain of the FET can be varied by changing its drain current. This operating point can be varied by an external DAC voltage that feeds the SET pin. VNEG and VCLAMP together with R1, R2, and R3 set the DC bias point limits for the PA transistor. VCLAMP is a suitable positive voltage and VNEG is a suitable negative voltage. When VOUT = 0V, the gate voltage of the PA FET is: VNEG x R2 = VOUT (R1 + R2)
Base-Station PA Gain Control
When the OUT open-dran transistor is off, the gate voltage of the PA FET is: VGATE = VCLAMPR1 VNEG (R2 + R3) + R1 + R2 + R3 R1 + R2 + R3
RCOMP and CCOMP connected to the OUT pin compensate the internal amplifier. Choose a corner frequency of 100kHz. Choose suitable RSENSE as required for the application. The inductor isolates the DC measuring point of current from the high-frequency AC signals through the PA FET, as well as helping with the high-frequency gain. The MAX9611/MAX9612 share a common ground pin for both the analog and digital on-chip circuitry. It is therefore very important to properly bypass the VCC to GND, and to have a solid low-noise ground plane on the circuit board so as to minimize ground bounce. Bypass VCC to GND with low ESR 0.1FF in parallel with a 4.7FF ceramic capacitors to GND placed as close as possible to the device.
Power-Supply Bypassing and Grounding
Chip Information
PROCESS: BiCMOS
BASE-STATION PA GAIN CONTROL
2.7V TO 5.5V RFOUT CIN VCLAMP R3 N R2
RSVCC
RS+ A0 A1 MAX9612 I2C CLOCK INPUT I2C DATA INPUT/OUTPUT
10-BIT DAC
SCL SDA
OUT R1 VNEG RFIN (OUTPUT SET TO OP-AMP MODE) RCOMP CCOMP SET
GND
Figure 4. Base-Station PA Gain Control 18 _____________________________________________________________________________________
High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 10 FMAX PACKAGE CODE U10+2 OUTLINE NO. 21-0061 LAND PATTERN NO. 90-0330
10LUMAX.EPS
MAX9611/MAX9612
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High-Side, Current-Sense Amplifiers with 12-Bit ADC and Op Amp/Comparator MAX9611/MAX9612
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 9/10 11/10 1/11 Initial release Updated text in Table 5 to add "comparator" to mode 000 for bits 7, 6, 5 Relaxed room temperature limits for 4x and 8x gains from 0.3mV to 0.5mv DESCRIPTION PAGES CHANGED -- 16 1, 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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