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| www..com Maintenance only Features UD61466 64K x 4 DRAM SCM facilitates faster data operation with predefined row address. Via 8 address inputs the 16 address bits are transmitted into the internal address memories in a time-multiplex operation. The falling RASedge takes over the row address. After the row address hold time the column address can be applied. During the Read cycle the address transfer is not latched by the falling edge at the CAS input, so that the column address must be applied until the data are valid at the output. During Write the column address is taken over with the falling edge of the control signal CAS, or W, that becomes active as the last. The selection of one or more memory circuits can be made via the RAS input. Data Output Control The usual state of the data output is the High-Z state. Whenever CAS is inactive (HIGH), Q will float (High-Z). Thus, CAS functions as data output control. After access time, in case of a Read cycle, the output is activated, and it contains the logic 0" or 1". The memory cycle being a Read, Read-Write or a Write cycle (W-controlled), Q changes from High-Z state to the active state (0" or 1"). After access time, the contents of the selected cell will be available, with the exception of the Write cycle. The output remains active until CAS becomes inactive, irrespective of RAS becoming inactive or not. The memory cycle being a Write cycle (CAS-controlled), the data output keeps its High-Z state throughout the whole cycle. This configuration makes Q fully controllable by the user merely through the timing of W. The output storaging the data, they remain valid from the end of access time until the start of another cycle. F Dynamic random access memory F F F F F F F F F F F 65536 x 4 bits manufactured using a CMOS technology RAS access times 70 ns/80 ns TTL-compatible Three-state outputs bidirectional 256 refresh cycles 4 ms refresh cycle time STATIC COLUMN MODE Operating modes: Read, Write, Read - Write, RAS only Refresh, Hidden Refresh with address transfer Low power dissipation Power supply voltage 5 V Package PDIP18 (300 mil) Operating temperature range 0 to 70 C Quality assessment according to CECC 90000, CECC 90100 and CECC 90112 Read-Write-Control The choice between Read or Write cycle is made at the W input. HIGH at the W input causes a Read cycle, Description meanwhile LOW leads to a Write cycle. Addressing The UD61466 is a dynamic random Both CAS-controlled and W-controlaccess memory organized 65536 led Write cycles are possible with words by 4 bits. activated RAS signal. Pin Configuration Pin Description (OE) G DQ0 DQ1 1 2 3 4 5 6 7 8 9 18 17 16 15 13 12 11 10 VSS DQ3 CAS DQ2 A6 A3 A4 A5 A7 Signal Name A0 - A7 DQ0 - DQ3 W RAS G VCC VSS CAS Signal Description Address Inputs Data In/Out Read, Write Control Row Address Strobe Output Enable Power Supply Voltage Ground Column Address Strobe (WE) W RAS A0 A2 A1 VCC PDIP 14 SOJ Top View December 12, 1997 1 UD61466 Block Diagram DQ0 G Data Input and Output Amplifier Output Control DQ1 DQ2 DQ3 CAS W Write-Read-Control 4 Write-Read-Amplifiers RAS Clock Generator 128 Kbit Array with Sensor Amplifier Row Decoder VCC VSS 128 Kbit Array with Sensor Amplifier Column Decoder A0 A1 Address Input A2 A3 A4 A5 A6 A7 M U X A0X to A7X A0Y to A7Y Row Decoder Operation Address R X Row Row Row Row C X Function Stand-by Read Write Read-Write 1st cycle 2nd cycle 1st cycle 2nd cycle 1st cycle 2nd cycle RAS H L L L L L L L L CAS X L L L L L L L L W X H L HL H H L HL HL HL X H L G X L X LH L L X X LH LH X Data High-Z Output Data Input Data Output Data/Input Data Output Data Output Data Input Data Input Data Output Data/Input Data Output Data/Input Data High-Z Output Data Input Data Column Column Column Column Column SCM Read SCM Write Row Column Column Row Column SCM Read-Write L L L H L L Column Row Row Row Column Column RAS only Refresh HIDDEN Refresh*) Read L H L Write L H L L X *) Transfer of Refresh Address required 2 December 12, 1997 UD61466 Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and operating temperature range indicated below. Absolute Maximum Ratings Power Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Remarks: see page 7 1) 1) 1a) Symbol VCC VI VO IO PD Ta Tstg Min. -0.5 -1.0 -1.0 -50 Max. 7.0 7.0 7.0 50 1 Unit V V V mA W C C 0 -55 70 125 Recommended Operating Conditions Power Supply Voltage Input Low Voltage Input High Voltage Remark: see page 7 1) Symbol VCC VIL VIH Min. 4.5 -1.0 2.4 Max. 5.5 0.8 5.5 Unit V V V Capacitances Input Capacitance A0 to A7 Input Capacitance RAS, CAS, W and G Output Capacitance DQ0 to DQ3 Conditions Symbol CI1 CI2 CO Min. Max. 6 7 7 Unit pF pF pF V CC VI f Ta = 5.0 V = VSS = 1 MHz = 25 C All pins not under test (alternating voltage) must be connected with ground. December 12, 1997 3 UD61466 Min. Static Characteristics Power Supply Current (average value of RAS-CAS cycles) Refresh Current (average value of RAS cycles) 2) Max. Unit DC07 70 DC08 60 mA Conditions tcW = tcWmin tcR = tcRmin CAS = VIH tcW = tcWmin tcR = tcRmin RAS = VIL tc(A) = tc(A)min RAS = CAS = VIH RAS = VCC 0.2 V CAS = VCC 0.2 V IOH = -5 mA IOL = 4.2 mA VI = 0 V to 5.5 V VO = 0 V to 5.5 V RAS = CAS = VIH Symbol DC07 ICC1 DC08 2) ICC2 70 60 mA SCM Current (average value of SCM cycles) Stand-by Current TTL Level 2) ICC3 50 40 mA ICC4 2 2 mA Stand-by Current CMOS Level ICC5 1 1 mA Output High Voltage Output Low Voltage Input Leakage Current at any input, all other pins = 0 V Output Leakage Current Q = High-Z VOH VOL II 2.4 2.4 0.4 0.4 10 V V A -10 -10 10 IO -10 -10 10 10 A Remarks: see page 7 4 December 12, 1997 UD61466 Symbol Alt. IEC Min. DC07 DC08 Max. Unit DC07 DC08 Dynamic Characteristics 3) F ALL CYCLES Transition Time (Rise and Fall) RAS Precharge Time CAS Precharge Time Row Address Set-up Time Row Address Hold Time Output Buffer Turn-off Delay Time Output Buffer Turn-off Delay Time from OE CAS to RAS Precharge Time RAS to Column Address Delay Time Column Address to RAS Lead Time CAS to Output in Low-Z Refresh Period 5) 5) 4) tT tRP tCP tASR tRAH tOFF tOEZ tCRP tRAD tRAL tCLZ tREF tt tw(RASH) tw(CASH) tsu(RA-RAS) th(RAS-RA) tv(CAS) tv(G) tCASH-RASL tRAS-CA tCA-RASH tCASL-QX trf 3 50 10 0 10 0 0 5 15 35 0 3 60 10 0 10 0 0 5 15 40 0 50 50 ns ns ns ns ns 20 20 35 20 20 40 ns ns ns ns ns ns ms 6) 4 4 F READ Random Read Cycle Time Access Time from RAS Access Time from Column Address Access Time from CAS OE Access Time RAS Pulse Width CAS Pulse Width Read Command Set-up Time Read Command Hold Time ref. to RAS 9) Read Command Hold Time Column Address Hold Time ref. to RAS 10) Column Address Hold Time ref. to RAS Rise RAS to CAS Delay Time CAS Hold Time RAS Hold Time RAS Hold Time referenced to OE Remarks: see page 7 6) 9) 7) 8) 8) 8) 8) tRC tRAC tAA tCAC tOEA tRAS tCAS tRCS tRRH tRCH tAR tAH tRCD tCSH tRSH tROH tcR ta(RAS) ta(CA) ta(CAS) ta(G) tw(RASL) tw(CASL) tsu(R-CAS) th(RAS-R) th(CAS-R) th(RAS-CA) th(RASH-CA) tRASL-CASL tRASL-CASH tCASL-RASH tGL-RASH 130 150 70 35 20 20 80 40 20 20 ns ns ns ns ns ns ns ns ns ns ns ns 50 60 ns ns ns ns 70 20 0 0 0 70 5 20 70 20 10 80 20 0 0 0 80 5 20 80 20 10 10000 10000 10000 10000 December 12, 1997 5 UD61466 Symbol Alt. IEC Min. DC07 DC08 Max. Unit DC07 DC08 Dynamic Characteristics 3) F WRITE Random Write Cycle Time RAS Pulse Width CAS Pulse Width Write Command Pulse Width Write Command Set-up Time Data Set-up Time ref. to CAS Data Set-up Time ref. to W Column Address Set-up Time Column Address to W Delay Time 11) 12) 12) 12) 12) 7) tRC tRAS tCAS tWP tWCS tDS tDS tASC tAWD tWCH tWCR tRWL tCWL tDH tDH tAR tCAH tCAH tOEH tRCD tCSH tRSH tcW tw(RASL) tw(CASL) tw(W) tsu(W-CAS) tsu(D-CAS) tsu(D-W) tsu(CA-CAS) tsu(CA-W) th(CAS-W) th(CASH-W) th(RAS-W) th(W-RAS) th(W-CAS) th(CAS-D) th(W-D) th(RAS-CA) th(CAS-CA) th(W-CA) th(W-GL) tRASL-CASL tRASL-CASH tCASL-RASH 130 70 25 15 0 0 0 0 0 15 0 55 20 20 15 15 55 15 15 20 20 70 20 150 80 25 15 0 0 0 0 0 15 0 60 20 20 15 15 60 15 15 20 20 80 20 50 60 10000 10000 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write Command Hold Time Write Command Hold Time ref. to CAS-High Write Command Hold Time ref. to RAS Write Command to RAS Lead Time Write Command to CAS Lead Time 12) Data Hold Time ref. to CAS 12) Data Hold Time ref. to W Column Address Hold Time ref. to RAS 12) Column Address Hold Time Column Address Hold Time 12) OE Command Hold Time RAS to CAS Delay Time CAS Hold Time RAS Hold Time 6) F READ-WRITE Read-Write Cycle Time RAS Pulse Width CAS Pulse Width CAS Hold Time RAS to WRITE Delay Time CAS to WRITE Delay Time Column to WRITE Delay Time 7) tRWC tRAS tCAS tCSH tcRW tw(RASL)RW tw(CASL)RW t(RASLCASH)RW 185 125 75 125 100 50 65 205 135 75 135 110 55 70 10000 10000 10000 10000 ns ns ns ns ns ns ns 11) 11) 11) tRWD tCWD tAWD tRAS-W tCAS-W t(CA-W)RW F SCM Static Column Mode Cycle Time RAS Pulse Width CAS Precharge Time 13) tSC tRASC tCP tc(A) tw(RASL) tw(CASH) 50 70 10 50 80 10 100000 100000 ns ns ns Remarks: see page 7 6 December 12, 1997 UD61466 Dynamic Characteristics 3) Alt. Symbol IEC Min. DC07 DC08 Max. Unit DC07 DC08 F SCM Read Column Address Hold Time ref. to RAS Rise Output Data Hold Time from Column Address 10) tAH tAOH th(RASH-CA) tv(CA) 5 5 5 5 ns ns F SCM Write F SCM Read-Write Write Command Inactive Time tWI tw(WH) 10 10 ns Static Column Mode Read-Write Cycle Time Access Time from Last Write Output Data Enable Time from WRITE tSRWC tALW tOW tc(A)RW ta(WL) ta(WH) 100 65 35 110 75 40 ns ns ns F HIDDEN REFRESH Remark: see below Remarks: 1) CAS Hold Time (CAS before RAS Cycle) tCHR tRASL-CASH 15 15 ns 6) The Input Low Voltage must not drop below -0.3 V for more than 40 ns. The total sum of the absolute values of output currents must not exceed 100 mA in case of static application. The current is inversely proportional to the cycle time; the max. current is measured in the shortest cycle time. For test conditions see test configuration for functional test and clock timing. VIHmin and V ILmax are reference levels for time measurement of the input signals; transition times are measured between VIH and VIL. tv(CAS) and tv(G) define the time at which the data output goes to High-Z; this time is not related to any level. tRASL-CASLmax and tv(G) are given as reference points only; they do not represent restrictive conditions. The values of tcWmin, tcRmin and tcRWmin are used for indication of the particular cycle time in which full function is guaranteed in the temperature range from 0 to 70 C. Values below the one shown above may cause permanent damage to the component. Measured with a load equivalent to 2 TTL loads, 100 pF In Read cycle either th(RAS-R) or th(CAS-R) must be kept. th(RASH-CA) is only required if the valid data are to be held beyond the rising edge of RAS. 13) cycle is a Write cycle (CAS-controlled), and the data output remains in High-Z throughout the whole cycle, - if tCAS-W > tCAS-Wmin, tRAS-W > tRAS-Wmin and t(CA-W)RW > t(CAW)RWmin, the cycle is a ReadWrite cycle, and the content of the cell is available at the data output, - if none of these conditions is satisfied, the condition of the data output (at access time) is indeterminate, since a Write cycle (W-controlled) is carried out. 12) 7) 1a) 2) 8) 3) 9) 4) 10) These parameters refer to CAS during Write (CAS-controlled), and to W (W-controlled) or to W during Read-Write. Timing of CAS in SCM is necessary only if the data output is to go to High-Z between the readout of two successiv column addresses. 11) 5) tsu(W-CAS), tRAS-W, tCAS-W and t(CA-W)RW do not represent restrictive parameters: - if tsu(W-CAS) tsu(W-CAS)min and th(CASH-W) th(CASH-W)min, the 7 December 12, 1997 UD61466 Test Configuration for Functional Check 5V Input voltage according to timing diagrams (at least 8 operating cycles before measurement). All addresses are to be checked. A0 A1 A2 A3 A4 A5 A6 A7 RAS CAS W G VCC DQ0 DQ1 DQ2 DQ3 Output voltage check according to timing diagrams 1.2 K VIH VIL V0 100 pF 680 VSS IC Code Numbers Example UD61466 Type Package D = PDIP Operating Temperature Range C = 0 to 70 C Access Time 07 = 70 ns 08 = 80 ns D C 07 The date of manufacture is given by the 4 last digits of the mark, the 2 first digits indicating the year, and the last 2 digits the calendar week. 8 December 12, 1997 UD61466 Read tcR tw(RA SL) tw(RASH) RAS VIH VIL tRASL-CASH tCASH-RASL tRASL-CA SL tCA SL-RA SH tw(CA SL) tCA SH-RA SL CAS VIH VIL tsu(R-CAS) tCA-RASH th(RA S-R) th(CA S-R) W VIH VIL AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA tsu(RA-RAS) tsu(CA-CAS) th(RAS-RA ) ta(CAS) th(RA S-CA) AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA t h(RA SH-CA ) V A0 - A7 IH VIL AAAAA AAAAA AAAAA tRAS-CA AAA AAA AAA ta(CA) ta(RA S) tCA SL-QX AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA tv(CA S) DQ0 - VOH DQ3 VOL AAAAAAA AAAAAAA AAAAAAA tGL-RASH ta(G) Output Data tv(G) G VIH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA Write (CAS-controlled) tcW tw(RASL) tw(RASH) RAS VIH VIL tCASH-RASL tRA SL-CA SL tRASL-CASH tCASL-RASH tw(CA SL) tCA SH-RASL CAS VIH VIL th(W-CA S) th(W-RA S) th(RA S-W) th(CASH-W) W VIH AAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA tsu(RA-RA S) tsu(W-CAS) tw(W) th(CAS-W) AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA th(RA S-CA) th(RAS-RA ) V A0 - A7 VIH AAAAA AAAAA IL AAAAA tsu(CA-CA S) tsu(D-CA S) AAA AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA t h(CAS-CA) tCA-RASH th(CAS-D) Input Data DQ0 - VIH DQ3 VIL G VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 9 December 12, 1997 UD61466 Write (W-controlled) tcW tw(RASL) tw(RASH) RAS VIH VIL tCASH-RASL tRASL-CA SL tRASL-CA SH tCA SL-RA SH tw(CASL) tw(CASH) CAS VIH VIL th(CA S-W) th(W-CAS) th(W-RAS) W VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA t h(RA S-W) tw(W) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA th(RA S-CA) tsu(RA-RAS) th(RA S-RA) V A0 - A7 VIH AAAAA AAAAA IL AAAAA tRA S-CA AAA AAA AAA tsu(CA-W) tCA-RASH tsu(D-W) th(W-CA ) th(W-D) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA DQ0 - VIH DQ3 VIL AAAAAAAAA AAAAAAAAA AAAAAAAAA tv(G) Input Data t IXGL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA th(W-GL) G VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Read-Write tcRW tw(RASL) tCA SL-RASH tw(RA SH) RAS VIH VIL tCASH-RASL tRASL-CASL tRASL-CASH tw(CASL)RW tCASH-RASL CAS VIH VIL tsu(R-CAS) tRA S-W tCA S-W th(W-RAS) th(W-CAS) W VIH AAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA th(RAS-CA ) tsu(RA-RAS) th(RAS-RA ) tw(W) th(W-CA ) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A0 - A7 VIH AAAAA VIL AAAAA AAAAA AAA AAA AAA tRAS-CA ta(CA S) t(CA -W)RW tsu(D-W) O. D. ta(CA ) ta(RAS) ta(G) tv(G) tCA -RA SH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA th(W-D) DQ0 - VIH/VOH DQ3 VIL/VOL Input Data AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA G VIH VIL 10 December 12, 1997 UD61466 SCM Read tw(RA SL) tw(RASH) RAS VIH VIL tRASL-CASH tRASL-CASL tw(CASL) tw(CASH) tCASL-RASH tw(CASL) tCA SH-RA SL CAS VIH VIL tsu(R-CA S) tsu(R-CA S) th(CA S-R) th(RAS-R) th(CA S-R) W VIH VIL AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA tsu(RA -RA S) tRAS-CA th(RAS-RA) tCASL-QX tc(A) tc(A) AAAAAAA AAAAAAA AAAAAAA tCA-RASH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA th(RASH-CA) V A0 - A7 VIH IL AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA th(RAS-CA ) ta(CAS) ta(CA) ta(CA ) ta(CA) ta(CA S) tv(CAS) tCASL-QX tv(CA S) AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA DQ0 - VOH DQ3 VOL ta(RAS) AAAA AAAAA AAAA Outp. D. AAAAA Outp. D. AAAA AAAAA tv(CA) ta(G) tv(G) ta(G) AAAAA AAAAA Outp. D. AAAAA tv(G) tGL-RASH G VIH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA SCM Write (CAS-controlled) tw(RA SL) tw(RA SH) RAS VIH VIL tRASL-CA SH tRA SL-CA SL tw(CASH) tw(CA SL) tw(CASH) tw(CASL) tCA SL-RASH tCASH-RASL th(CASH-W) th(RAS-W) tsu(W-CAS) th(CA SH-W) tsu(W-CAS) tw(WH) th(CA SH-W) th(CA S-W) tw(W) t su(W-CA S) CAS VIH VIL th(CAS-W) tw(W) tsu(RA -RA S) th(RAS-RA ) th(RA S-CA) tsu(CA -CA S) th(W-RAS) th(CA S-W) tw(W) tw(WH) W VIH VIL AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA tsu(CA-CAS) th(CA S-CA) AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA th(CAS-CA ) tsu(CA-CAS) tCA-RASH th(CA S-CA) VIH A0 - A7 VIL AAAAAA AAAAAA AAAAAA tRAS-CA AAA AAA AAA AAAAAAAA AAAAAAAA AAAAAAAA tsu(D-CAS) th(CA S-D) AAAAAAAA AAAAAAAA AAAAAAAA th(CAS-D) tsu(D-CA S) AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA th(CAS-D) tsu(D-CA S) DQ0 - VIH DQ3 VIL AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA Input Data AAAAAAAAAAA Input Data AAAAAAAAA Input Data AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA G VIH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA December 12, 1997 11 UD61466 SCM Read-Write tw(RA SL) tw(RASH) RAS VIH VIL tRASL-CASL tCAS-W tCA SH-RA SL CAS VIH VIL tRAS-W t(CA-W)RW tw(W) t(CA-W)RW th(W-CAS) th(W-RA S) W VIH VIL tsu(RA -RA S) tRA S-CA th(RAS-RA) tc(A )RW th(W-CA) tCA-RASH A0 - A7 VIL V IH AAAAA AAAAA AAAAA AAAAAA AAAAAA AAAAAA ta(CAS) ta(RA S) ta(CA) tsu(W-D) AAAAAAAA AAAAAAAA AAAAAAAA th(W-GL) ta(WH) ta(CA) AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA DQ0 - VIH/VOH DQ3 VIL/VOL tCA SL-QX AAAAAA AA AAAAA AAAAAA O. D. AA I. D. AAAAA AAAAAA AA AAAAA tv(G) ta(G) th(W-D) ta(WL) AAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA O. D. AAA I. D. AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAA tv(G) ta(G) G VIH VIL AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA SCM Read-Write Mixed Cycle RAS VIH VIL tRA SL-CASL CAS VIH VIL tw(W) W VIH VIL tCA S-W tsu(RA -RA S) th(RAS-RA) t(CA -W)SC ta(WH) th(W-CA) V A0 - A7 VIH IL AAAAA AAAAA AAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA tRAS-CA AAAAAAAA AAAAAAAA AAAAAAAA tsu(D-W) th(W-D) Input D. AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA DQ0DQ3 VIH/VOH VIL/VOL ta(CA) AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tv(CA) tv(G) ta(CA ) ta(WL) AAAAAA AAAAAA AAAAAA ta(G) Output D. tv(CA) ta(CA S) ta(G) G VIH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA t a(RAS) 12 December 12, 1997 UD61466 RAS only Refresh tcR tw(RASL) tw(RA SH) RAS VIH VIL tCASH-RASL CAS VIH VIL W VIH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tsu(RA -RAS) th(RAS-RA ) V A0 - A7 VIH IL AAAAAA AAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA DQ0 - VOH DQ3 VOL High-Z G VIH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA HIDDEN Refresh with address transfer tcR tw(RASL) tw(RA SH) tw(RA SL) tcR t w(RASH) RAS VIH VIL tCASH-RA SL tRASL-CA SL tCASL-RASH tRASL-CASH tCA SH-RA SL CAS VIH VIL tsu(R-CAS) th(RAS-R) W VIH VIL AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA tsu(RA -RA S) tRA S-CA th(RAS-RA ) tCA-RASH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tsu(RA-RA S) th(RAS-RA ) V A0-A7 VIH IL AAAAA AAAAA AAAAA AAAAAA AAAAAA AAAAAA tCASL-QX ta(CA) ta(CAS) AAA AAA AAA th(RASH-CA ) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tv(CAS) DQ0 - VOH DQ3 VOL ta(RAS) AAAAA AAAAA AAAAA tv(G) ta(G) tGL-RA SH G VIH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA December 12, 1997 13 Memory Products 1998 64K x 4 DRAM UD61466 LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intend for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Zentrum Mikroelektronik Dresden GmbH Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 88 22-3 06 * Fax: +49 351 88 22-3 37 * Email: sales@zmd.de Internet Web Site: http://www.zmd.de |
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