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| SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET SX1239 Receiver Low Power Integrated UHF Receiver VBAT1&2 VR_ANA VR_DIG RC Oscillator / Modulators Demodulator & Bit Synchronizer Decimation and & Filtering RESET Power Distribution System LNA Single to Differential Mixers RFIN Control Registers - Shift Registers - SPI Interface RSSI Division by 2, 4 or 6 AFC Packet Engine & 66 Bytes FIFO SPI GND DIO0 DIO1 DIO2 DIO3 DIO4 Tank Inductor NC NC NC Loop Filter Frac-N PLL Synthesizer XO 32 MHz DIO5 XTAL GND GENERAL DESCRIPTION The SX1239 is a highly integrated RF receiver capable of operation over a wide frequency range, including the 433, 868 and 915 MHz license-free ISM (Industry Scientific and Medical) frequency bands. Its highly integrated architecture allows for a minimum of external components whilst maintaining maximum design flexibility. All major RF communication parameters are programmable and most of them can be dynamically set. The SX1239 offers the unique advantage of programmable narrow-band and wide-band communication modes without the need to modify external components. The SX1239 is optimized for low power consumption while offering high sensitivity and channelized operation. TrueRFTM technology enables a lowcost external component count (elimination of the SAW filter) whilst still satisfying ETSI and FCC regulations. KEY PRODUCT FEATURES High Sensitivity: down to -120 dBm at 1.2 kbps High Selectivity: 16-tap FIR Channel Filter Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm, 80 dB Blocking Immunity, no Image Frequency response Low current: Rx = 16 mA, 100nA register retention Constant RF performance over voltage range of chip FSK Bit rates up to 300 kb/s Fully integrated synthesizer with a resolution of 61 Hz FSK, GFSK, MSK, GMSK and OOK demodulation Built-in Bit Synchronizer performing Clock Recovery Incoming Sync Word Recognition 115 dB+ Dynamic Range RSSI Automatic RF Sense with ultra-fast AFC Packet engine with CRC, AES-128 encryption and 66byte FIFO Built-in temperature sensor and Low Battery indicator APPLICATIONS Automated Meter Reading Wireless Sensor Networks Home and Building Automation Wireless Alarm and Security Systems Industrial Monitoring and Control ORDERING INFORMATION Part Number Delivery Tape & Reel MOQ / Multiple 3000 pieces MARKETS Europe: EN 300-220-1 North America: FCC Part 15.247, 15.249, 15.231 Narrow Korean and Japanese bands SX1239IMLTRT QFN 24 Package - Operating Range [-40;+85C] Pb-free, Halogen free, RoHS/WEEE compliant product Rev 2 - April 2010 Page 1 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET Table of Contents 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.4. Page General Description ................................................................................................................................................ 8 Simplified Block Diagram ................................................................................................................................ 8 Pin and Marking Diagram................................................................................................................................ 9 Pin Description .............................................................................................................................................. 10 ESD Notice.................................................................................................................................................... 11 Absolute Maximum Ratings .......................................................................................................................... 11 Operating Range........................................................................................................................................... 11 Chip Specification ......................................................................................................................................... 12 Electrical Characteristics....................................................................................................................................... 11 2.4.1. Power Consumption ................................................................................................................................. 12 2.4.2. Frequency Synthesis ................................................................................................................................ 12 2.4.3. Receiver ................................................................................................................................................... 13 2.4.4. Digital Specification .................................................................................................................................. 14 3. Chip Description.................................................................................................................................................... 15 3.1. 3.2. 3.3. Power Supply Strategy.................................................................................................................................. 15 Low Battery Detector..................................................................................................................................... 15 Frequency Synthesis..................................................................................................................................... 15 3.3.1. Reference Oscillator ................................................................................................................................. 15 3.3.2. CLKOUT Output ........................................................................................................................................16 3.3.3. PLL Architecture ....................................................................................................................................... 16 3.3.4. Lock Time ..................................................................................................................................................17 3.3.5. Lock Detect Indicator................................................................................................................................ 17 3.4. Receiver Description ..................................................................................................................................... 17 3.4.1. Block Diagram .......................................................................................................................................... 17 3.4.2. LNA - Single to Differential Buffer .............................................................................................................18 3.4.3. Automatic Gain Control ............................................................................................................................ 18 3.4.4. Quadrature Mixer - ADCs - Decimators.................................................................................................... 20 3.4.5. Channel Filter ........................................................................................................................................... 20 3.4.6. DC Cancellation ....................................................................................................................................... 21 3.4.7. Complex Filter - OOK ............................................................................................................................... 21 3.4.8. RSSI ......................................................................................................................................................... 22 3.4.9. Cordic ....................................................................................................................................................... 22 3.4.10. Bit Rate Setting ...................................................................................................................................... 22 3.4.11. FSK Demodulator ................................................................................................................................... 23 3.4.12. OOK Demodulator ...................................................................................................................................24 3.4.13. Bit Synchronizer ......................................................................................................................................26 3.4.14. Frequency Error Indicator....................................................................................................................... 26 3.4.15. Automatic Frequency Correction ............................................................................................................ 27 3.4.16. Optimized Setup for Low Modulation Index Systems ............................................................................. 28 3.4.17. Temperature Sensor 29 Rev 2 - April 2010 Page 2 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET 3.4.18. Timeout Function.................................................................................................................................... 29 4. Operating Modes .................................................................................................................................................. 30 4.1. 4.2. Basic Modes.................................................................................................................................................. 30 Automatic Sequencer and Wake-Up Times .................................................................................................. 30 4.2.1. Receiver Startup Time.............................................................................................................................. 30 4.2.2. Rx Start Procedure ................................................................................................................................... 32 4.2.3. Optimized Frequency Hopping Sequences .............................................................................................. 32 4.3. Listen mode ................................................................................................................................................... 33 4.3.1. Timings ..................................................................................................................................................... 33 4.3.2. Criteria ...................................................................................................................................................... 34 4.3.3. End of Cycle Actions ................................................................................................................................ 34 4.3.4. RC Timer Accuracy .................................................................................................................................. 35 4.4. 5. 5.1. AutoModes .................................................................................................................................................... 36 Overview ....................................................................................................................................................... 37 Data Processing.................................................................................................................................................... 37 5.1.1. Block Diagram .......................................................................................................................................... 37 5.1.2. Data Operation Modes ............................................................................................................................. 37 5.2. Control Block Description.............................................................................................................................. 38 5.2.1. SPI Interface............................................................................................................................................. 38 5.2.2. FIFO ......................................................................................................................................................... 39 5.2.3. Sync Word Recognition ............................................................................................................................ 40 5.2.4. Packet Handler ......................................................................................................................................... 41 5.2.5. Control ...................................................................................................................................................... 41 5.3. Digital IO Pins Mapping ................................................................................................................................. 42 5.3.1. DIO Pins Mapping in Continuous Mode ................................................................................................... 42 5.3.2. DIO Pins Mapping in Packet Mode .......................................................................................................... 42 5.4. Continuous Mode .......................................................................................................................................... 43 5.4.1. General Description.................................................................................................................................. 43 5.4.2. Rx Processing .......................................................................................................................................... 43 5.5. Packet Mode ................................................................................................................................................. 44 5.5.1. General Description.................................................................................................................................. 44 5.5.2. Packet Format .......................................................................................................................................... 44 5.5.3. Processing (without AES)......................................................................................................................... 47 5.5.4. AES .......................................................................................................................................................... 47 5.5.5. Handling Large Packets ........................................................................................................................... 48 5.5.6. Packet Filtering......................................................................................................................................... 48 5.5.7. DC-Free Data Mechanisms ...................................................................................................................... 50 6. Configuration and Status Registers ...................................................................................................................... 52 6.1. 6.2. 6.3. 6.4. General Description ...................................................................................................................................... 52 Common Configuration Registers ................................................................................................................. 55 Receiver Registers........................................................................................................................................ 58 IRQ and Pin Mapping Registers.................................................................................................................... 60 Page 3 www.semtech.com Rev 2 - April 2010 SX1239 ADVANCED COMMUNICATIONS & SENSING 6.5. 6.6. 6.7. 7. 7.1. 7.2. Packet Engine Registers 62 Temperature Sensor Registers ..................................................................................................................... 65 Test Registers ............................................................................................................................................... 65 Crystal Resonator Specification .................................................................................................................... 66 Reset of the Chip .......................................................................................................................................... 66 DATASHEET Application Information ......................................................................................................................................... 66 7.2.1. POR.......................................................................................................................................................... 66 7.2.2. Manual Reset ............................................................................................................................................ 67 7.3. 8. 8.1. 8.2. 8.3. 8.4. 9. 9.1. 9.2. Reference Design ......................................................................................................................................... 67 Package Outline Drawing.............................................................................................................................. 68 Recommended Land Pattern ........................................................................................................................ 68 Thermal Impedance ...................................................................................................................................... 69 Tape & Reel Specification............................................................................................................................. 69 RC Oscillator Calibration............................................................................................................................... 70 Listen Mode................................................................................................................................................... 70 Packaging Information .......................................................................................................................................... 68 Chip Revisions ...................................................................................................................................................... 70 9.2.1. Resolutions............................................................................................................................................... 70 9.2.2. Exiting Listen Mode .................................................................................................................................. 71 9.3. 9.4. OOK Floor Threshold Default Setting ........................................................................................................... 71 AFC Control .................................................................................................................................................. 71 9.4.1. AfcAutoClearOn ....................................................................................................................................... 71 9.4.2. LowBetaAfcOn and LowBetaAfcOffset..................................................................................................... 71 10. Revision History .................................................................................................................................................... 72 Rev 2 - April 2010 Page 4 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET Index of Figures Page Figure 1. Block Diagram ................................................................................................................................................ 8 Figure 2. Pin Diagram .................................................................................................................................................... 9 Figure 3. Marking Diagram ............................................................................................................................................ 9 Figure 4. TCXO Connection ........................................................................................................................................ 15 Figure 5. Receiver Block Diagram ............................................................................................................................... 17 Figure 6. AGC Thresholds Settings ............................................................................................................................. 19 Figure 7. Cordic Extraction .......................................................................................................................................... 22 Figure 8. OOK Peak Demodulator Description ............................................................................................................ 24 Figure 9. Floor Threshold Optimization ....................................................................................................................... 25 Figure 10. Bit Synchronizer Description ...................................................................................................................... 26 Figure 11. FEI Process ................................................................................................................................................ 27 Figure 12. Optimized Afc (AfcLowBetaOn=1) .............................................................................................................. 28 Figure 13. Temperature Sensor Response ................................................................................................................. 29 Figure 14. Rx Startup - No AGC, no AFC .................................................................................................................... 31 Figure 15. Rx Startup - AGC, no AFC ......................................................................................................................... 31 Figure 16. Rx Startup - AGC and AFC ........................................................................................................................ 31 Figure 17. Listen Mode Sequence (no wanted signal is received) .............................................................................. 33 Figure 18. Listen Mode Sequence (wanted signal is received) ................................................................................... 35 Figure 19. Auto Modes of Packet Handler ................................................................................................................... 36 Figure 20. SX1239 Data Processing Conceptual View ............................................................................................... 37 Figure 21. SPI Timing Diagram (single access) .......................................................................................................... 38 Figure 22. FIFO and Shift Register (SR) ..................................................................................................................... 39 Figure 23. FifoLevel IRQ Source Behavior .................................................................................................................. 40 Figure 24. Sync Word Recognition .............................................................................................................................. 41 Figure 25. Continuous Mode Conceptual View ........................................................................................................... 43 Figure 26. Rx Processing in Continuous Mode ........................................................................................................... 43 Figure 27. Packet Mode Conceptual View ................................................................................................................... 44 Figure 28. Fixed Length Packet Format ...................................................................................................................... 45 Figure 29. Variable Length Packet Format .................................................................................................................. 46 Figure 30. Unlimited Length Packet Format ................................................................................................................ 46 Figure 31. CRC Implementation .................................................................................................................................. 50 Figure 32. Manchester Decoding ................................................................................................................................ 50 Figure 33. Data De-Whitening ..................................................................................................................................... 51 Figure 34. POR Timing Diagram ................................................................................................................................. 66 Figure 35. Manual Reset Timing Diagram ................................................................................................................... 67 Figure 36. Application Schematic ................................................................................................................................ 67 Figure 37. Package Outline Drawing ........................................................................................................................... 68 Figure 38. Recommended Land Pattern ..................................................................................................................... 68 Figure 39. Tape & Reel Specification .......................................................................................................................... 69 Figure 40. Listen Mode Resolutions, V2a ................................................................................................................... 70 Figure 41. Listen Mode Resolution, V2b ..................................................................................................................... 70 Rev 2 - April 2010 Page 5 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET Figure 42. Exiting Listen Mode in SX1239 V2a ........................................................................................................... 71 Figure 43. RegTestOok Description ............................................................................................................................ 71 Index of Tables Page Table 1. SX1239 Pinouts .............................................................................................................................................. 10 Table 2. Absolute Maximum Ratings ............................................................................................................................ 11 Table 3. Operating Range ............................................................................................................................................ 11 Table 4. Power Consumption Specification .................................................................................................................. 12 Table 5. Frequency Synthesizer Specification .............................................................................................................. 12 Table 6. Receiver Specification .................................................................................................................................... 13 Table 7. Digital Specification ........................................................................................................................................ 14 Table 8. LNA Gain Settings .......................................................................................................................................... 18 Table 9. Receiver Performance Summary .................................................................................................................... 19 Table 10. Available RxBw Settings ............................................................................................................................... 21 Table 11. Bit Rate Examples ........................................................................................................................................ 23 Table 12. Basic Receiver Modes .................................................................................................................................. 30 Table 13. Range of Durations in Listen Mode .............................................................................................................. 33 Table 14. Signal Acceptance Criteria in Listen Mode ................................................................................................... 34 Table 15. End of Listen Cycle Actions .......................................................................................................................... 34 Table 16. Status of FIFO when Switching Between Different Modes of the Chip ......................................................... 40 Table 17. DIO Mapping, Continuous Mode .................................................................................................................. 42 Table 18. DIO Mapping, Packet Mode ......................................................................................................................... 42 Table 19. Registers Summary ...................................................................................................................................... 52 Table 20. Common Configuration Registers ................................................................................................................. 55 Table 21. Receiver Registers ....................................................................................................................................... 58 Table 22. IRQ and Pin Mapping Registers ................................................................................................................... 60 Table 23. Packet Engine Registers .............................................................................................................................. 62 Table 24. Temperature Sensor Registers ..................................................................................................................... 65 Table 25. Test Registers .............................................................................................................................................. 65 Table 26. Crystal Specification ..................................................................................................................................... 66 Table 27. Chip Identification ......................................................................................................................................... 70 Table 28. Revision History ............................................................................................................................................ 72 Rev 2 - April 2010 Page 6 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET Acronyms BOM BR BW CCITT CRC DAC ETSI FCC Fdev FIFO FIR FS FSK GUI IC ID IF IRQ ITU LFSR LNA LO Bill Of Materials Bit Rate Bandwidth Comite Consultatif International Telephonique et Telegraphique - ITU Cyclic Redundancy Check Digital to Analog Converter European Telecommunications Standards Institute Federal Communications Commission Frequency Deviation First In First Out Finite Impulse Response Frequency Synthesizer Frequency Shift Keying Graphical User Interface Integrated Circuit IDentificator Intermediate Frequency Interrupt ReQuest International Telecommunication Union Linear Feedback Shift Register Low Noise Amplifier Local Oscillator LSB MSB NRZ OOK PA PCB PLL POR RBW RF RSSI Rx SAW SPI SR Stby Tx uC VCO XO XOR Least Significant Bit Most Significant Bit Non Return to Zero On Off Keying Power Amplifier Printed Circuit Board Phase-Locked Loop Power On Reset Resolution BandWidth Radio Frequency Received Signal Strength Indicator Receiver Surface Acoustic Wave Serial Peripheral Interface Shift Register Standby Transmitter Microcontroller Voltage Controlled Oscillator Crystal Oscillator eXclusive OR Rev 2 - April 2010 Page 7 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET This product datasheet contains a detailed description of the SX1239 performance and functionality. Please consult the Semtech website for the latest updates or errata. Refer to section 9 of this document to identify chip revisions. 1. General Description The SX1239 is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The SX1239's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended for use as high-performance, low-cost FSK and OOK RF receiver for robust frequency agile RF links, and where stable and constant RF performance is required over the full operating range of the device down to 1.8V. The SX1239 is intended for applications over a wide frequency range, including the 433 MHz and 868 MHz European and the 902-928 MHz North American ISM bands. Coupled with a very aggressive sensitivity, the advanced system features of the SX1239 include a 66 byte RX FIFO, configurable automatic packet handler, listen mode, temperature sensor and configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU requirements. The SX1239 complies with both ETSI and FCC regulatory requirements and is available in a 5 x 5 mm QFN 24 lead package 1.1. Simplified Block Diagram VBAT1&2 VR_ANA VR_DIG RC Oscillator / Modulators Demodulator & Bit Synchronizer Decimation and & Filtering RESET Power Distribution System LNA Single to Differential Mixers RFIN Control Registers - Shift Registers - SPI Interface RSSI Division by 2, 4 or 6 AFC Packet Engine & 66 Bytes FIFO SPI GND DIO0 DIO1 DIO2 DIO3 DIO4 Tank Inductor NC NC NC Loop Filter Frac-N PLL Synthesizer XO 32 MHz DIO5 XTAL Frequency Synthesis Receiver Blocks Control Blocks GND Primarily Analog Primarily Digital Figure 1. Block Diagram Rev 2 - April 2010 Page 8 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 1.2. Pin and Marking Diagram The following diagram shows the pin arrangement of the QFN package, top view. DATASHEET Figure 2. Pin Diagram BC Figure 3. Marking Diagram Notes yyww refers to the date code xxxxxx refers to the lot number Rev 2 - April 2010 Page 9 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 1.3. Pin Description Table 1 SX1239 Pinouts Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name GROUND VBAT1 VR_ANA VR_DIG XTA XTB RESET DIO0 DIO1/DCLK DIO2/DATA DIO3 DIO4 DIO5 VBAT2 GND SCK MISO MOSI NSS NC GND RFIN GND NC NC Type I/O I/O I/O I/O O O I/O I/O I/O I O I I I Description Exposed ground pad Supply voltage Regulated supply voltage for analogue circuitry Regulated supply voltage for digital blocks XTAL connection XTAL connection Reset trigger input Digital I/O, software configured Digital Output, software configured Digital Output, software configured Digital I/O, software configured Digital I/O, software configured Digital I/O, software configured Supply voltage Ground SPI Clock input SPI Data output SPI Data input SPI Chip select input Do not connect Ground RF input Ground Do not connect Do not connect DATASHEET Rev 2 - April 2010 Page 10 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET 2. Electrical Characteristics 2.1. ESD Notice The SX1239 is a high performance radio frequency device. Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins. Class B of the JEDEC standard JESD22-A115-A (Machine Model) on all pins. Class IV of the JEDEC standard JESD22-C101C (Charged Device Model) on pins 2-3-21-23-24, Class III on all other pins. It should thus be handled with all the necessary ESD precautions to avoid any permanent damage. 2.2. Absolute Maximum Ratings Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 2 Absolute Maximum Ratings Symbol Description Supply Voltage Temperature Junction temperature RF Input Level Min -0.5 -55 Max 3.9 +115 +125 +6 Unit V C C dBm VDDmr Tmr Tj Pmr 2.3. Operating Range Table 3 Operating Range Symbol VDDop Top Clop ML Supply voltage Operational temperature range Load capacitance on digital ports RF Input Level Description Min 1.8 -40 Max 3.6 +85 25 0 Unit V C pF dBm Rev 2 - April 2010 Page 11 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 2.4. Chip Specification The tables below give the electrical specifications of the receiver under the following conditions: Supply voltage VBAT1= VBAT2=VDD=3.3 V, temperature = 25 C, FXOSC = 32 MHz, FRF = 915 MHz, 2-level FSK modulation without pre-filtering, Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, unless otherwise specified. Note Unless otherwise specified, the performances in the other frequency bands are similar or better. DATASHEET 2.4.1. Power Consumption Table 4 Power Consumption Specification Symbol IDDSL IDDIDLE IDDST IDDFS IDDR Description Supply current in sleep mode Supply current in Idle mode Supply current in standby mode Supply current in synthesizer mode Supply current in receive mode RC oscillator enabled Crystal oscillator enabled Conditions Min Typ 0.1 1.2 1.25 9 16 Max 1 1.5 Unit uA uA mA mA mA 2.4.2. Frequency Synthesis Table 5 Frequency Synthesizer Specification Symbol FR Description Synthesizer Frequency Range Conditions Programmable Min 290 424 862 From Standby mode 200 kHz step 1 MHz step 5 MHz step 7 MHz step 12 MHz step 20 MHz step 25 MHz step FSTEP = FXOSC/219 After calibration Programmable Programmable 1.2 1.2 Typ 32 250 80 20 20 50 50 80 80 80 61.0 62.5 Max 340 510 1020 500 150 300 32.768 Unit MHz MHz MHz MHz us us us us us us us us us Hz kHz kbps kbps FXOSC TS_OSC TS_FS TS_HOP Crystal oscillator frequency Crystal oscillator wake-up time Frequency synthesizer wake-up time to PllLock signal Frequency synthesizer hop time at most 10 kHz away from the target See section 7.1 FSTEP FRC BRF BRO Frequency synthesizer step RC Oscillator frequency Bit rate, FSK Bit rate, OOK Rev 2 - April 2010 Page 12 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 2.4.3. Receiver All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in RegRxBw, receiving a PN15 sequence with a BER of 0.1% (Bit Synchronizer is enabled), unless otherwise specified. The LNA impedance is set to 200 Ohms, by setting bit LnaZin in RegLna to 1. Blocking tests are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR, IIP2, IIP3 and AMR tests is set 3 dB above the nominal sensitivity level. DATASHEET Table 6 Receiver Specification Description FSK sensitivity, highest LNA gain Conditions FDA = 5 kHz, BR = 1.2 kb/s FDA = 5 kHz, BR = 4.8 kb/s FDA = 40 kHz, BR = 38.4 kb/s FDA = 5 kHz, BR = 1.2 kb/s* Min -13 Offset = +/- 25 kHz Offset = +/- 50 kHz Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz Lowest LNA gain Highest LNA gain Lowest LNA gain Highest LNA gain Programmable Wanted signal level = -106 dBm 37 -23 Typ -118 -114 -105 -120 -112 -10 42 42 -45 -40 -32 -36 -33 -25 -45 -40 -32 +75 +35 +20 -18 Max -109 Unit dBm dBm dBm dBm dBm dB dB dB dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm Symbol RFS_F RFS_O CCR ACR OOK sensitivity, highest LNA gain Co-Channel Rejection Adjacent Channel Rejection BR = 4.8 kb/s BI Blocking Immunity Blocking Immunity Wanted signal at sensitivity +16dB AMR AM Rejection , AM modulated interferer with 100% modulation depth, fm = 1 kHz, square 2nd order Input Intercept Point Unwanted tones are 20 MHz above the LO 3rd order Input Intercept point Unwanted tones are 1MHz and 1.995 MHz above the LO Single Side channel filter BW Image rejection in OOK mode Receiver wake-up time, from PLL locked state to RxReady Receiver wake-up time, from PLL locked state, AGC enabled Receiver wake-up time, from PLL lock state, AGC and AFC enabled IIP2 IIP3 BW_SSB IMR_OOK TS_RE TS_RE_AGC TS_RE_AGC &AFC 2.6 27 - 30 1.7 96 3.0 163 4.8 265 500 - kHz dB ms us ms us ms us RxBw = 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s RxBw= 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s RxBw= 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s Rev 2 - April 2010 Page 13 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET TS_FEI TS_AFC TS_RSSI DR_RSSI FEI sampling time AFC Response Time RSSI Response Time RSSI Dynamic Range Receiver is ready Receiver is ready Receiver is ready AGC enabled Min Max - 4.Tbit 4.Tbit 2.Tbit -115 0 - dBm dBm * Set SensitivityBoost in RegTestLna to 0x2D to reduce the noise floor in the receiver 2.4.4. Digital Specification Conditions: Temp = 25C, VDD = 3.3V, FXOSC = 32 MHz, unless otherwise specified. Table 7 Digital Specification Description Digital input level high Digital input level low Digital output level high Digital output level low SCK frequency SCK high time SCK low time SCK rise time SCK fall time MOSI setup time MOSI hold time NSS setup time NSS hold time NSS high time between SPI accesses DATA hold and setup time from MOSI change to SCK rising edge from SCK rising edge to MOSI change from NSS falling edge to SCK rising edge from SCK falling edge to NSS rising edge, normal mode Imax = 1 mA Imax = -1 mA Conditions Min 0.8 0.9 50 50 30 60 30 30 20 250 Typ 5 5 Max 0.2 0.1 10 Unit VDD VDD VDD VDD MHz ns ns ns ns ns ns ns ns ns ns Symbol VIH VIL VOH VOL FSCK tch tcl trise tfall tsetup thold tnsetup tnhold tnhigh T_DATA Rev 2 - April 2010 Page 14 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET 3. Chip Description This section describes in depth the architecture of the SX1239 low-power, highly integrated receiver. 3.1. Power Supply Strategy The SX1239 employs an advanced power supply scheme, which provides stable operating characteristics over the full temperature and voltage range of operation. The SX1239 can be powered from any low-noise voltage source via pins VBAT1 and VBAT2. Decoupling capacitors should be connected, as suggested in the reference design on VR_DIG and VR_ANA pins to ensure a correct operation of the built-in voltage regulators. 3.2. Low Battery Detector A low battery detector is also included allowing the generation of an interrupt signal in response to passing a programmable threshold adjustable through the register RegLowBat. The interrupt signal can be mapped to any of the DIO pins, through the programmation of RegDioMapping. 3.3. Frequency Synthesis The LO generation on the SX1239 is based on a state-of-the-art fractional-N PLL. The PLL is fully integrated with automatic calibration. 3.3.1. Reference Oscillator The crystal oscillator is the main timing reference of the SX1239. It is used as a reference for the frequency synthesizer and as a clock for the digital processing. The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. When using the builtin sequencer, the SX1239 optimizes the startup time and automatically triggers the PLL when the XO signal is stable. To manually control the startup time, the user should either wait for TS_OSC max, or monitor the signal CLKOUT which will only be made available on the output buffer when a stable XO oscillation is achieved. An external clock can be used to replace the crystal oscillator, for instance a tight tolerance TCXO. To do so, bit 4 at address 0x59 should be set to 1, and the external clock has to be provided on XTA (pin 4). XTB (pin 5) should be left open. The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an appropriate value of decoupling capacitor, CD. XTA XTB NC TCXO 32 MHz OP Vcc GND CD Vcc Figure 4. TCXO Connection Rev 2 - April 2010 Page 15 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 3.3.2. CLKOUT Output The reference frequency, or a fraction of it, can be provided on DIO5 (pin 12) by modifying bits ClkOut in RegDioMapping2. Two typical applications of the CLKOUT output include: To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be made available in any operation mode except Sleep mode and is automatically enabled at power on reset. To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the initial crystal tolerance. Note to minimize the current consumption of the SX1239, please ensure that the CLKOUT signal is disabled when not required. DATASHEET 3.3.3. PLL Architecture The frequency synthesizer generating the LO frequency for the receiver is a fractional-N sigma-delta PLL. The PLL incorporates a third order loop capable of fast auto-calibration, and it has a fast switching-time. The VCO and the loop filter are both fully integrated, removing the need for an external tight-tolerance, high-Q inductor in the VCO tank circuit. 3.3.3.1. VCO The VCO runs at 2, 4 or 6 times the RF frequency (respectively in the 915, 434 and 315 MHz bands) to reduce any LO leakage in receiver mode, to improve the quadrature precision of the receiver. The VCO calibration is fully automated. A coarse adjustment is carried out at power on reset, and a fine tuning is performed each time the SX1239 PLL is activated. Automatic calibration times are fully transparent to the end-user, as their processing time is included in the TS_RE specifications. 3.3.3.2. PLL Bandwidth The bandwidth of the SX1239 Fractional-N PLL is wide enough to allow for very fast PLL lock times, enabling both short startup and fast hop times required for frequency agile applications. 3.3.3.3. Carrier Frequency and Resolution The SX1239 PLL embeds a 19-bit sigma-delta modulator and its frequency resolution, constant over the whole frequency range, and is given by: F XOSC F STEP = --------------19 2 The carrier frequency is programmed through RegFrf, split across addresses 0x07 to 0x09: F RF = F STEP x Frf (23,0) Note The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the least significant byte FrfLsb in RegFrfLsb is written. Rev 2 - April 2010 Page 16 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 3.3.4. Lock Time PLL lock time TS_FS is a function of a number of technical factors, such as synthesized frequency, frequency step, etc. When using the built-in sequencer, the SX1239 optimizes the startup time and automatically starts the receiver when the PLL has locked. To manually control the startup time, the user should either wait for TS_FS max given in the specification, or monitor the signal PLL lock detect indicator, which is set when the PLL has is within its locking range. When performing an AFC, which usually corrects very small frequency errors, the PLL response time is approximately: 5T PLLAFC = ------------------PLLBW DATASHEET In a frequency hopping scheme, the timings TS_HOP given in the table of specifications give an order of magnitude for the expected lock times. 3.3.5. Lock Detect Indicator A lock indication signal can be made available on some of the DIO pins, and is toggled high when the PLL reaches its locking range. Please refer to Table 17 and Table 18 to map this interrupt to the desired pins. 3.4. Receiver Description The SX1239 features a digital receiver with the analog to digital conversion process being performed directly following the LNA-Mixers block. The zero-IF receiver is able to handle (G)FSK and (G)MSK modulation. ASK and OOK modulation is, however, demodulated by a low-IF architecture. All the filtering, demodulation, gain control, synchronization and packet handling is performed digitally, which allows a very wide range of bit rates and frequency deviations to be selected. The receiver is also capable of automatic gain calibration in order to improve precision on RSSI measurements. 3.4.1. Block Diagram Rx Calibration Reference LNA Single to Differential RFIN Mixers / Modulators CORDIC Complex Filter Phase Output FSK Demodulator Channel Filter Decimator DC Cancellation Module Output Bypassed in FSK AFC RSSI OOK Demodulator Local Oscillator AGC Figure 5. Receiver Block Diagram The following sections give a brief description of each of the receiver blocks. Rev 2 - April 2010 Page 17 www.semtech.com Processing SX1239 ADVANCED COMMUNICATIONS & SENSING 3.4.2. LNA - Single to Differential Buffer The LNA uses a common-gate topology, which allows for a flat characteristic over the whole frequency range. It is designed to have an input impedance of 50 Ohms or 200 Ohms (as selected with bit LnaZin in RegLna), and the parasitic capacitance at the LNA input port is cancelled with the external RF choke. A single to differential buffer is implemented to improve the second order linearity of the receiver. The LNA gain, including the single-to-differential buffer, is programmable over a 48 dB dynamic range, and control is either manual or automatic with the embedded AGC function. Note In the specific case where the LNA gain is manually set by the user, the receiver will not be able to properly handle FSK signals with a modulation index smaller than 2 at an input power greater than the 1dB compression point, tabulated in section 3.4.3. DATASHEET Table 8 LNA Gain Settings LnaGainSelect 000 001 010 011 100 101 110 111 LNA Gain Any of the below, set by the AGC loop Max gain Max gain - 6 dB Max gain - 12 dB Max gain - 24 dB Max gain - 36 dB Max gain - 48 dB Reserved Gain Setting G1 G2 G3 G4 G5 G6 - 3.4.3. Automatic Gain Control By default (LnaGainSelect = 000), the LNA gain is controlled by a digital AGC loop in order to obtain the optimal sensitivity/ linearity trade-off. Regardless of the data transfer mode (Packet or Continuous), the following series of events takes place when the receiver is enabled: The receiver stays in WAIT mode, until RssiValue exceeds RssiThreshold for two consecutive samples. Its power consumption is the receiver power consumption. When this condition is satisfied, the receiver automatically selects the most suitable LNA gain, optimizing the sensitivity/ linearity trade-off. The programmed LNA gain, read-accessible with LnaCurrentGain in RegLna, is carried on for the whole duration of the packet, until one of the following conditions is fulfilled: Packet mode: if AutoRxRestartOn = 0, the LNA gain will remain the same for the reception of the following packet. If AutoRxRestartOn = 1, after the controller has emptied the FIFO the receiver will re-enter the WAIT mode described above, after a delay of InterPacketRxDelay, allowing for the distant transmitter to ramp down, hence avoiding a false RSSI detection. Continuous mode: upon reception of valid data, the user can decide to either leave the receiver enabled with the same LNA gain, or to restart the procedure, by setting RestartRx bit to 1, resuming the WAIT mode of the receiver, described above. Notes - the AGC procedure must be performed while receiving preamble in FSK mode - in OOK mode, the AGC will give better results if performed while receiving a constant "1" sequence Rev 2 - April 2010 Page 18 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING The following figure illustrates the AGC behavior:: DATASHEET Re fe re nc e hr es h3 hr es h4 Ag cT hr es h Ag cT hr es h Towards -125 dBm AG C Ag cT h Ag cT Ag cT re s h5 1 2 16dB 7dB 11dB 9dB 11dB Pin [dBm] G1 G2 G3 G4 G5 G6 Higher Sensitivity Lower Linearity Lower Noise Figure Lower Sensitivity Higher Linearity Higher Noise Figure Figure 6. AGC Thresholds Settings The following table summarizes the performance (typical figures) of the complete receiver: Table 9 Receiver Performance Summary Input Power Pin Pin < AgcThresh1 AgcThresh1 < Pin < AgcThresh2 AgcThresh2 < Pin < AgcThresh3 AgcThresh3 < Pin < AgcThresh4 AgcThresh4 < Pin < AgcThresh5 AgcThresh5 < Pin Gain Setting G1 G2 G3 G4 G5 G6 P-1dB [dBm] -37 -31 -26 -14 >-6 >0 Receiver Performance (typ) NF IIP3 IIP2 [dB] [dBm] [dBm] 7 13 18 27 36 44 -18 -15 -8 -1 +13 +20 +35 +40 +48 +62 +68 +75 3.4.3.1. RssiThreshold Setting For correct operation of the AGC, RssiThreshold in RegRssiThresh must be set to the sensitivity of the receiver. The receiver will remain in WAIT mode until RssiThreshold is exceeded. Note When AFC is enabled and performed automatically at the receiver startup, the channel filter used by the receiver during the AFC and the AGC is RxBwAfc instead of the standard RxBw setting. This may impact the sensitivity of the receiver, and the setting of RssiThreshold accordingly 3.4.3.2. AGC Reference The AGC reference level is automatically computed in the SX1239, according to: AGC Reference [dBm] = -174 + NF + DemodSnr +10.log(2*RxBw) + FadingMargin [dBm] Rev 2 - April 2010 Page 19 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING With: NF = 7dB DemodSnr = 8 dB RxBw DATASHEET : LNA's Noise Figure at maximum gain : SNR needed by the demodulator : Single sideband channel filter bandwidth FadingMargin = 5 dB : Fading margin 3.4.4. Quadrature Mixer - ADCs - Decimators The mixer is inserted between output of the RF buffer stage and the input of the analog to digital converter (ADC) of the receiver section. This block is designed to translate the spectrum of the input RF signal to base-band, and offer both high IIP2 and IIP3 responses. In the lower bands of operation (290 to 510 MHz), the multi-phase mixing architecture with weighted phases improves the rejection of the LO harmonics in receiver mode, hence increasing the receiver immunity to out-of-band interferers. The I and Q digitalization is made by two 5th order continuous-time Sigma-Delta Analog to Digital Converters (ADC). Their gain is not constant over temperature, but the whole receiver is calibrated before reception, so that this inaccuracy has no impact on the RSSI precision. The ADC output is one bit per channel. It needs to be decimated and filtered afterwards. This ADC can also be used for temperature measurement, please refer to section 3.4.17 for more details. The decimators decrease the sample rate of the incoming signal in order to optimize the area and power consumption of the following receiver blocks. 3.4.5. Channel Filter The role of the channel filter is to filter out the noise and interferers outside of the channel. Channel filtering on the SX1239 is implemented with a 16-tap Finite Impulse Response (FIR) filter, providing an outstanding Adjacent Channel Rejection performance, even for narrowband applications. Note to respect oversampling rules in the decimation chain of the receiver, the Bit Rate cannot be set at a higher value than 2 times the single-side receiver bandwidth (BitRate < 2 x RxBw) The single-side channel filter bandwidth RxBw is controlled by the parameters RxBwMant and RxBwExp in RegRxBw: When FSK modulation is enabled: FXOSC RxBw = ----------------------------------------------------------------RxBwExp + 2 RxBwMant x 2 When OOK modulation is enabled: FXOSC RxBw = ----------------------------------------------------------------RxBwExp + 3 RxBwMant x 2 The following channel filter bandwidths are accessible (oscillator is mandated at 32 MHz): Rev 2 - April 2010 Page 20 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING Table 10 Available RxBw Settings RxBwMant (binary/value) 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 RxBwExp (decimal) 7 7 7 6 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 0 0 0 RxBw (kHz) FSK OOK ModulationType=00 ModulationType=01 2.6 1.3 3.1 1.6 3.9 2.0 5.2 2.6 6.3 3.1 7.8 3.9 10.4 5.2 12.5 6.3 15.6 7.8 20.8 10.4 25.0 12.5 31.3 15.6 41.7 20.8 50.0 25.0 62.5 31.3 83.3 41.7 100.0 50.0 125.0 62.5 166.7 83.3 200.0 100.0 250.0 125.0 333.3 166.7 400.0 200.0 500.0 250.0 DATASHEET 3.4.6. DC Cancellation DC cancellation is required in zero-IF architecture receivers to remove any DC offset generated through self-reception. It is built-in the SX1239 and its adjustable cutoff frequency fc is controlled in RegRxBw: 4 x RxBw fc = ----------------------------------------DccFreq + 2 2 x 2 The default value of DccFreq cutoff frequency is typically 4% of the RxBw (channel filter BW). The cutoff frequency of the DCC can however be increased to slightly improve the sensitivity, under wider modulation conditions. It is advised to adjust the DCC setting while monitoring the receiver sensitivity. 3.4.7. Complex Filter - OOK In OOK mode the SX1239 is modified to a low-IF architecture. The IF frequency is automatically set to half the single side bandwidth of the channel filter (FIF = 0.5 x RxBw). The Local Oscillator is automatically offset by the IF in the OOK receiver. A complex filter is implemented on the chip to attenuate the resulting image frequency by typically 30 dB. Note this filter is automatically bypassed when receiving FSK signals (ModulationType = 00 in RegDataModul). Page 21 www.semtech.com Rev 2 - April 2010 SX1239 ADVANCED COMMUNICATIONS & SENSING 3.4.8. RSSI The RSSI block evaluates the amount of energy available within the receiver channel bandwidth. Its resolution is 0.5 dB, and it has a wide dynamic range to accommodate both small and large signal levels that may be present. Its acquisition time is very short, taking only 2 bit periods. The RSSI sampling must occur during the reception of preamble in FSK, and constant "1" reception in OOK. Note - The receiver is capable of automatic gain calibration, in order to improve the precision of its RSSI measurements. This function injects a known RF signal at the LNA input, and calibrates the receiver gain accordingly. This calibration is automatically performed during the PLL start-up, making it a transparent process to the end-user. - RssiValue can only be read when it exceeds RssiThreshold DATASHEET 3.4.9. Cordic The Cordic task is to extract the phase and the amplitude of the modulation vector (I+j.Q). This information, still in the digital domain is used: Phase output: used by the FSK demodulator and the AFC blocks. Amplitude output: used by the RSSI block, for FSK demodulation, AGC and automatic gain calibration purposes. Real-time Magnitude Q(t) Real-time Phase I(t) Figure 7. Cordic Extraction 3.4.10. Bit Rate Setting The Bit Rate (BR) is controlled by bits BitRate in RegBitrate: F XOSC BR = ------------------BitRate Amongst others, the following Bit Rates are accessible: Rev 2 - April 2010 Page 22 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING Table 11 Bit Rate Examples Type Classical modem baud rates (multiples of 1.2 kbps) BitRate (15:8) 0x68 0x34 0x1A 0x0D 0x06 0x03 0x01 0x00 Classical modem baud rates (multiples of 0.9 kbps) Round bit rates (multiples of 12.5, 25 and 50 kbps) 0x02 0x01 0x0A 0x05 0x02 0x01 0x00 0x00 0x00 0x00 Watch Xtal frequency 0x03 BitRate (7:0) 0x2B 0x15 0x0B 0x05 0x83 0x41 0xA1 0xD0 0x2C 0x16 0x00 0x00 0x80 0x40 0xD5 0xA0 0x80 0x6B 0xD1 (G)FSK (G)MSK 1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps 38.4 kbps 76.8 kbps 153.6 kbps 57.6 kbps 115.2 kbps 12.5 kbps 25 kbps 50 kbps 100 kbps 150 kbps 200 kbps 250 kbps 300 kbps 32.768 kbps 32.768 kbps 12.5 kbps 25 kbps OOK 1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps Actual BR (b/s) 1200.015 2400.060 4799.760 9600.960 19196.16 38415.36 76738.60 153846.1 57553.95 115107.9 12500.00 25000.00 50000.00 100000.0 150234.7 200000.0 250000.0 299065.4 32753.32 DATASHEET 3.4.11. FSK Demodulator The FSK demodulator of the SX1239 is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals. It is most efficient when the modulation index of the signal is greater than 0.5 and below 10: 2 x F DEV 0.5 = ---------------------- 10 BR The output of the FSK demodulator can be fed to the Bit Synchronizer (described in section 3.4.13), to provide the companion processor with a synchronous data stream in Continuous mode. Rev 2 - April 2010 Page 23 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 3.4.12. OOK Demodulator The OOK demodulator performs a comparison of the RSSI output and a threshold value. Three different threshold modes are available, configured through bits OokThreshType in RegOokPeak. The recommended mode of operation is the "Peak" threshold mode, illustrated in Figure 8: RSSI [dBm] `'Peak -6dB'' Threshold DATASHEET `'Floor'' threshold defined by OokFixedThresh Noise floor of receiver Time Zoom Zoom Decay in dB as defined in OokPeakThreshStep Fixed 6dB difference Period as defined in OokPeakThreshDec Figure 8. OOK Peak Demodulator Description In peak threshold mode the comparison threshold level is the peak value of the RSSI, reduced by 6dB. In the absence of an input signal, or during the reception of a logical "0", the acquired peak value is decremented by one OokPeakThreshStep every OokPeakThreshDec period. When the RSSI output is null for a long time (for instance after a long string of "0" received, or if no transmitter is present), the peak threshold level will continue falling until it reaches the "Floor Threshold", programmed in OokFixedThresh. The default settings of the OOK demodulator lead to the performance stated in the electrical specification. However, in applications in which sudden signal drops are awaited during a reception, the three parameters should be optimized accordingly. 3.4.12.1. Optimizing the Floor Threshold OokFixedThresh determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals (i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly. Rev 2 - April 2010 Page 24 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING Note that the noise floor of the receiver at the demodulator input depends on: The noise figure of the receiver. The gain of the receive chain from antenna to base band. The matching - including SAW filter if any. The bandwidth of the channel filters. It is therefore important to note that the setting of OokFixedThresh will be application dependant. The following procedure is recommended to optimize OokFixedThresh. Set SX1239 in OOK Rx mode Adjust Bit Rate, Channel filter BW Default OokFixedThresh setting No input signal Continuous Mode DATASHEET Monitor DIO2/DATA pin Increment OokFixedThresh Glitch activity on DATA ? Optimization complete Figure 9. Floor Threshold Optimization The new floor threshold value found during this test should be used for OOK reception with those receiver settings. 3.4.12.2. Optimizing OOK Demodulator for Fast Fading Signals A sudden drop in signal strength can cause the bit error rate to increase. For applications where the expected signal drop can be estimated, the following OOK demodulator parameters OokPeakThreshStep and OokPeakThreshDec can be optimized as described below for a given number of threshold decrements per bit. Refer to RegOokPeak to access those settings. 3.4.12.3. Alternative OOK Demodulator Threshold Modes In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold detectors: Fixed Threshold: The value is selected through OokFixedThresh Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with DC-free encoded data. Rev 2 - April 2010 Page 25 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 3.4.13. Bit Synchronizer The Bit Synchronizer is a block that provides a clean and synchronized digital output, free of glitches. Its output is made available on pin DIO1/DCLK in Continuous mode and can be disabled through register settings. However, for optimum receiver performance its use when running Continuous mode is strongly advised. The Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by BitRateMsb and BitRateLsb in RegBitrate. Raw demodulator output (FSK or OOK) DATASHEET DATA BitSync Output To pin DATA and DCLK in continuous mode DCLK Figure 10. Bit Synchronizer Description To ensure correct operation of the Bit Synchronizer, the following conditions have to be satisfied: A preamble (0x55 or 0xAA) of 12 bits is required for synchronization (from the RxReady interrupt) The subsequent payload bit stream must have at least one transition form '0' to '1' or '1' to '0 every 16 bits during data transmission The bit rate matching between the transmitter and the receiver must be better than 6.5 %. Notes - If the Bit Rates of Transmitter and Receiver are known to be the same, the SX1239 will be able to receive an infinite unbalanced sequence (all "0s" or all "1s") with no restriction. - If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the BitSync can withstand can be estimated as follows: - This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily achievable (crystal tolerance is in the range of 50 to 100 ppm). 3.4.14. Frequency Error Indicator This function provides information about the frequency error of the local oscillator (LO) compared with the carrier frequency of a modulated signal at the input of the receiver. When the FEI block is launched, the frequency error is measured and the Rev 2 - April 2010 Page 26 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET signed result is loaded in FeiValue in RegFei, in 2's complement format. The time required for an FEI evaluation is 4 times the bit period. To ensure a proper behavior of the FEI: The operation must be done during the reception of preamble The sum of the frequency offset and the 20 dB signal bandwidth must be lower than the base band filter bandwidth The 20 dB bandwidth of the signal can be evaluated as follows (double-side bandwidth): BR BW 20dB = 2 x F DEV + ------ 2 The frequency error, in Hz, can be calculated with the following formula: FEI = F STEP x FeiValue SX1239 in Rx mode Preamble-modulated input signal Signal level > Sensitivity Set FeiStart =1 FeiDone =1 Yes No Read FeiValue Figure 11. FEI Process 3.4.15. Automatic Frequency Correction The AFC is based on the FEI block, and therefore the same input signal and receiver setting conditions apply. When the AFC procedure is done, AfcValue is directly subtracted to the register that defines the frequency of operation of the chip, FRF. The AFC can be launched: Each time the receiver is enabled, if AfcAutoOn = 1 Upon user request, by setting bit AfcStart in RegAfcFei, if AfcAutoOn = 0 Rev 2 - April 2010 Page 27 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING When the AFC is automatically triggered (AfcAutoOn = 1), the user has the option to: Clear the former AFC correction value, if AfcAutoClearOn = 1 Start the AFC evaluation from the previously corrected frequency. This may be useful in systems in which the LO keeps on drifting in the "same direction". Ageing compensation is a good example. The SX1239 offers an alternate receiver bandwidth setting during the AFC phase, to accommodate large LO drifts. If the user considers that the received signal may be out of the receiver bandwidth, a higher channel filter bandwidth can be programmed in RegAfcBw, at the expense of the receiver noise floor, which will impact upon sensitivity. DATASHEET 3.4.16. Optimized Setup for Low Modulation Index Systems For wide band systems, where AFC is usually not required (XTAL inaccuracies do not typically impact the sensitivity), it is recommended to offset the LO frequency of the receiver to avoid desensitization. This can be simply done by modifying Frf in RegFrfLsb. A good rule of thumb is to offset the receiver's LO by 10% of the expected transmitter frequency deviation. For narrow band systems, it is recommended to perform AFC. The SX1239 has a dedicated AFC, enabled when AfcLowBetaOn in RegAfcCtrl is set to 1. A frequency offset, programmable through LowBetaAfcOffset in RegTestAfc, is added and is calculated as follows: Offset = LowBetaAfcOffset x 488 Hz The user should ensure that the programmed offset exceeds the DC canceller's cutoff frequency, set through DccFreqAfc in RegAfcBw. RX TX Standard AFC AfcLowBetaOn = 0 RX & TX AfcValue FeiValue f RX TX Optimized AFC AfcLowBetaOn = 1 f TX RX AfcValue LowBetaAfcOffset FeiValue f Before AFC After AFC f Figure 12. Optimized Afc (AfcLowBetaOn=1) As shown on Figure 12, a standard AFC sequence uses the result of the FEI to correct the LO frequency and align both local oscillators. When the optimized AFC is enabled (AfcLowBetaOn=1), the receiver's LO is corrected by "FeiValue + LowBetaAfcOffset". When the optimized AFC routine is enabled, the receiver startup time can be computed as follows (refer to section 4.2.1): TS_RE_AGC&AFC (optimized AFC) = Tana + 4.Tcf + 4.Tdcc + 3.Trssi + 2.Tafc + 2.Tpllafc Rev 2 - April 2010 Page 28 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 3.4.17. Temperature Sensor When temperature is measured, the receiver ADC is used to digitize the sensor response. Most receiver blocks are disabled, and temperature measurement can only be triggered in Standby or Frequency Synthesizer modes. The response of the temperature sensor is -1C / Lsb. A CMOS temperature sensor is not accurate by nature, therefore it should be calibrated at ambient temperature for precise temperature readings. TempValue DATASHEET -1C/Lsb TempValue(t) TempValue(t)-1 Returns 150d (typ.) Needs calibration -40C t t+1 Ambient +85C Figure 13. Temperature Sensor Response It takes less than 100 microseconds for the SX1239 to evaluate the temperature (from setting TempMeasStart to 1 to TempMeasRunning reset). 3.4.18. Timeout Function The SX1239 includes a Timeout function, which allows it to automatically shut-down the receiver after a receive sequence and therefore save energy. Timeout interrupt is generated TimeoutRxStart x 8 x Tbit after switching to RX mode if RssiThreshold flag does not raise within this time frame Timeout interrupt is generated TimeoutRssiThresh x 8 x Tbit after RssiThreshold flag has been raised. This timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power mode. Rev 2 - April 2010 Page 29 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET 4. Operating Modes 4.1. Basic Modes The circuit can be set in 4 different basic modes which are described in Table 12. By default, when switching from a mode to another one, the sub-blocks are woken up according to a pre-defined and optimized sequence. Alternatively, these operating modes can be selected directly by disabling the automatic sequencer (SequencerOff in RegOpMode = 1). Table 12 Basic Receiver Modes ListenOn in RegOpMode 0 0 0 0 1 Mode in RegOpMode 000 001 010 100 x Selected mode Sleep Mode Stand-by Mode FS Mode Receive Mode Listen Mode Enabled blocks None Top regulator and crystal oscillator Frequency synthesizer Frequency synthesizer and receiver See Listen Mode, section 4.3 4.2. Automatic Sequencer and Wake-Up Times By default, when switching from one operating mode to another, the circuit takes care of the sequence of events in such a way that the transition timing is optimized. For example, when switching from Sleep mode to Receive mode, the SX1239 goes first to Standby mode (XO started), then to frequency synthesizer mode, and finally, when the PLL has locked, to Receive mode. The crystal oscillator wake-up time, TS_OSC, is directly related to the time for the crystal oscillator to reach its steady state. It depends notably on the crystal characteristics. The frequency synthesizer wake-up time, TS_FS, is directly related to the time needed by the PLL to reach its steady state. The signal PLL_LOCK, provided on an external pin, gives an indication of the lock status. It goes high when the PLL reaches its locking range. Three specific cases can be highlighted: Receiver Wake Up time from Sleep mode Receiver Wake Up time from Sleep mode, AGC enabled Receiver Wake Up time from Sleep mode, AGC and AFC enabled These timings are details in section 4.2.1. In applications where the target average power consumption, or the target startup time, do not require setting the SX1239 in the lowest power modes (Sleep or Standby), the respective timings TS_OSC and TS_FS in the former equations can be omitted. = TS_OSC + TS_FS + TS_RE = TS_OSC + TS_FS + TS_RE_AGC = TS_OSC + TS_FS + TS_RE_AGC&AFC 4.2.1. Receiver Startup Time It is highly recommended to use the built-in sequencer of the SX1239, to optimize the delays when setting the chip in receive mode. It guarantees the shortest startup times, hence the lowest possible energy usage, for battery operated systems. The startup times of the receiver can be calculated from the following: Rev 2 - April 2010 Page 30 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET Rx startup request (sequencer or user) TS_RE Analog FE's group delay Tana Channel Filter's group delay Tcf DC Cutoff's group delay Tdcc RSSI sampling Trssi RSSI sampling Trssi Reception of Packet XO Started and PLL is locked ModeReady RxReady Figure 14. Rx Startup - No AGC, no AFC Rx startup request (sequencer or user) The LNA gain is adjusted by the AGC, according to the RSSI result TS_RE_AGC Analog FE's group delay Tana Channel Filter's group delay Tcf DC Cutoff's group delay Tdcc RSSI sampling Trssi RSSI sampling Trssi Channel Filter's group delay Tcf DC Cutoff's group delay Tdcc RSSI sampling Trssi XO Started and PLL is locked Reception of Packet ModeReady RxReady Figure 15. Rx Startup - AGC, no AFC Rx startup request (sequencer or user) The LNA gain is adjusted by the AGC, according to the RSSI result Carrier Frequency is adjusted by the AFC TS_RE_AGC&AFC Analog FE's group delay Tana Channel Filter's group delay Tcf DC Cutoff's group delay Tdcc RSSI sampling Trssi RSSI sampling Trssi Channel Filter's group delay Tcf DC Cutoff's group delay Tdcc RSSI sampling Trssi XO Started and PLL is locked AFC Tafc PLL lock Tpllafc Channel Filter's group delay Tcf DC Cutoff's group delay Tdcc Reception of Packet ModeReady RxReady Figure 16. Rx Startup - AGC and AFC The different timings shown above are as follows: Group delay of the analog front end: Channel filter's group delay in FSK mode: Channel filter's group delay in OOK mode: DC Cutoff's group delay: PLL lock time after AFC adjustment: AFC sample time: RSSI sample time: Note Tana = 20 us Tcf = 21 / (4.RxBw) Tcf = 34 / (4.RxBw) Tdcc = max(8 , 2^(round(log2(8.RxBw.Tbit)+1)) / (4.RxBw) Tpllafc = 5 / PLLBW (PLLBW = 300 kHz) Tafc = 4 x Tbit (also denoted TS_AFC in the general specification) (aka TS_RSSI) Trssi = 2 x int(4.RxBw.Tbit)/(4.RxBw) The above timings represent maximum settling times, and shorter settling times may be observed in real cases Rev 2 - April 2010 Page 31 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 4.2.2. Rx Start Procedure As described in the former sections, the RxReady interrupt warns the uC that the receiver is ready. In Continuous mode with Bit Synchronizer, the receiver will start locking its Bit Synchronizer on a minimum or 12 bits of received preamble (see section 3.4.13 for details), before the reception of correct Data, or Sync Word (if enabled) can occur. In Continuous mode without Bit Synchronizer, valid data will be available on DIO2/DATA right after the RxReady interrupt. In Packet mode, the receiver will start locking its Bit Synchronizer on a minimum or 12 bits of received preamble (see section 3.4.13 for details), before the reception of correct Data, or Sync Word (if enabled) can occur. DATASHEET 4.2.3. Optimized Frequency Hopping Sequences In a frequency hopping-like application, it is required to turn off the receiver when hopping from one channel to another, to optimize the hopping sequence: Receiver hop from Ch A to Ch B: (0) SX1239 is in Rx mode in Ch A (1) Change the carrier frequency in the RegFrf registers (2) Program the SX1239 in FS mode (3) Turn the receiver back to Rx mode (4) Respect the Rx start procedure, described in section 4.2.4 Note the above sequence assumes that the sequencer is turned on (SequencerOff=0 in RegOpMode). Rev 2 - April 2010 Page 32 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 4.3. Listen mode The circuit can be set to Listen mode, by setting ListenOn in RegOpMode to 1. In this mode, SX1239 spends most of the time in Idle mode, during which only the RC oscillator runs. Periodically the receiver is woken up and listens for an RF signal. If a wanted signal is detected, the receiver is kept on and the data is demodulated. Otherwise, if a wanted signal hasn't been detected after a pre-defined period of time, the receiver is disabled until the next time period. This periodical Rx wake-up requirement is very common in low power applications. On SX1239 it is handled locally by the Listen mode block without using uC resources or energy. The simplified timing diagram of this procedure is illustrated in Figure 17. DATASHEET tListenIdle Rx Idle Rx time tListenRx tListenRx Figure 17. Listen Mode Sequence (no wanted signal is received) 4.3.1. Timings The duration of the Idle phase is given by tListenIdle. The time during which the receiver is on and waits for a signal is given by tListenRx. tListenRx includes the wake-up time of the receiver, described in section 4.2.1. This duration can be programmed in the configuration registers via the serial interface. Both time periods tListenRx and tListenIdle (denoted tListenX in the following text) are fixed by two parameters from the configuration register and are calculated as follows: t ListenX = ListenCoefX Listen Re solX where ListenResolX is the Rx or Idle resolution and is independantly programmable on three values (64us, 4.1ms or 262ms), whereas ListenCoefX is an integer between 1 and 255. All parameters are located in RegListen registers. The timing ranges are tabulated in Table 13 below. Table 13 Range of Durations in Listen Mode ListenResolX Min duration ( ListenCoef = 1 ) Max duration ( ListenCoef = 255 ) 01 10 11 64 us 4.1 ms 0.26 s 16 ms 1.04 s 67 s Rev 2 - April 2010 Page 33 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING Notes - the accuracy of the typical timings given in Table 13 will depend in the RC oscillator calibration - RC oscillator calibration is required, and must be performed at power up. See section 9.1 for details DATASHEET 4.3.2. Criteria The criteria taken for detecting a wanted signal and hence deciding to maintain the receiver on is defined by ListenCriteria in RegListen1. Table 14 Signal Acceptance Criteria in Listen Mode ListenCriteria Input Signal Power >= RssiThreshold SyncAddressMatch 0 1 Required Required Not Required Required 4.3.3. End of Cycle Actions The action taken after detection of a packet, is defined by ListenEnd in RegListen3, as described in the table below. Table 15 End of Listen Cycle Actions ListenEnd Description 00 01 10 Chip stays in Rx mode. Listen mode stops and must be disabled. Chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. It then goes to the mode defined by Mode. Listen mode stops and must be disabled. Chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. Listen mode then resumes in Idle state. FIFO content is lost at next Rx wakeup. Rev 2 - April 2010 Page 34 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING Upon detection of a valid packet, the sequencing is altered, as shown below: PayloadReady ListenCriteria passed DATASHEET Idle ListenEnd = 00 Listen Mode Rx Idle ListenEnd = 01 Listen Mode Rx Mode Idle ListenEnd = 10 Listen Mode Rx Idle Rx Figure 18. Listen Mode Sequence (wanted signal is received) Listen mode can be disabled by writing ListenOn to 0 4.3.4. RC Timer Accuracy All timings of the Listen Mode rely on the accuracy of the internal low-power RC oscillator. This oscillator is automatically calibrated at the device power-up, and it is a user-transparent process. For applications enduring large temperature variations, and for which the power supply is never removed, RC calibration can be performed upon user request. RcCalStart in RegOsc1 can be used to trigger this calibration, and the flag RcCalDone will be set automatically when the calibration is over. Rev 2 - April 2010 Page 35 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 4.4. AutoModes Automatic modes of packet handler can be enabled by configuring the related parameters in RegAutoModes. The intermediate mode of the chip is called IntermediateMode and the enter and exit conditions to/from this intermediate mode can be configured through the parameters EnterCondition & ExitCondition. The enter and exit conditions cannot be used independently of each other i.e. both should be enabled at the same time. The initial and the final state is the one configured in the Mode in RegOpMode. The initial & final states can be different by configuring the modes register while the chip is in intermediate mode. The pictorial description of the auto modes is shown below. Intermediate State defined by IntermediateMode EnterCondition Initial state defined By Mode in RegOpMode ExitCondition Final state defined By Mode in RegOpMode DATASHEET Figure 19. Auto Modes of Packet Handler Some typical examples of AutoModes usage are described below : Automatic reception (AutoRx) : Mode = Rx, IntermediateMode = Sleep, EnterCondition = CrcOk, ExitCondition = falling edge of FifoNotEmpty ... Rev 2 - April 2010 Page 36 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET 5. Data Processing 5.1. Overview 5.1.1. Block Diagram Figure below illustrates the SX1239 data processing circuit. Its role is to interface the data from the demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers. The circuit contains several control blocks which are described in the following paragraphs. Rx CONTROL DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 Data Rx SYNC RECOG. PACKET HANDLER FIFO (+SR) SPI NSS SCK MOSI MISO Potential datapaths (data operation mode dependant) Figure 20. SX1239 Data Processing Conceptual View The SX1239 implements several data operation modes, each with their own data path through the data processing section. Depending on the data operation mode selected, some control blocks are active whilst others remain disabled. 5.1.2. Data Operation Modes The SX1239 has two different data operation modes selectable by the user: Continuous mode: each bit received is accessed in real time at the DIO2/DATA pin. This mode may be used if adequate external signal processing is available. Packet mode (recommended): user only retrieves payload bytes from the FIFO. The packet engine automatically removes the preamble, checks the Sync word, performs AES decryption, checks the CRC, and decodes DC-free schemes if enabled. The uC processing overhead is hence significantly reduced compared to Continuous mode. Depending on the optional features activated (CRC, AES, etc) the maximum payload length is limited to FIFO size, 255 bytes or unlimited. Each of these data operation modes is described fully in the following sections. Rev 2 - April 2010 Page 37 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 5.2. Control Block Description 5.2.1. SPI Interface The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented. Three access modes to the registers are provided: SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access. The NSS pin goes low at the begin of the frame and goes high after the data byte. BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally between each data byte. This mode is available for both read and write accesses. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer. FIFO access: if the address byte corresponds to the address of the FIFO, then succeeding data byte will address the FIFO. The address is not automatically incremented but is memorized and does not need to be sent between each data byte. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer. Figure below shows a typical SPI single access to a register. DATASHEET Figure 21. SPI Timing Diagram (single access) MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the rising edge of SCK. MISO is generated by the slave on the falling edge of SCK. A transfer always starts by the NSS pin going low. MISO is high impedance when NSS is high. The first byte is the address byte. It is made of: wnr bit, which is 1 for write access and 0 for read access 7 bits of address, MSB first The second byte is a data byte, either sent on MOSI by the master in case of a write access, or received by the master on MISO in case of read access. The data byte is transmitted MSB first. Proceeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without rising NSS and re-sending the address. In FIFO mode, if the address was the FIFO address then the bytes will be read at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented at each new byte received. Rev 2 - April 2010 Page 38 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is actually a special case of FIFO / BURST mode with only 1 data byte transferred. During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written register before the write operation. 5.2.2. FIFO 5.2.2.1. Overview and Shift Register (SR) In packet mode of operation, data that has been received is stored in a configurable FIFO (First In First Out) device. It is accessed via the SPI interface and provides several interrupts for transfer management. The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A shift register is therefore employed to interface the two devices. In Rx the shift register gets bit by bit data from the demodulator and writes them byte by byte to the FIFO. This is illustrated in Figure 22. byte1 byte0 Rx Data 1 MSB LSB FIFO 8 SR (8bits) Figure 22. FIFO and Shift Register (SR) Note When switching to Sleep mode, the FIFO can only be used once the ModeReady flag is set (quasi immediate from all modes) 5.2.2.2. Size The FIFO size is fixed to 66 bytes. 5.2.2.3. Interrupt Sources and Flags FifoNotEmpty: FifoNotEmpty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high. Note that when retrieving data from the FIFO, FifoNotEmpty is updated on NSS falling edge, i.e. when FifoNotEmpty is updated to low state the currently started read operation must be completed. In other words, FifoNotEmpty state must be checked after each read operation for a decision on the next one (FifoNotEmpty = 1: more byte(s) to read; FifoNotEmpty = 0: no more byte to read). FifoFull: Fifofull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low. FifoOverrunFlag: FifoOverrunFlag is set when a new byte is written by the SR while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will also be cleared. FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below. Rev 2 - April 2010 Page 39 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET FifoLevel 1 0 B B+1 # of bytes in FIFO Figure 23. FifoLevel IRQ Source Behavior 5.2.2.4. FIFO Clearing Table below summarizes the status of the FIFO when switching between different modes Table 16 Status of FIFO when Switching Between Different Modes of the Chip From Stdby Sleep Stdby/Sleep Rx To Sleep Stdby Rx Stdby/Sleep FIFO status Not cleared Not cleared Cleared Not cleared Comments To allow the user to read FIFO in Stdby/Sleep mode after Rx 5.2.3. Sync Word Recognition 5.2.3.1. Overview Sync word recognition (also called Pattern recognition) is activated by setting SyncOn in RegSyncConfig. The bit synchronizer must also be activated in continuous mode (automatically done in Packet mode) . The block behaves like a shift register; it continuously compares the incoming data with its internally programmed Sync word and sets SyncAddressMatch when a match is detected. This is illustrated in Figure 24 below. Rev 2 - April 2010 Page 40 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET Rx DATA Bit N-x = (NRZ) Sync_value[x] Bit N-1 = Bit N = Sync_value[1] Sync_value[0] DCLK SyncAddressMatch Figure 24. Sync Word Recognition During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync word. When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be processed accordingly. SyncAddressMatch is cleared when leaving Rx or FIFO is emptied. 5.2.3.2. Configuration Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via SyncSize in RegSyncConfig. Error tolerance: The number of errors tolerated in the Sync word recognition can be set from 0 to 7 bits to via SyncTol. Value: The Sync word value is configured in SyncValue(63:0). Note SyncValue choices containing 0x00 bytes are not allowed 5.2.4. Packet Handler The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5. 5.2.5. Control The control block configures and controls the full chip's behavior according to the settings programmed in the configuration registers. Rev 2 - April 2010 Page 41 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 5.3. Digital IO Pins Mapping Six general purpose IO pins are available on the SX1239, and their configuration in Continuous or Packet mode is controlled through RegDioMapping1 and RegDioMapping2. DATASHEET 5.3.1. DIO Pins Mapping in Continuous Mode Table 17 DIO Mapping, Continuous Mode Mode Sleep Diox Mapping 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 DIO5 LowBat ModeReady ClkOut LowBat ModeReady ClkOut LowBat ModeReady ClkOut Rssi LowBat ModeReady DIO4 LowBat LowBat LowBat PllLock Timeout RxReady SyncAddress PllLock DIO3 AutoMode AutoMode AutoMode Rssi RxReady AutoMode Timeout DIO2 Data Data Data Data DIO1 LowBat LowBat LowBat PllLock Dclk RxReady LowBat SyncAddress DIO0 LowBat ModeReady LowBat ModeReady PllLock LowBat ModeReady SyncAddress Timeout Rssi ModeReady Stdby FS Rx 5.3.2. DIO Pins Mapping in Packet Mode Table 18 DIO Mapping, Packet Mode Mode Sleep Diox Mapping 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 DIO5 LowBat ModeReady ClkOut LowBat ModeReady ClkOut LowBat ModeReady ClkOut Data LowBat ModeReady DIO4 LowBat LowBat LowBat PllLock Timeout Rssi RxReady PllLock DIO3 FifoFull LowBat FifoFull LowBat FifoFull LowBat PllLock FifoFull Rssi SyncAddress PllLock DIO2 FifoNotEmpty LowBat AutoMode FifoNotEmpty LowBat AutoMode FifoNotEmpty LowBat AutoMode FifoNotEmpty Data LowBat AutoMode DIO1 FifoLevel FifoFull FifoNotEmpty FifoLevel FifoFull FifoNotEmpty FifoLevel FifoFull FifoNotEmpty PllLock FifoLevel FifoFull FifoNotEmpty Timeout DIO0 LowBat LowBat LowBat PllLock CrcOk PayloadReady SyncAddress Rssi Stdby FS Rx Note Received Data is only shown on the Data signal between RxReady and PayloadReady's rising edges Rev 2 - April 2010 Page 42 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 5.4. Continuous Mode 5.4.1. General Description As illustrated in Figure 25, in Continuous mode the NRZ data from the demodulator is directly accessed by the uC on the DIO2/DATA pin. The FIFO and packet handler are thus inactive. DATASHEET Rx CONTROL DIO0 DIO1/DCLK DIO2/DATA DIO3 DIO4 DIO5 Data Rx SYNC RECOG. SPI NSS SCK MOSI MISO Figure 25. Continuous Mode Conceptual View 5.4.2. Rx Processing If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal is provided. Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on DIO2/DATA and DIO1/DCLK pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as illustrated below. DATA (NRZ) DCLK Figure 26. Rx Processing in Continuous Mode Note in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode). Rev 2 - April 2010 Page 43 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 5.5. Packet Mode 5.5.1. General Description In Packet mode the NRZ data from the demodulator is not directly accessed by the uC but stored in the FIFO and accessed via the SPI interface. In addition, the SX1239 packet handler performs several packet oriented tasks such as Preamble and Sync word check, CRC check, dewhitening of data, Manchester decoding, address filtering, AES decryption, etc. This simplifies software and reduces uC overhead by performing these repetitive tasks within the RF chip itself. Another important feature is ability to empty the FIFO in Sleep/Stdby mode, ensuring optimum power consumption and adding more flexibility for the software. DATASHEET CONTROL DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 Data Rx SYNC RECOG. PACKET HANDLER FIFO (+SR) SPI NSS SCK MOSI MISO Figure 27. Packet Mode Conceptual View Note The Bit Synchronizer is automatically enabled in Packet mode. 5.5.2. Packet Format 5.5.2.1. Fixed Length Packet Format Fixed length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to any value greater than 0. In applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize RF overhead (no length byte field is required). All nodes should be programmed with the same packet length value. Rev 2 - April 2010 Page 44 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET The length of the payload is limited to 255 bytes if AES is not enabled else the message is limited to 64 bytes (i.e. max 65 bytes payload if Address byte is enabled). The length programmed in PayloadLength relates only to the payload which includes the message and the optional address byte. In this mode, the payload must contain at least one byte, i.e. address or message byte. An illustration of a fixed length packet is shown below. It contains the following fields: Preamble (1010...) Sync word (Network ID) Optional Address byte (Node ID) Message data Optional 2-bytes CRC checksum DC free Data decoding CRC checksum calculation AES Decryption Preamble 0 to 65535 bytes Sync Word 0 to 8 bytes Address byte Message Up to 255 bytes Payload (min 1 Byte) CRC 2-bytes Fields processed and removed in Rx Optional User provided fields which are part of the payload Message part of the payload Figure 28. Fixed Length Packet Format 5.5.2.2. Variable Length Packet Format Variable length packet format is selected when bit PacketFormat is set to 1. This mode is useful in applications where the length of the packet is not known in advance and can vary over time. It is then necessary for the transmitter to send the length information together with each packet in order for the receiver to operate properly. In this mode the length of the payload, indicated by the length byte, is given by the first byte of the FIFO and is limited to 255 bytes if AES is not enabled else the message is limited to 64 bytes (i.e. max 66 bytes payload if Address byte is enabled). Note that the length byte itself is not included in its calculation. In this mode, the payload must contain at least 2 bytes, i.e. length + address or message byte. An illustration of a variable length packet is shown below. It contains the following fields: Preamble (1010...) Sync word (Network ID) Length byte Rev 2 - April 2010 Page 45 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING Optional Address byte (Node ID) Message data Optional 2-bytes CRC checksum DC free Data decoding CRC checksum calculation AES Decryption Preamble 0 to 65535 bytes Sync Word 0 to 8 bytes Length byte Address byte Message Up to 255 bytes CRC 2-bytes DATASHEET Payload (min 2 bytes) Fields processed and removed in Rx Optional User provided fields which are part of the payload Message part of the payload Figure 29. Variable Length Packet Format 5.5.2.3. Unlimited Length Packet Format Unlimited length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to 0. The user can then receive packets of arbitrary length and PayloadLength register is not used in Rx modes for counting the length of the bytes received. This mode is a replacement for the legacy buffered mode in SX1211/SX1212 transceivers. The data processing features like Address filtering, Manchester decoding and data dewhitening are not available if the sync pattern length is set to zero (SyncOn = 0). The CRC detection is also not supported in this mode of the packet handler. The interrupts like CrcOk & PayloadReady are not available either. An unlimited length packet shown in is made up of the following fields: Preamble (1010...). Sync word (Network ID). Optional Address byte (Node ID). Message data DC free Data decoding Preamble 0 to 65535 bytes Sync Word 0 to 8 bytes Address byte Message unlimited length Payload Fields processed and removed in Rx Message part of the payload Optional User provided fields which are part of the payload Figure 30. Unlimited Length Packet Format Rev 2 - April 2010 Page 46 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 5.5.3. Processing (without AES) In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations: Receiving the preamble and stripping it off Detecting the Sync word and stripping it off Optional DC-free decoding of data Optionally checking the address byte Optionally checking CRC and reflecting the result on CrcOk. Only the payload (including optional address and length fields) is made available in the FIFO. When the Rx mode is enabled the demodulator receives the preamble followed by the detection of sync word. If fixed length packet format is enabled then the number of bytes received as the payload is given by the PayloadLength parameter. In variable length mode the first byte received after the sync word is interpreted as the length of the received packet. The internal length counter is initialized to this received length. The PayloadLength register is set to a value which is greater than the maximum expected length of the received packet. If the received length is greater than the maximum length stored in PayloadLength register the packet is discarded otherwise the complete packet is received. If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed length is the address byte. If the address matches to the one in the NodeAddress field, reception of the data continues otherwise it's stopped. The CRC check is performed if CrcOn = 1 and the result is available in CrcOk indicating that the CRC was successful. An interrupt (PayloadReady) is also generated on DIO0 as soon as the payload is available in the FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode. If the CRC fails the PayloadReady interrupt is not generated and the FIFO is cleared. This function can be overridden by setting CrcAutoClearOff = 1, forcing the availability of PayloadReady interrupt and the payload in the FIFO even if the CRC fails. DATASHEET 5.5.4. AES AES is the symmetric-key block cipher that provides the cryptographic capabilities to the receiver. The system proposed can work with 128-bit long fixed keys. The fixed key is stored in a 16-byte write only user configuration register, which retains its value in Sleep mode. As shown in Figure 28 and Figure 29 above the message part of the Packet can be decrypted with the cipher 128- cipher key stored in the configuration registers. 5.5.4.1. Processing 1. The data received is stored in the FIFO, The address, CRC interrupts are generated as usual because these parameters were not encrypted. 2. Once the complete packet has been received. The data is read from the FIFO, decrypted and written back to FIFO. The PayloadReady interrupt is issued once the decrypted data is ready in the FIFO for reading via the SPI interface. The AES decryption cannot be used on the fly i.e. while receiving data. Thus when AES decryption is enabled, the FIFO acts as a simple buffer. The decryption is initiated only once the complete packet has been received in the buffer. The decryption process takes approximately 7.0 us per 16-byte block. Thus for a maximum of 4 blocks (i.e. 64 bytes) it can take up to 28 us for completing the cryptographic operations. Rev 2 - April 2010 Page 47 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET The receiver sees the AES decryption time as a sequential delay before the PayloadReady interrupt is available. In Fixed length mode the Message part of the payload that can be decrypted can be 64 bytes long. If the address filtering is enabled, the length of the payload should be at max 65 bytes in this case. In Variable length mode the Max message size that can be decrypted is also 64 bytes whether address comparison is enabled or not. Thus, including length byte, the length of the payload is either 65 or 66 bytes (the latter when address comparison is enabled) at max. Crc check being performed on encrypted data, CrcOk interrupt will occur "decryption time" before PayloadReady interrupt. 5.5.5. Handling Large Packets When Payload length exceeds FIFO size (66 bytes) whether in fixed, variable or unlimited length packet format, in addition to PayloadReady or CrcOk in Rx, the FIFO interrupts/flags can be used as described below: FIFO must be unfilled "on-the-fly" during Rx to prevent FIFO overrun. 1) Start reading bytes from the FIFO when FifoNotEmpty or FifoThreshold becomes set. 2) Suspend reading from the FIFO if FifoNotEmpty clears before all bytes of the message have been read 3) Continue to step 1 until PayloadReady or CrcOk fires 4) Read all remaining bytes from the FIFO either in Rx or Sleep/Standby mode Note AES decryption is not feasible on large packets, since all Payload bytes need to be in the FIFO at the same time to perform decryption 5.5.6. Packet Filtering SX1239's packet handler offers several mechanisms for packet filtering, ensuring that only useful packets are made available to the uC, reducing significantly system power consumption and software complexity. 5.5.6.1. Sync Word Based Sync word filtering/recognition is used for identifying the start of the payload and also for network identification. As previously described, the Sync word recognition block is configured (size, error tolerance, value) in RegSyncValue registers. This information is used to filter packets in Rx. Every received packet which does not start with this locally configured Sync word is automatically discarded and no interrupt is generated. When the Sync word is detected, payload reception automatically starts and SyncAddressMatch is asserted. Note Sync Word values containing 0x00 byte(s) are forbidden Rev 2 - April 2010 Page 48 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 5.5.6.2. Address Based Address filtering can be enabled via the AddressFiltering bits. It adds another level of filtering, above Sync word (i.e. Sync must match first), typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word) and each node has its own ID (address). Two address based filtering options are available: AddressFiltering = 01: Received address field is compared with internal register NodeAddress. If they match then the packet is accepted and processed, otherwise it is discarded. AddressFiltering = 10: Received address field is compared with internal registers NodeAddress and BroadcastAddress. If either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional check with a constant is useful for implementing broadcast in a multi-node networks As address filtering requires a Sync Word match, both features share the same interrupt flag SyncAddressMatch. Please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. DATASHEET 5.5.6.3. Length Based In variable length Packet mode, PayloadLength must be programmed with the maximum payload length permitted. If received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded. Please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. To disable this function the user should set the value of the PayloadLength to 255. 5.5.6.4. CRC Based The CRC check is enabled by setting bit CrcOn in RegPacketConfig1. It is used for checking the integrity of the message. The checksum is calculated on the received payload and compared with the two checksum bytes received. The result of the comparison is stored in bit CrcOk. By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function can be disabled via CrcAutoClearOff bit and in this case, even if CRC fails, the FIFO is not cleared and only PayloadReady interrupt goes high. Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler and only the payload is made available in the FIFO. The CRC is based on the CCITT polynomial as shown below. This implementation also detects errors due to leading and trailing zeros. Rev 2 - April 2010 Page 49 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET data input CRC Polynomial =X16 + X12 + X5 + 1 X15 X14 X13 X12 X11 *** X5 X4 *** X0 Figure 31. CRC Implementation 5.5.7. DC-Free Data Mechanisms The received payload can be de-whitened or Manchester decoded automatically in the SX1239 Packet Handler. Note Only one of the two methods should be enabled at a time. 5.5.7.1. Manchester Decoding Manchester decoding is enabled if DcFree = 01 and can only be used in Packet mode. The Manchester data is decoded to NRZ code by decoding "10" as '1' and "01" as '0'. In this case, the maximum chip rate is the maximum bit rate given in the specifications section and the actual bit rate is half the chip rate. Manchester decoding is only applied to the payload and CRC checksum while preamble and Sync word are kept NRZ. However, the chip rate from preamble to CRC is the same and defined by BitRate in RegBitRate (Chip Rate = Bit Rate NRZ = 2 x Bit Rate Manchester). Manchester decoding is thus made transparent for the user, who still retrieves NRZ data from the FIFO. 1/BR ...Sync 1/BR RF chips @ BR User/NRZ bits Manchester OFF User/NRZ bits Manchester ON ... ... ... 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 Payload... 0 1 1 0 0 1 1 1 0 0 1 1 1 0 0 ... ... ... t Figure 32. Manchester Decoding 5.5.7.2. Data De-Whitening Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission. The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence. Comparing to Manchester technique it has the advantage of keeping NRZ data rate i.e. actual bit rate is not halved. Rev 2 - April 2010 Page 50 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET The de-whitening process is enabled if DcFree = 10. The data, including payload and 2-byte CRC checksum, is dewhitened by XORing it with a random sequence generated in a 9-bit LFSR, shown in Figure 33. Payload de-whitening is thus made transparent for the user, who still retrieves NRZ data from the FIFO. Received Data De-whitened Data Figure 33. Data De-Whitening Rev 2 - April 2010 Page 51 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET 6. Configuration and Status Registers 6.1. General Description Table 19 Registers Summary Reset (built-in) Default (recom mended) FIFO read/write access Operating modes of the receiver Data operation mode and Modulation settings Bit Rate setting, Most Significant Bits Bit Rate setting, Least Significant Bits RF Carrier Frequency, Most Significant Bits RF Carrier Frequency, Intermediate Bits RF Carrier Frequency, Least Significant Bits RC Oscillators Settings AFC control in low modulation index situations Low Battery Indicator Settings Listen Mode settings Listen Mode Idle duration Listen Mode Rx duration Semtech ID relating the silicon revision 0x88 0x55 LNA settings Channel Filter BW Control Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 Register Name RegFifo RegOpMode RegDataModul RegBitrateMsb RegBitrateLsb Reserved05 Reserved06 RegFrfMsb RegFrfMid RegFrfLsb RegOsc1 RegAfcCtrl RegLowBat RegListen1 RegListen2 RegListen3 RegVersion Reserved11 Reserved12 Reserved13 Reserved14 Reserved15 Reserved16 Reserved17 RegLna RegRxBw Description 0x00 0x04 0x00 0x1A 0x0B 0x00 0x52 0xE4 0xC0 0x00 0x41 0x00 0x02 0x92 0xF5 0x20 0x22 0x9F 0x09 0x1A 0x40 0xB0 0x7B 0x9B 0x08 0x86 Rev 2 - April 2010 Page 52 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET Address 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F-0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D Register Name RegAfcBw RegOokPeak RegOokAvg RegOokFix RegAfcFei RegAfcMsb RegAfcLsb RegFeiMsb RegFeiLsb RegRssiConfig RegRssiValue RegDioMapping1 RegDioMapping2 RegIrqFlags1 RegIrqFlags2 RegRssiThresh RegRxTimeout1 RegRxTimeout2 Reserved2C Reserved2D RegSyncConfig RegSyncValue1-8 RegPacketConfig1 RegPayloadLength RegNodeAdrs RegBroadcastAdrs RegAutoModes RegFifoThresh RegPacketConfig2 Reset (built-in) 0x8A Default (recom mended) 0x8B Description Channel Filter BW control during the AFC routine OOK demodulator selection and control in peak mode Average threshold control of the OOK demodulator Fixed threshold control of the OOK demodulator AFC and FEI control and status MSB of the frequency correction of the AFC LSB of the frequency correction of the AFC MSB of the calculated frequency error LSB of the calculated frequency error RSSI-related settings RSSI value in dBm Mapping of pins DIO0 to DIO3 0x40 0x80 0x06 0x10 0x00 0x00 0x00 0x00 0x02 0xFF 0x00 0x05 0x80 0x00 0xFF 0x00 0x00 0x00 0x03 0x98 0x00 0x10 0x40 0x00 0x00 0x00 0x0F 0x02 0x8F 0x01 0xE4 0x07 Mapping of pins DIO4 and DIO5, ClkOut frequency Status register: PLL Lock state, Timeout, RSSI > Threshold... Status register: FIFO handling flags, Low Battery detection... RSSI Threshold control Timeout duration between Rx request and RSSI detection Timeout duration between RSSI detection and PayloadReady Sync Word Recognition control Sync Word bytes, 1 through 8 Packet mode settings Payload length setting Node address Broadcast address Auto modes settings Fifo threshold Packet mode settings Rev 2 - April 2010 Page 53 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET Address 0x3E-0x4D 0x4E 0x4F 0x58 0x71 0x50 + Register Name RegAesKey1-16 RegTemp1 RegTemp2 RegTestLna RegTestAfc RegTest Reset (built-in) Default (recom mended) Description 16 bytes of the cypher key Temperature Sensor control Temperature readout Sensitivity boost AFC offset for low modulation index AFC Internal test registers 0x00 0x01 0x00 0x1B 0x00 - Note - Reset values are automatically refreshed in the chip at Power On Reset - Default values are the Semtech recommended register values, optimizing the device operation - Registers for which the Default value differs from the Reset value are denoted by a * in the tables of section 6 Rev 2 - April 2010 Page 54 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 6.2. Common Configuration Registers Table 20 Common Configuration Registers Name (Address) RegFifo (0x00) RegOpMode (0x01) Bits Variable Name 7-0 7 Fifo SequencerOff Mode rw rw Default Description Value 0x00 FIFO data output 0 Controls the automatic Sequencer (see section 4.2 ): 0 Operating mode as selected with Mode bits in RegOpMode is automatically reached with the Sequencer Mode is forced by the user 1 Enables Listen mode: 0 Off (see section 4.3) 1 On Aborts Listen mode when set together with ListenOn=0 and new Mode selection in 1 SPI access (see section 4.3) Always reads 0. Receiver's operating modes: 000 sleep mode (SLEEP) 001 standby mode (STDBY) frequency synthesizer mode (FS) 010 100 receiver mode (RX) others reserved Reads the value corresponding to the current chip mode unused unused Data processing mode: 00 Packet mode 01 reserved Continuous mode with bit synchronizer 10 11 Continuous mode without bit synchronizer Modulation scheme: 00 FSK 01 OOK reserved 10 - 11 unused MSB of Bit Rate (Chip Rate when Manchester encoding is enabled) LSB of Bit Rate (Chip Rate if Manchester encoding is enabled) FXOSC BitRate = ---------------------------------BitRate (15,0) Default value: 4.8 kb/s unused unused MSB of the RF Local Oscillator Middle byte of the RF Local Oscillator DATASHEET 6 ListenOn rw 0 5 ListenAbort w 0 4-2 Mode rw 001 RegDataModul (0x02) 1-0 7 6-5 DataMode r r rw 00 0 00 4-3 ModulationType rw 00 RegBitrateMsb (0x03) RegBitrateLsb (0x04) 2-0 7-0 7-0 BitRate(15:8) BitRate(7:0) r rw rw 000 0x1a 0x0b Reserved05 (0x05) Reserved06 (0x06) RegFrfMsb (0x07) RegFrfMid (0x08) 7-0 7-0 7-0 7-0 Frf(23:16) Frf(15:8) r r rw rw 0x00 0x52 0xe4 0xc0 Rev 2 - April 2010 Page 55 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 7-0 Frf(7:0) rw 0x00 LSB of the RF Local Oscillator DATASHEET RegFrfLsb (0x09) Frf = Fstep x Frf ( 23 ;0 ) 7 RcCalStart w Default value: Frf = 915 MHz (32 MHz XO) 0 Triggers the calibration of the RC oscillator when set. Always reads 0. RC calibration must be triggered in Standby mode. 1 0 RC calibration in progress 1 RC calibration is over 000001 unused 00 unused 0 Improved AFC routine for signals with modulation index lower than 2. Refer to section 3.4.16 for details Standard AFC routine 0 1 Improved AFC routine 00000 unused 000 unused Real-time (not latched) output of the Low Battery detector, when enabled. 0 Low Battery detector enable signal LowBat off 0 1 LowBat on 010 Trimming of the LowBat threshold: 000 1.695 V 001 1.764 V 1.835 V 011 1.905 V 010 100 1.976 V 101 2.045 V 110 2.116 V 111 2.185 V 10 Resolution of Listen modes timings (calibrated RC osc): 0101 64 us 4.1 ms 1010 1111 262 ms Others reserved 01 Resolution of Listen mode Rx time (calibrated RC osc): 00 reserved 64 us 01 10 4.1 ms 11 262 ms 0 Criteria for packet acceptance in Listen mode: 0 signal strength is above RssiThreshold 1 signal strength is above RssiThreshold and SyncAddress matched 01 Action taken after acceptance of a packet in Listen mode: 00 chip stays in Rx mode. Listen mode stops and must be disabled (see section 4.3). chip stays in Rx mode until PayloadReady or 01 Timeout interrupt occurs. It then goes to the mode defined by Mode. Listen mode stops and must be disabled (see section 4.3). chip stays in Rx mode until PayloadReady or 10 Timeout interrupt occurs. Listen mode then resumes in Idle state. FIFO content is lost at next Rx wakeup. Reserved 11 0 unused RegOsc1 (0x0A) 6 5-0 7-6 5 RcCalDone AfcLowBetaOn r r r rw RegAfcCtrl (0x0B) RegLowBat (0x0C) 4-0 7-5 4 3 LowBatMonitor LowBatOn r r rw rw 2-0 LowBatTrim rw RegListen1 (0x0D) 7-6 ListenResolIdle rw 5-4 ListenResolRx rw 3 ListenCriteria rw 2-1 ListenEnd rw 0 - r Rev 2 - April 2010 Page 56 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 7-0 ListenCoefIdle rw 0xf5 DATASHEET Duration of the Idle phase in Listen mode. RegListen2 (0x0E) RegListen3 (0x0F) t ListenIdle = ListenCoefIdle ListenResolIdle 7-0 ListenCoefRx rw 0x20 Duration of the Rx phase in Listen mode (startup time included, see section 4.2.1) t ListenRx = ListenCoefRx ListenResolRx RegVersion (0x10) 7-0 Version r 0x22 Version code of the chip. Bits 7-4 give the full revision number; bits 3-0 give the metal mask revision number. Rev 2 - April 2010 Page 57 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 6.3. Receiver Registers Table 21 Receiver Registers Name (Address) Reserved14 (0x14) Reserved15 (0x15) Reserved16 (0x16) Reserved17 (0x17) RegLna (0x18) Bits Variable Name 7-0 7-0 7-0 7-0 7 LnaZin Mode r r r r rw Default Description Value 0x40 unused 0xB0 0x7B 0x9B 1 * 0 001 000 unused unused unused LNA's input impedance 0 50 ohms 200 ohms 1 unused Current LNA gain, set either manually, or by the AGC LNA gain setting: 000 gain set by the internal AGC loop G1 = highest gain 001 010 G2 = highest gain - 6 dB 011 G3 = highest gain - 12 dB G4 = highest gain - 24 dB 100 101 G5 = highest gain - 36 dB 110 G6 = highest gain - 48 dB reserved 111 Cut-off frequency of the DC offset canceller (DCC): 4 x RxBw fc = ----------------------------------------DccFreq + 2 2 x 2 ~4% of the RxBw by default Channel filter bandwidth control: RxBwMant = 16 10 RxBwMant = 24 00 01 RxBwMant = 20 11 reserved Channel filter bandwidth control: FSK Mode: FXOSC RxBw = ----------------------------------------------------------------RxBwExp + 2 RxBwMant x 2 OOK Mode: DATASHEET 6 5-3 2-0 LnaCurrentGain LnaGainSelect r r rw RegRxBw (0x19) 7-5 DccFreq rw 010 * 4-3 RxBwMant rw 10 * 101 * 2-0 RxBwExp rw FXOSC RxBw = ----------------------------------------------------------------RxBwExp + 3 RxBwMant x 2 RegAfcBw (0x1A) 7-5 4-3 2-0 DccFreqAfc RxBwMantAfc RxBwExpAfc rw rw rw 100 01 011 * See Table 10 for tabulated values DccFreq parameter used during the AFC RxBwMant parameter used during the AFC RxBwExp parameter used during the AFC Rev 2 - April 2010 Page 58 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 7-6 OokThreshType rw 01 DATASHEET Selects type of threshold in the OOK data slicer: 00 fixed 10 average peak 11 reserved 01 Size of each decrement of the RSSI threshold in the OOK demodulator: 0.5 dB 001 1.0 dB 000 010 1.5 dB 011 2.0 dB 3.0 dB 101 4.0 dB 100 110 5.0 dB 111 6.0 dB Period of decrement of the RSSI threshold in the OOK demodulator: 000 once per chip 001 once every 2 chips once every 4 chips 011 once every 8 chips 010 100 twice in each chip 101 4 times in each chip 110 8 times in each chip 111 16 times in each chip Filter coefficients in average mode of the OOK demodulator: fC chip rate / 32. 00 01 10 11 fC chip rate / 8. fC chip rate / 4. fC chip rate / 2. RegOokPeak (0x1B) 5-3 OokPeakTheshStep rw 000 2-0 OokPeakThreshDec rw 000 RegOokAvg (0x1C) 7-6 OokAverageThreshFilt rw 10 RegOokFix (0x1D) RegAfcFei (0x1E) 5-0 7-0 7 6 5 4 3 OokFixedThresh FeiDone FeiStart AfcDone AfcAutoclearOn r rw r r w r rw 000000 unused 0110 Fixed threshold value (in dB) in the OOK demodulator. (6dB) Used when OokThresType = 00 0 0 0 1 0 unused 0 FEI is on-going 1 FEI finished Triggers a FEI measurement when set. Always reads 0. 0 AFC is on-going AFC has finished 1 Only valid if AfcAutoOn is set 0 AFC register is not cleared before a new AFC phase 1 AFC register is cleared before a new AFC phase 0 AFC is performed each time AfcStart is set 1 AFC is performed each time Rx mode is entered Clears the AfcValue if set in Rx mode. Always reads 0 Triggers an AFC when set. Always reads 0. MSB of the AfcValue, 2's complement format LSB of the AfcValue, 2's complement format Frequency correction = AfcValue x Fstep MSB of the measured frequency offset, 2's complement LSB of the measured frequency offset, 2's complement Frequency error = FeiValue x Fstep 2 1 0 7-0 7-0 7-0 7-0 7-2 1 0 7-0 AfcAutoOn AfcClear AfcStart AfcValue(15:8) AfcValue(7:0) FeiValue(15:8) FeiValue(7:0) RssiDone RssiStart RssiValue rw w w r r r r r r w r 0 0 0 0x00 0x00 - RegAfcMsb (0x1F) RegAfcLsb (0x20) RegFeiMsb (0x21) RegFeiLsb (0x22) RegRssiConfig (0x23) RegRssiValue (0x24) Rev 2 - April 2010 000000 unused 1 0 RSSI is on-going RSSI sampling is finished, result available 1 0 Trigger a RSSI measurement when set. Always reads 0. 0xFF Absolute value of the RSSI in dBm, 0.5dB steps. RSSI = -RssiValue/2 [dBm] Page 59 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 6.4. IRQ and Pin Mapping Registers Table 22 IRQ and Pin Mapping Registers Name (Address) RegDioMapping1 (0x25) Bits Variable Name 7-6 5-4 3-2 1-0 7-6 5-4 3 2-0 Dio0Mapping Dio1Mapping Dio2Mapping Dio3Mapping Dio4Mapping Dio5Mapping ClkOut Mode rw rw rw rw rw rw r rw Default Value 00 00 00 00 00 00 0 111 * Description Mapping of pins DIO0 to DIO5 See Table 17 for mapping in Continuous mode See Table 18 for mapping in Packet mode DATASHEET RegDioMapping2 (0x26) RegIrqFlags1 (0x27) 7 ModeReady r 1 6 5 4 3 2 RxReady PllLock Rssi Timeout r r r rwc r 0 0 0 0 0 1 AutoMode r 0 0 SyncAddressMatch r/rwc 0 unused Selects CLKOUT frequency: 000 FXOSC FXOSC / 2 001 010 FXOSC / 4 FXOSC / 8 011 100 FXOSC / 16 101 FXOSC / 32 RC (automatically enabled) 110 111 OFF Set when the operation mode requested in Mode, is ready - Sleep: Entering Sleep mode - Standby: XO is running - FS: PLL is locked - Rx: RSSI sampling starts Cleared when changing operating mode. Set in Rx mode, after RSSI, AGC and AFC. Cleared when leaving Rx. unused Set (in FS and Rx) when the PLL is locked. Cleared when it is not. Set in Rx when the RssiValue exceeds RssiThreshold. Cleared when leaving Rx. Set when a timeout occurs (see TimeoutRxStart and TimeoutRssiThresh) Cleared when leaving Rx or FIFO is emptied. Set when entering Intermediate mode. Cleared when exiting Intermediate mode. Please note that in Sleep mode a small delay can be observed between AutoMode interrupt and the corresponding enter/exit condition. Set when Sync and Address (if enabled) are detected. Cleared when leaving Rx or FIFO is emptied. This bit is read only in Packet mode, rwc in Continuous mode Rev 2 - April 2010 Page 60 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 7 6 5 4 FifoFull FifoNotEmpty FifoLevel FifoOverrun r r r rwc 0 0 0 0 DATASHEET Set when FIFO is full (i.e. contains 66 bytes), else cleared. Set when FIFO contains at least one byte, else cleared Set when the number of bytes in the FIFO strictly exceeds FifoThreshold, else cleared. Set when FIFO overrun occurs. (except in Sleep mode) Flag(s) and FIFO are cleared when this bit is set. The FIFO then becomes immediately available for the next reception. unused Set in Rx when the payload is ready (i.e. last byte received and CRC, if enabled and CrcAutoClearOff is cleared, is Ok). Cleared when FIFO is empty. Set in Rx when the CRC of the payload is Ok. Cleared when FIFO is empty. Set when the battery voltage drops below the Low Battery threshold. Cleared only when set by the user. RSSI trigger level for Rssi interrupt : - RssiThreshold / 2 [dBm] RegIrqFlags2 (0x28) 3 2 PayloadReady r r 0 0 1 0 RegRssiThresh (0x29) RegRxTimeout1 (0x2A) 7-0 7-0 CrcOk LowBat RssiThreshold TimeoutRxStart r rwc rw rw 0 0xE4 * 0x00 RegRxTimeout2 (0x2B) 7-0 TimeoutRssiThresh rw 0x00 Timeout interrupt is generated TimeoutRxStart*16*Tbit after switching to Rx mode if Rssi interrupt doesn't occur (i.e. RssiValue > RssiThreshold) 0x00: TimeoutRxStart is disabled Timeout interrupt is generated TimeoutRssiThresh*16*Tbit after Rssi interrupt if PayloadReady interrupt doesn't occur. 0x00: TimeoutRssiThresh is disabled Rev 2 - April 2010 Page 61 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 6.5. Packet Engine Registers Table 23 Packet Engine Registers Name (Address) Reserved2C (0x2c) Reserved2D (0x2d) RegSyncConfig (0x2e) Bits Variable Name 7-0 7-0 7 SyncOn Mode rw rw rw Default Description Value 0x00 unused 0x03 1 unused Enables the Sync word detection: 0 Off On 1 FIFO filling condition: if SyncAddress interrupt occurs 0 1 as long as FifoFillCondition is set Size of the Sync word: (SyncSize + 1) bytes Number of tolerated bit errors in Sync word 1st byte of Sync word. (MSB byte) Used if SyncOn is set. 2nd byte of Sync word Used if SyncOn is set and (SyncSize +1) >= 2. 3rd byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 3. 4th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 4. 5th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 5. 6th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 6. 7th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 7. 8th byte of Sync word. Used if SyncOn is set and (SyncSize +1) = 8. DATASHEET 6 FifoFillCondition rw 0 5-3 2-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 SyncSize SyncTol SyncValue(63:56) SyncValue(55:48) SyncValue(47:40) SyncValue(39:32) SyncValue(31:24) SyncValue(23:16) SyncValue(15:8) SyncValue(7:0) rw rw rw rw rw rw rw rw rw rw 011 000 0x01 * 0x01 * 0x01 * 0x01 * 0x01 * 0x01 * 0x01 * 0x01 * RegSyncValue1 (0x2f) RegSyncValue2 (0x30) RegSyncValue3 (0x31) RegSyncValue4 (0x32) RegSyncValue5 (0x33) RegSyncValue6 (0x34) RegSyncValue7 (0x35) RegSyncValue8 (0x36) Rev 2 - April 2010 Page 62 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 7 PacketFormat rw 0 DATASHEET Defines the packet format used: 0 Fixed length Variable length 1 Defines DC-free decoding performed: None (Off) 00 01 Manchester 10 Whitening reserved 11 Enables CRC check: Off 0 1 On Defines the behavior of the packet handler when CRC check fails: 0 Clear FIFO and restart new packet reception. No PayloadReady interrupt issued. 1 Do not clear FIFO. PayloadReady interrupt issued. Defines address based filtering in Rx: 00 None (Off) Address field must match NodeAddress 01 10 Must match NodeAddress or BroadcastAddress 11 reserved unused If PacketFormat = 0 (fixed), payload length. If PacketFormat = 1 (variable), max length in Rx Node address used in address filtering. Broadcast address used in address filtering. Interrupt condition for entering the intermediate mode: 000 None (AutoModes Off) 001 Rising edge of FifoNotEmpty 010 Rising edge of FifoLevel 011 Rising edge of CrcOk 100 Rising edge of PayloadReady 101 Rising edge of SyncAddress 110 Reserved 111 Falling edge of FifoNotEmpty (i.e. FIFO empty) Interrupt condition for exiting the intermediate mode: 000 None (AutoModes Off) Falling edge of FifoNotEmpty (i.e. FIFO empty) 001 010 Rising edge of FifoLevel or Timeout 011 Rising edge of CrcOk or Timeout 100 Rising edge of PayloadReady or Timeout 101 Rising edge of SyncAddress or Timeout 110 Reserved Rising edge of Timeout 111 Intermediate mode: Sleep mode (SLEEP) 00 01 Standby mode (STDBY) 10 Receiver mode (RX) Reserved 11 unused RegPacketConfig1 (0x37) 6-5 DcFree rw 00 4 CrcOn rw 1 3 CrcAutoClearOff rw 0 2-1 AddressFiltering rw 00 RegPayloadLength (0x38) RegNodeAdrs (0x39) RegBroadcastAdrs (0x3A) RegAutoModes (0x3B) 0 7-0 7-0 7-0 7-5 PayloadLength NodeAddress BroadcastAddress EnterCondition rw rw rw rw rw 0 0x40 0x00 0x00 000 4-2 ExitCondition rw 000 1-0 IntermediateMode rw 00 RegFifoThresh (0x3C) 7 6-0 FifoThreshold rw rw 1 * 0001111 Used to trigger FifoLevel interrupt. Rev 2 - April 2010 Page 63 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 7-4 InterPacketRxDelay rw 0000 DATASHEET After PayloadReady occurred, defines the delay between FIFO empty and the start of a new RSSI phase for next packet. Must match the transmitter's PA ramp-down time. - Tdelay = 0 if InterpacketRxDelay >= 12 - Tdelay = (2InterpacketRxDelay) / BitRate otherwise unused Forces the Receiver in WAIT mode, in Continuous Rx mode. Always reads 0. Enables automatic Rx restart (RSSI phase) after PayloadReady occurred and packet has been completely read from FIFO: Off. RestartRx can be used. 0 1 On. Rx auto. restart after InterPacketRxDelay. Enable the AES decryption: 0 Off On (payload limited to 66 bytes maximum) 1 1st byte of cipher key (MSB byte) 2nd byte of cipher key 3rd byte of cipher key 4th byte of cipher key 5th byte of cipher key 6th byte of cipher key 7th byte of cipher key 8th byte of cipher key 9th byte of cipher key 10th byte of cipher key 11th byte of cipher key 12th byte of cipher key 13th byte of cipher key 14th byte of cipher key 15th byte of cipher key 16th byte of cipher key (LSB byte) RegPacketConfig2 (0x3D) 3 2 RestartRx rw w 0 0 1 AutoRxRestartOn rw 1 0 AesOn rw 0 RegAesKey1 (0x3E) RegAesKey2 (0x3F) RegAesKey3 (0x40) RegAesKey4 (0x41) RegAesKey5 (0x42) RegAesKey6 (0x43) RegAesKey7 (0x44) RegAesKey8 (0x45) RegAesKey9 (0x46) RegAesKey10 (0x47) RegAesKey11 (0x48) RegAesKey12 (0x49) RegAesKey13 (0x4A) RegAesKey14 (0x4B) RegAesKey15 (0x4C) RegAesKey16 (0x4D) 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 AesKey(127:120) AesKey(119:112) AesKey(111:104) AesKey(103:96) AesKey(95:88) AesKey(87:80) AesKey(79:72) AesKey(71:64) AesKey(63:56) AesKey(55:48) AesKey(47:40) AesKey(39:32) AesKey(31:24) AesKey(23:16) AesKey(15:8) AesKey(7:0) w w w w w w w w w w w w w w w w 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Rev 2 - April 2010 Page 64 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 6.6. Temperature Sensor Registers Table 24 Temperature Sensor Registers Name (Address) RegTemp1 (0x4E) Bits Variable Name 7-4 3 2 TempMeasStart TempMeasRunning Mode r w r Default Description Value 0000 unused 0 Triggers the temperature measurement when set. Always reads 0. 0 Set to 1 while the temperature measurement is running. Toggles back to 0 when the measurement has completed. The receiver can not be used while measuring temperature 01 unused Measured temperature -1C per Lsb Needs calibration for accuracy DATASHEET RegTemp2 (0x4F) 1-0 7-0 TempValue r r 6.7. Test Registers Table 25 Test Registers Name (Address) RegTestLna (0x58) RegTestAfc (0x71) Bits Variable Name 7-0 SensitivityBoost Mode rw Default Description Value 0x1B High sensitivity or normal sensitivity mode: Normal mode 0x1B 0x2D High sensitivity mode 0x00 AFC offset set for low modulation index systems, used if AfcLowBetaOn=1. Offset = LowBetaAfcOffset x 488 Hz 7-0 LowBetaAfcOffset rw Rev 2 - April 2010 Page 65 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET 7. Application Information 7.1. Crystal Resonator Specification Table 26 shows the crystal resonator specification for the crystal reference oscillator circuit of the SX1239. This specification covers the full range of operation of the SX1239 and is employed in the reference design. Table 26 Crystal Specification Symbol FXOSC RS C0 CLOAD Description XTAL Frequency XTAL Serial Resistance XTAL Shunt Capacitance External Foot Capacitance On each pin XTA and XTB Conditions Min 26 8 Typ 30 2.8 16 Max 32 140 7 22 Unit MHz ohms pF pF Notes - the initial frequency tolerance, temperature stability and ageing performance should be chosen in accordance with the target operating temperature range and the receiver bandwidth selected. - the loading capacitance should be applied externally, and adapted to the actual Cload specification of the XTAL. - A minimum XTAL frequency of 28 MHz is required to cover the 863-870 MHz band, 29 MHz for the 902-928 MHz band 7.2. Reset of the Chip A power-on reset of the SX1239 is triggered at power up. Additionally, a manual reset can be issued by controlling pin 6. 7.2.1. POR If the application requires the disconnection of VDD from the SX1239, despite of the extremely low Sleep Mode current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus. Pin 6 (Reset) should be left floating during the POR sequence. VDD Pin 6 (output) Undefined Wait for 10 ms Chip is ready from this point on Figure 34. POR Timing Diagram Please note that any CLKOUT activity can also be used to detect that the chip is ready. Rev 2 - April 2010 Page 66 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 7.2.2. Manual Reset A manual reset of the SX1239 is possible even for applications in which VDD cannot be physically disconnected. Pin 6 should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms before using the chip. DATASHEET VDD > 100 us Wait for 5 ms Chip is ready from this point on Pin 6 (input) High-Z ''1'' High-Z Figure 35. Manual Reset Timing Diagram Note whilst pin 6 is driven high, an over current consumption of up to ten milliamps can be seen on VDD. 7.3. Reference Design Please contact your Semtech representative for evaluation tools, reference designs and design assistance. Note that all schematics shown in this section are full schematics, listing ALL required components, including decoupling capacitors. Figure 36. Application Schematic Note In very cost-sensitive and/or size-constrained applications where it is acceptable to degrade the receiver sensitivity by approximately 2 dB, L1 and C1 can be omitted. Rev 2 - April 2010 Page 67 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET 8. Packaging Information 8.1. Package Outline Drawing The SX1239 is available in a 24-lead QFN package as show in Figure 37. A D B DIM A A1 A2 b D D1 E E1 e L N aaa bbb DIMENSIONS MILLIMETERS MIN NOM MAX 0.80 1.00 0.00 0.05 - (0.20) 0.25 0.30 0.35 4.90 5.00 5.10 3.20 3.25 3.30 4.90 5.00 5.10 3.20 3.25 3.30 0.65 BSC 0.35 0.40 0.45 24 0.08 0.10 PIN 1 INDICATOR (LASER MARK) E A1 A aaa C A2 SEATING PLANE C D1 LxN E/2 E1 2 1 N bxN bbb e CAB e/2 D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. Figure 37. Package Outline Drawing 8.2. Recommended Land Pattern K DIM C G H K P X Y Z DIMENSIONS MILLIMETERS (4.90) 4.10 3.30 3.30 0.65 0.35 0.80 5.70 (C) H G Z Y X P NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. Figure 38. Recommended Land Pattern Rev 2 - April 2010 Page 68 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 8.3. Thermal Impedance The thermal impedance of this package is: Theta ja = 29 C/W typ., calculated from a package in still air, on a 4-layer FR4 PCB, as per the Jedec standard. DATASHEET 8.4. Tape & Reel Specification Figure 39. Tape & Reel Specification Note Single Sprocket holes Rev 2 - April 2010 Page 69 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET 9. Chip Revisions Two distinct chip populations exist and can be identified as follows: Table 27 Chip Identification Chip Version V2a V2b Register Value @ address 0x10 0x21 0x22 Date Codes yyww (see Figure 3) 1008 1006, 1009 and beyond Comment Limited supply Running production This document describes the behavior and characteristics of the SX1239 V2b. Minor differences can be observed between the two versions, and they are listed in the following sub sections. 9.1. RC Oscillator Calibration On the SX1239 V2a, RC calibration at power-up needs to be performed according to the following routine: /////// RC CALIBRATION (Once at POR) /////// SetRFMode(RF_STANDBY); WriteRegister(0x57, 0x80); WriteRegister(REG_OSC1, ReadRegister(REG_OSC1) | 0x80); while (ReadRegister(REG_OSC1) & 0x40 == 0x00); WriteRegister(REG_OSC1, ReadRegister(REG_OSC1) | 0x80); while (ReadRegister(REG_OSC1) & 0x40 == 0x00); WriteRegister(0x57, 0x00); //////////////////////////////////////////// This is not required in the version V2b any more, where the calibration is fully automatic. 9.2. Listen Mode 9.2.1. Resolutions On the SX1239 V2a, the Listen mode resolutions were identical for the Idle phase and the Rx phase. They are now independently configurable, adding flexibility in the setup of the Listen mode. Figure 40. Listen Mode Resolutions, V2a Figure 41. Listen Mode Resolution, V2b Rev 2 - April 2010 Page 70 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING 9.2.2. Exiting Listen Mode In the SX1239 V2a, the following procedure was requested to exit Listen mode: For all three ListenEnd settings (i.e. even for 00 and 01) disabling Listen mode can be done anytime by writing all together in a single SPI write command (same register) : ListenOn to 0 ListenAbort to 1 Mode to the wanted operation mode DATASHEET Figure 42. Exiting Listen Mode in SX1239 V2a Listen mode can simply be exited on the SX1239 V2b by resetting bit ListenOn to 0 in RegListen. 9.3. OOK Floor Threshold Default Setting The following default value modification was required on the V2a silicon: Figure 43. RegTestOok Description It is not required to modify this register any more on the SX1239 V2b. 9.4. AFC Control The following differences are observed between silicon revisions V2a and V2b: 9.4.1. AfcAutoClearOn On the SX1239 V2a, it is required to manually clear AfcValue in RegAfcFei, when the device is in Rx mode. AfcAutoClear function is fully functional on the silicon version V2b. 9.4.2. LowBetaAfcOn and LowBetaAfcOffset Those two bits enable a functionality that was not available on the silicon version V2a. Rev 2 - April 2010 Page 71 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET 10. Revision History Table 28 Revision History Revision 1 Date Feb 2010 Comment First FINAL datasheet version Update DIOx mapping tables Simplify and clarify the description of the AGC Add temperature sensor's approximate measurement time Optimize suggested frequency hopping sequences, section 4.2.5 Modify Listen mode resolution description List in Section 9 the differences between chip versions V2a and V2b Describe handling method for Packets larger than the FIFO size Document AFC for low modulation index, timing diagrams, adjust Tana Document RegTestAfc at address 0x71 Add section describing setup for low modulation index systems Add application schematics 2 April 2010 Rev 2 - April 2010 Page 72 www.semtech.com SX1239 ADVANCED COMMUNICATIONS & SENSING DATASHEET (c) Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Contact information Semtech Corporation Advanced Communication and Sensing Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 E-mail: sales@semtech.com acsupport@semtech.com Internet: http://www.semtech.com Rev 2 - April 2010 Page 73 www.semtech.com |
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