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| C161V / C161K / C161O 16-Bit CMOS Single-Chip Microcontrollers User's Manual 12.96 Version 1.0 ht tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/ Edition 12.96 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. C161V / C161K / C161O Revision History: Previous Version: Page Page (in previous (in current version) version) Original Version 1.0 (12.96) - Subjects (major changes since last revision) 1996 Contents / C161 Table of Contents Page 1 1.1 1.2 1.3 2 2.1 2.1.1 2.1.2 2.2 2.3 2.4 3 3.1 3.2 3.3 3.4 4 4.1 4.1.1 4.2 4.3 4.4 5 5.1 5.1.1 5.2 5.3 5.4 5.5 5.5.1 5.6 5.7 6 6.1 6.1.1 6.2 6.2.1 6.3 6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 The Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . . . 1-1 Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 High Instruction Bandwidth / Fast Execution . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . . . . . . . . 2-6 The On-chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 The On-chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Internal ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Internal RAM and SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 The Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Particular Pipeline Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . . . 5-13 Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Alternate Functions of PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Alternate Functions of PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Alternate Functions of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Semiconductor Group I-1 1996 Contents / C161 Table of Contents Page 6.4 6.4.1 6.5 6.5.1 6.6 6.6.1 6.7 6.7.1 7 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.1.1 9.1.2 9.1.3 9.2 9.2.1 9.2.2 9.2.3 10 10.1 10.2 10.3 10.4 10.5 11 11.1 11.2 11.3 11.4 11.5 12 13 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Alternate Functions of Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Alternate Functions of Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Alternate Functions of Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Alternate Functions of Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 The External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 External Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Programmable Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Controlling the External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 EBC Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 The XBUS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Timer Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 GPT1 Core Timer T3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 GPT1 Auxiliary Timers T2 and T4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Interrupt Control for GPT1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Timer Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 GPT2 Core Timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 GPT2 Auxiliary Timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 Interrupt Control for GPT2 Timers and CAPREL . . . . . . . . . . . . . . . . . . . . 9-26 The Asynchronous/Synchr. Serial Interface . . . . . . . . . . . . . . . . . . . . . 10-1 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 ASC0 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 ASC0 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 The High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . 11-1 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 SSC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 The Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 The Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Semiconductor Group I-2 1996 Contents / C161 Table of Contents Page 14 15 15.1 15.2 15.3 16 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 17 17.1 17.2 17.3 17.4 18 19 20 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 Status of Output Pins during Idle and Power Down Mode . . . . . . . . . . . . . 15-4 System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 Stack Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 Register Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 Procedure Call Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 Table Searching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 Peripheral Control and Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 Floating Point Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 Trap/Interrupt Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 Unseparable Instruction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 Overriding the DPP Addressing Mechanism . . . . . . . . . . . . . . . . . . . . . . 16-13 Handling the Internal ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 Pits, Traps and Mines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 The Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 CPU General Purpose Registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 Special Function Registers ordered by Name . . . . . . . . . . . . . . . . . . . . . . 17-4 Registers ordered by Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 Special Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 Semiconductor Group I-3 10Jul97@15:19h Introduction / C161 1 Introduction The rapidly growing area of embedded control applications is representing one of the most timecritical operating environments for today's microcontrollers. Complex control algorithms have to be processed based on a large number of digital as well as analog input signals, and the appropriate output signals must be generated within a defined maximum response time. Embedded control applications also are often sensitive to board space, power consumption, and overall system cost. Embedded control applications therefore require microcontrollers, which... * offer a high level of system integration * eliminate the need for additional peripheral devices and the associated software overhead * provide system security and fail-safe mechanisms. With the increasing complexity of embedded control applications, a significant increase in CPU performance and peripheral functionality over conventional 8-bit controllers is required from microcontrollers for high-end embedded control systems. In order to achieve this high performance goal Siemens has decided to develop its family of 16-bit CMOS microcontrollers without the constraints of backward compatibility. Of course the architecture of the 16-bit microcontroller family pursues successfull hardware and software concepts, which have been established in Siemens's popular 8-bit controller families. 1.1 The Members of the 16-bit Microcontroller Family The microcontrollers of the Siemens 16-bit family have been designed to meet the high performance requirements of real-time embedded control applications. The architecture of this family has been optimized for high instruction throughput and minimum response time to external stimuli (interrupts). Intelligent peripheral subsystems have been integrated to reduce the need for CPU intervention to a minimum extent. This also minimizes the need for communication via the external bus interface. The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive, industrial control, or data communications. The core of the 16-bit family has been developped with a modular family concept in mind. All family members execute an efficient control-optimized instruction set (additional instructions for members of the second generation). This allows an easy and quick implementation of new family members with different internal memory sizes and technologies, different sets of on-chip peripherals and/or different numbers of IO pins. The XBUS concept opens a straight forward path for the integration of application specific peripheral modules in addition to the standard on-chip peripherals in order to build application specific derivatives. As programs for embedded control applications become larger, high level languages are favoured by programmers, because high level language programs are easier to write, to debug and to maintain. Semiconductor Group 1-1 10Jul97@15:19h Introduction / C161 The 80C166-type microcontrollers were the first generation of the 16-bit controller family. These devices have established the C166 architecture. The C165-type and C167-type devices are members of the second generation of this family. This second generation is even more powerful due to additional instructions for HLL support, an increased address space, increased internal RAM and highly efficient management of various resources on the external bus. Utilizing integration to design efficient systems may require the integration of application specific peripherals to boost system performance, while minimizing the part count. These efforts are supported by the so-called XBUS, defined for the Siemens 16-bit microcontrollers (second generation). This XBUS is an internal representation of the external bus interface that opens and simplifies the integration of peripherals by standardizing the required interface. One representative taking advantage of this technology is the integrated CAN module that is offered by some devices. The C165-type devices are reduced versions of the C167 which provide a smaller package and reduced power consumption at the expense of the A/D converter, the CAPCOM units and the PWM module. The C161 derivatives are especially suited for cost sensitive applications. A variety of different versions is provided which offer mask-programmable ROM, Flash memory or no non-volatile memory at all. Also there are devices with specific functional units. The devices may be offered in different packages, temperature ranges and speed classes. More standard and application-specific derivatives are planned and in development. Information about specific versions and derivatives will be made available with the devices themselves. Contact your Siemens representative for up-to-date material. Note: As the architecture and the basic features (ie. CPU core and built in peripherals) are identical for most of the currently offered versions of the C161, the descriptions within this manual that refer to the "C161" also apply to the other variations, unless otherwise noted. Especially those parts which refer exclusively to a single derivative are marked. Semiconductor Group 1-2 10Jul97@15:19h Introduction / C161 1.2 Summary of Basic Features The C161 is a cost effective representative of the Siemens family of full featured 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with high peripheral functionality. Several key features contribute to the high performance of the C161. High Performance 16-Bit CPU With Four-Stage Pipeline * * * * * * * 125 ns minimum instruction cycle time, with most instructions executed in 1 cycle 625 ns multiplication (16-bit *16-bit), 1.25 s division (32-bit/16-bit) Multiple high bandwidth internal data buses Register based design with multiple variable register banks Single cycle context switching support 4 MBytes linear address space for code and data (von Neumann architecture) System stack cache support with automatic stack overflow/underflow detection Control Oriented Instruction Set with High Efficiency * * * * * Bit, byte, and word data types Flexible and efficient addressing modes for high code density Enhanced boolean bit manipulation with direct addressability of 4 Kbits for peripheral control and user defined flags Hardware traps to identify exception conditions during runtime HLL support for semaphore operations and efficient data access Integrated On-chip Memory * * Internal RAM for variables, register banks, system stack and code (2 KByte on the C161O, 1 KByte on the C161V C161K) Internal Mask ROM, OTP or Flash memory (not for romless devices) External Bus Interface * * * * Multiplexed or demultiplexed bus configurations (MUX only on C161V) Segmentation capability and chip select signal generation (not on the C161V) 8-bit or 16-bit data bus Bus cycle characteristics selectable for five programmable address areas 16-Priority-Level Interrupt System * * * 20/14 interrupt nodes (C161O/C161V/K) with separate interrupt vectors 315/625 ns typical/maximum interrupt latency in case of internal program execution Fast external interrupts Semiconductor Group 1-3 10Jul97@15:19h Introduction / C161 8-Channel Peripheral Event Controller (PEC) * * * Interrupt driven single cycle data transfer Transfer count option (standard CPU interrupt after a programmable number of PEC transfers) Eliminates overhead of saving and restoring system state for interrupt requests Intelligent On-chip Peripheral Subsystems * Multifunctional General Purpose Timer Units GPT1: three 16-bit timers/ counters, 500 ns maximum resolution GPT2: two 16-bit timers/counters, 250 ns maximum resolution (C161O only) Asynchronous/Synchronous Serial Channel (USART) with baud rate generator, parity, framing, and overrun error detection High Speed Synchronous Serial Channel programmable data length and shift direction Watchdog Timer with programmable time intervals Bootstrap Loader for flexible system initialization (not in the C161V) * * * * 63 IO Lines With Individual Bit Addressability * * Tri-stated in input mode Push/pull or open drain output mode Different Temperature Ranges * 0 to +70 C, -40 to +85 C Siemens CMOS Process * Low Power CMOS Technology, including power saving Idle and Power Down modes 80-Pin Plastic Quad Flat Pack (PQFP) Package * P-MQFP, 14*14 mm body, 0.65 mm (25.6 mil) lead spacing, surface mount technology Semiconductor Group 1-4 10Jul97@15:19h Introduction / C161 Device Cross-Reference The table below describes the differences between the three derivatives described in this data sheet. This table provides an overview on the capabilities of each derivative for a quick comparison. Feature Internal RAM Size (IRAM) Chip Select Signals Bus Modes Power Saving Modes Fast External Interrupts General Purpose Timer Unit 1 (GPT1) Input / Output Functionality of GPT1 General Purpose Timer Unit 2 (GPT2) with Capture Input (CAPIN) Functionality Built-in Bootstrap Loader C161V 1 KByte --MUX --4 yes ------- C161K 1 KByte 2 MUX / Demux yes 4 yes yes --yes C161O 2 KBytes 4 MUX / Demux yes 7 yes yes yes yes Complete Development Support A variety of software and hardware development tools for the Siemens family of 16-bit microcontrollers is available from experienced international tool suppliers. The high quality and reliability of these tools is already proven in many applications and by many users. The tool environment for the Siemens 16-bit microcontrollers includes the following tools: * * * * * * * * * * * * * Compilers (C, MODULA2, FORTH) Macro-Assemblers, Linkers, Locaters, Library Managers, Format-Converters Architectural Simulators HLL debuggers Real-Time operating systems VHDL chip models In-Circuit Emulators (based on bondout or standard chips) Plug-In emulators Emulation and Clip-Over adapters, production sockets Logic Analyzer disassemblers Evaluation Boards with monitor programs Industrial boards (also for CAN, FUZZY, PROFIBUS, FORTH applications) Network driver software (CAN, PROFIBUS) Semiconductor Group 1-5 10Jul97@15:19h Introduction / C161 1.3 Abbreviations The following acronyms and termini are used within this document: ALE . . . . . . . . . . Address Latch Enable ALU . . . . . . . . . . Arithmetic and Logic Unit ASC . . . . . . . . . Asynchronous/synchronous Serial Controller CISC . . . . . . . . . Complex Instruction Set Computing CMOS . . . . . . . . Complementary Metal Oxide Silicon CPU . . . . . . . . . Central Processing Unit EBC . . . . . . . . . External Bus Controller ESFR . . . . . . . . Extended Special Function Register Flash . . . . . . . . . Non-volatile memory that may be electrically erased GPR . . . . . . . . . General Purpose Register GPT . . . . . . . . . General Purpose Timer unit HLL . . . . . . . . . . High Level Language IO . . . . . . . . . . . Input / Output OTP . . . . . . . . . One Time Programmable non-volatile Memory PEC . . . . . . . . . Peripheral Event Controller PLA . . . . . . . . . . Programmable Logic Array RAM . . . . . . . . . Random Access Memory RISC . . . . . . . . . Reduced Instruction Set Computing ROM . . . . . . . . . Read Only Memory SFR. . . . . . . . . . Special Function Register SSC . . . . . . . . . Synchronous Serial Controller XBUS . . . . . . . . Internal representation of the External Bus Semiconductor Group 1-6 10Jul97@15:19h Architectural Overview / C161 2 Architectural Overview The architecture of the C161 combines the advantages of both RISC and CISC processors in a very well-balanced way. The sum of the features which are combined result in a high performance microcontroller, which is the right choice not only for today's applications, but also for future engineering challenges. The C161 not only integrates a powerful CPU core and a set of peripheral units into one chip, but also connects the units in a very efficient way. One of the four buses used concurrently on the C161 is the XBUS, an internal representation of the external bus interface. This bus provides a standardized method of integrating application-specific peripherals to produce derivates of the standard C161. Figure 2-1 C161 Functional Block Diagram Semiconductor Group 2-1 10Jul97@15:19h Architectural Overview / C161 2.1 Basic CPU Concepts and Optimizations The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware is provided for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Figure 2-2 CPU Block Diagram To meet the demand for greater performance and flexibility, a number of areas has been optimized in the processor core. Functional blocks in the CPU core are controlled by signals from the instruction decode logic. These are summarized below, and described in detail in the following sections: 1) High Instruction Bandwidth / Fast Execution 2) High Function 8-bit and 16-bit Arithmetic and Logic Unit 3) Extended Bit Processing and Peripheral Control 4) High Performance Branch-, Call-, and Loop Processing 5) Consistent and Optimized Instruction Formats 6) Programmable Multiple Priority Interrupt Structure Semiconductor Group 2-2 10Jul97@15:19h Architectural Overview / C161 High Instruction Bandwidth / Fast Execution Based on the hardware provisions, most of the C161's instructions can be exected in just one machine cycle, which requires 125 ns at 16 MHz CPU clock. For example, shift and rotate instructions are always processed within one machine cycle, independent of the number of bits to be shifted. Branch-, multiply- and divide instructions normally take more than one machine cycle. These instructions, however, have also been optimized. For example, branch instructions only require an additional machine cycle, when a branch is taken, and most branches taken in loops require no additional machine cycles at all, due to the so-called `Jump Cache'. A 32-bit / 16-bit division takes 1s, a 16-bit * 16-bit multiplication takes 0.625 s. The instruction cycle time has been dramatically reduced through the use of instruction pipelining. This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel. The following four stage pipeline provides the optimum balancing for the CPU core: FETCH: In this stage, an instruction is fetched from the internal ROM or RAM or from the external memory, based on the current IP value. DECODE: In this stage, the previously fetched instruction is decoded and the required operands are fetched. EXECUTE: In this stage, the specified operation is performed on the previously fetched operands. WRITE BACK: In this stage, the result is written to the specified location. If this technique were not used, each instruction would require four machine cycles. This increased performance allows a greater number of tasks and interrupts to be processed. Instruction Decoder Instruction decoding is primarily generated from PLA outputs based on the selected opcode. No microcode is used and each pipeline stage receives control signals staged in control registers from the decode stage PLAs. Pipeline holds are primarily caused by wait states for external memory accesses and cause the holding of signals in the control registers. Multiple-cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals. High Function 8-bit and 16-bit Arithmetic and Logic Unit All standard arithmetic and logical operations are performed in a 16-bit ALU. In addition, for byte operations, signals are provided from bits six and seven of the ALU result to correctly set the condition flags. Multiple precision arithmetic is provided through a 'CARRY-IN' signal to the ALU from previously calculated portions of the desired operation. Most internal execution blocks have been optimized to perform operations on either 8-bit or 16-bit quantities. Once the pipeline has been filled, one instruction is completed per machine cycle, except for multiply and divide. An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle. Thus, these operations use two coupled 16-bit registers, MDL and MDH, and require four and nine machine cycles, respectively, to perform a 16-bit by 16-bit (or 32-bit by 16-bit) calculation plus one machine cycle to setup and adjust the operands and the result. Even these Semiconductor Group 2-3 10Jul97@15:19h Architectural Overview / C161 longer multiply and divide instructions can be interrupted during their execution to allow for very fast interrupt response. Instructions have also been provided to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations. The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements. A set of consistent flags is automatically updated in the PSW after each arithmetic, logical, shift, or movement operation. These flags allow branching on specific conditions. Support for both signed and unsigned arithmetic is provided through user-specifiable branch tests. These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine. All targets for branch calculations are also computed in the central ALU. A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotates and arithmetic shifts are also supported. Extended Bit Processing and Peripheral Control A large number of instructions has been dedicated to bit processing. These instructions provide efficient control and testing of peripherals while enhancing data manipulation. Unlike other microcontrollers, these instructions provide direct access to two operands in the bit-addressable space without requiring to move them into temporary flags. The same logical instructions available for words and bytes are also supported for bits. This allows the user to compare and modify a control bit for a peripheral in one instruction. Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations. These are also performed in a single machine cycle. In addition, bit field instructions have been provided, which allow the modification of multiple bits from one operand in a single instruction. High Performance Branch-, Call-, and Loop Processing Due to the high percentage of branching in controller applications, branch instructions have been optimized to require one extra machine cycle only when a branch is taken. This is implemented by precalculating the target address while decoding the instruction. To decrease loop execution overhead, three enhancements have been provided: * The first solution provides single cycle branch execution after the first iteration of a loop. Thus, only one machine cycle is lost during the execution of the entire loop. In loops which fall through upon completion, no machine cycles are lost when exiting the loop. No special instructions are required to perform loops, and loops are automatically detected during execution of branch instructions. * The second loop enhancement allows the detection of the end of a table and avoids the use of two compare instructions embedded in loops. One simply places the lowest negative number at the end of the specific table, and specifies branching if neither this value nor the compared value have been found. Otherwise the loop is terminated if either condition has been met. The terminating condition can then be tested. * The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction which is found in other microcontrollers. Through the use of Compare and Increment or Decrement instructions, the user can make comparisons to any value. This allows loop counters to cover any range. This is particularly advantageous in table searching. Semiconductor Group 2-4 10Jul97@15:19h Architectural Overview / C161 Saving of system state is automatically performed on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines. Call instructions push the value of the IP on the system stack, and require the same execution time as branch instructions. Instructions have also been provided to support indirect branch and call instructions. This supports implementation of multiple CASE statement branching in assembler macros and high level languages. Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined design, an instruction set has been designed which incorporates concepts from Reduced Instruction Set Computing (RISC). These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds. These concepts, however, do not preclude the use of complex instructions, which are required by microcontroller users. The following goals were used to design the instruction set: 1) Provide powerful instructions to perform operations which currently require sequences of instructions and are frequently used. Avoid transfer into and out of temporary registers such as accumulators and carry bits. Perform tasks in parallel such as saving state upon entry into interrupt routines or subroutines. Avoid complex encoding schemes by placing operands in consistent fields for each instruction. Also avoid complex addressing modes which are not frequently used. This decreases the instruction decode time while also simplifying the development of compilers and assemblers. Provide most frequently used instructions with one-word instruction formats. All other instructions are placed into two-word formats. This allows all instructions to be placed on word boundaries, which alleviates the need for complex alignment hardware. It also has the benefit of increasing the range for relative branching instructions. 2) 3) The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly functional C161 instruction set which includes the following instruction classes: * * * * * * * * * * * * Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions Possible operand types are bits, bytes and words. Specific instruction support the conversion (extension) of bytes to words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Semiconductor Group 2-5 10Jul97@15:19h Architectural Overview / C161 Programmable Multiple Priority Interrupt System The following enhancements have been included to allow processing of a large number of interrupt sources: 1) Peripheral Event Controller (PEC): This processor is used to off-load many interrupt requests from the CPU. It avoids the overhead of entering and exiting interrupt or trap routines by performing single-cycle interrupt-driven byte or word data transfers between any two locations in segment 0 with an optional increment of either the PEC source or the destination pointer. Just one cycle is 'stolen' from the current CPU activity to perform a PEC service. Multiple Priority Interrupt Controller: This controller allows all interrupts to be placed at any specified priority. Interrupts may also be grouped, which provides the user with the ability to prevent similar priority tasks from interrupting each other. For each of the possible interrupt sources there is a separate control register, which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Multiple Register Banks: This feature allows the user to specify up to sixteen general purpose registers located anywhere in the internal RAM. A single one-machine-cycle instruction allows to switch register banks from one task to another. Interruptable Multiple Cycle Instructions: Reduced interrupt latency is provided by allowing multiple-cycle instructions (multiply, divide) to be interruptable. 2) 3) 4) With an interrupt response time within a range from just 315 ns to 625 ns (in case of internal program execution), the C161 is capable of reacting very fast on non-deterministic events. Its fast external interrupt inputs are sampled every 65 ns and allow to recognize even very short external signals. The C161 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so called 'Hardware Traps'. Hardware traps cause an immediate non-maskable system reaction which is similiar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except for another higher prioritized trap service being in progress, a hardware trap will interrupt any current program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Software interrupts are supported by means of the 'TRAP' instruction in combination with an individual trap (interrupt) number. Semiconductor Group 2-6 10Jul97@15:19h Architectural Overview / C161 2.2 The On-chip System Resources The C161 controllers provide a number of powerful system resources designed around the CPU. The combination of CPU and these resources results in the high performance of the members of this controller family. Peripheral Event Controller (PEC) and Interrupt Control The Peripheral Event Controller allows to respond to an interrupt request with a single data transfer (word or byte) which only consumes one instruction cycle and does not require to save and restore the machine status. Each interrupt source is prioritized every machine cycle in the interrupt control block. If PEC service is selected, a PEC transfer is started. If CPU interrupt service is requested, the current CPU priority level stored in the PSW register is tested to determine whether a higher priority interrupt is currently being serviced. When an interrupt is acknowledged, the current state of the machine is saved on the internal system stack and the CPU branches to the system specific vector for the peripheral. The PEC contains a set of SFRs which store the count value and control bits for eight data transfer channels. In addition, the PEC uses a dedicated area of RAM which contains the source and destination addresses. The PEC is controlled similar to any other peripheral through SFRs containing the desired configuration of each channel. An individual PEC transfer counter is implicitly decremented for each PEC service except forming in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the vector location related to the corresponding source. PEC services are very well suited, for example, to move register contents to/from a memory table. The C161 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. Memory Areas The memory space of the C161 is configured in a Von Neumann architecture which means that code memory, data memory, registers and IO ports are organized within the same linear address space which covers up to 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. A 16-bit wide internal RAM (IRAM) provides fast access to General Purpose Registers (GPRs), user data (variables) and system stack. The internal RAM may also be used for code. A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data. The size of the internal RAM is ... ... 2 KByte for the C161O, ... 1 KByte for the C161V and the C161K. The CPU disposes of an actual register context consisting of up to 16 wordwide and/or bytewide GPRs, which are physically located within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. Semiconductor Group 2-7 10Jul97@15:19h Architectural Overview / C161 A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is also located within the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions. An optional internal ROM provides for both code and constant data storage. This memory area is connected to the CPU via a 32-bit-wide bus. Thus, an entire double-word instruction can be fetched in just one machine cycle. Program execution from the on-chip ROM is the fastest of all possible alternatives. For Special Function Registers 1024 Bytes of the address space are reserved. The standard Special Function Register area (SFR) uses 512 bytes, while the Extended Special Function Register area (ESFR) uses the other 512 bytes. (E)SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused (E)SFR addresses are reserved for future members of the C161 family with enhanced functionality. External Bus Interface In order to meet the needs of designs where more memory is required than is provided on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller via its external bus interface. The integrated External Bus Controller (EBC) allows to access external memory and/ or peripheral resources in a very flexible way. For up to five address areas the bus mode (multiplexed / demultiplexed), the data bus width (8-bit / 16-bit) and even the length of a bus cycle (waitstates, signal delays) can be selected independently. This allows to access a variety of memory and peripheral components directly and with maximum efficiency. If the device does not run in Single Chip Mode, where no external memory is required, the EBC can control external accesses in one of the following four different external access modes: q q q q 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed The demultiplexed bus modes use PORT1 for addresses and PORT0 for data input/output. The multiplexed bus modes use PORT0 for both addresses and data input/output. All modes use Port 4 for the upper address lines (A16...) if selected. Important timing characteristics of the external bus interface (waitstates, ALE length and Read/ Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and/or peripherals. For applications which require less than 64 KBytes of address space, a non-segmented memory model can be selected, where all locations can be addressed by 16 bits, and thus Port 4 is not needed as an output for the upper address bits (A21/A19/A17...A16), as is the case when using the segmented memory model. Note: The Demultiplexed bus modes are supported by the C161K and the C161O, not by the C161V. Semiconductor Group 2-8 10Jul97@15:19h Architectural Overview / C161 The on-chip XBUS is an internal representation of the external bus and allows to access integrated application-specific peripherals/modules in the same way as external components. It provides a defined interface for these customized peripherals. The C161 derivatives have no X-Peripherals implemented. Clock Generator The on-chip clock generator provides the C161 with its basic clock signal that controls all activities of the controller hardware. Its oscillator can either run with an external crystal and appropriate oscillator circuitry (see also recommendations in chapter Dedicated Pins") or it can be driven by an external oscillator. The oscillator either directly feeds the external clock signal to the controller hardware (through buffers, of course) or divides the external clock frequency by 2. This resulting internal clock signal is also referred to as "CPU clock". Two separated clock signals are generated for the CPU itself and the peripheral part of the chip. While the CPU clock is stopped during the idle mode, the peripheral clock keeps running. Both clocks are switched off, when the power down mode is entered. Figure 2-3 Clock Generation Block Diagram C161 Clock Generation Modes Reset Configuration P0.15-13 (P0H.7-5) 1 0 1) 2) CPU Frequency External Clock Input Range 2 to 32 MHz 1 to 16 MHz 2) X X X X fXTAL / 2 fXTAL * 1 1) 2) Prescaler operation. Default configuration after reset. Direct drive: the maximum frequency depends on the duty cycle of the external clock signal. In emulation mode pin P0.15 (P0H.7) is inverted, ie. the configuration '1XX' would select direct drive in emulation mode. Semiconductor Group 2-9 10Jul97@15:19h Architectural Overview / C161 Prescaler Operation When pins P0.15-13 (P0H.7-5) equal '001' (C163) during reset ('1XX' on the C165) the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (ie. the duration of an individual TCL) is defined by the period of the input clock f XTAL. The timings listed in the AC Characteristics" of the data sheet that refer to TCLs therefore can be calculated using the period of fXTAL for any TCL. Direct Drive When pins P0.15-13 (P0H.7-5) equal '011' (C163) during reset ('0XX' on the C165) the clock system is directly driven from the internal oscillator with the input clock signal, ie. f OSC = fCPU. The maximum input clock frequency depends on the clock signal's duty cycle, because the minimum values for the clock phases (TCLs) must be respected. Semiconductor Group 2-10 10Jul97@15:19h Architectural Overview / C161 2.3 The On-chip Peripheral Blocks The C161 family clearly separates peripherals from the core. This structure permits the maximum number of operations to be performed in parallel and allows peripherals to be added or deleted from family members without modifications to the core. Each functional block processes data independently and communicates information over common buses. Peripherals are controlled by data written to the respective Special Function Registers (SFRs). These SFRs are located either within the standard SFR area (00'FE00H...00'FFFFH) or within the extended ESFR area (00'F000H...00'F1FFH). These built in peripherals either allow the CPU to interface with the external world, or provide functions on-chip that otherwise were to be added externally in the respective system. The C161 peripherals are: * Two General Purpose Timer Blocks GPT1 and GPT2 (C161O only) * An Asynchronous/Synchronous Serial Interface ASC0 * A High-Speed Synchronous Serial Interface SSC * A Watchdog Timer * Seven IO ports with a total of 63 IO lines Each peripheral also contains a set of Special Function Registers (SFRs), which control the functionality of the peripheral and temporarily store intermediate data results. Each peripheral has an associated set of status flags. Individually selected clock signals are generated for each peripheral from binary multiples of the CPU clock. Peripheral Interfaces The on-chip peripherals generally have two different types of interfaces, an interface to the CPU and an interface to external hardware. Communication between CPU and peripherals is performed through Special Function Registers (SFRs) and interrupts. The SFRs serve as control/status and data registers for the peripherals. Interrupt requests are generated by the peripherals based on specific events which occur during their operation (eg. operation complete, error, etc.). For interfacing with external hardware, specific pins of the parallel ports are used, when an input or output function has been selected for a peripheral. During this time, the port pins are controlled by the peripheral (when used as outputs) or by the external hardware which controls the peripheral (when used as inputs). This is called the 'alternate (input or output) function' of a port pin, in contrast to its function as a general purpose IO pin. Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock (fCPU). The on-chip oscillator derives the CPU clock from the crystal or from the external clock signal. The clock signal which is gated to the peripherals is independent from the clock signal which feeds the CPU. During Idle mode the CPU's clock is stopped while the peripherals continue their operation. Peripheral SFRs may be accessed by the CPU once per state. When an SFR is written to by software in the same state where it is also to be modified by the peripheral, the software write operation has priority. Further details on peripheral timing are included in the specific sections about each peripheral. Semiconductor Group 2-11 10Jul97@15:19h Architectural Overview / C161 Programming Hints Access to SFRs All SFRs reside in data page 3 of the memory space. The following addressing mechanisms allow to access the SFRs: * indirect or direct addressing with 16-bit (mem) addresses it must be guaranteed that the used data page pointer (DPP0...DPP3) selects data page 3. * accesses via the Peripheral Event Controller (PEC) use the SRCPx and DSTPx pointers instead of the data page pointers. * short 8-bit (reg) addresses to the standard SFR area do not use the data page pointers but directly access the registers within this 512 Byte area. * short 8-bit (reg) addresses to the extended ESFR area require switching to the 512 Byte extended SFR area. This is done via the EXTension instructions EXTR, EXTP(R), EXTS(R). Byte write operations to word wide SFRs via indirect or direct 16-bit (mem) addressing or byte transfers via the PEC force zeros in the non-addressed byte. Byte write operations via short 8-bit (reg) addressing can only access the low byte of an SFR and force zeros in the high byte. It is therefore recommended, to use the bit field instructions (BFLDL and BFLDH) to write to any number of bits in either byte of an SFR without disturbing the non-addressed byte and the unselected bits. Reserved Bits Some of the bits which are contained in the C161's SFRs are marked as 'Reserved'. User software should never write '1's to reserved bits. These bits are currently not implemented and may be used in future products to invoke new functions. In this case, the active state for these functions will be '1', and the inactive state will be '0'. Therefore writing only `0's to reserved locations provides portability of the current software to future devices. Read accesses to reserved bits return `0's. Parallel Ports The C161 provides up to 63 IO lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A21/19/17...A16 in systems where segmentation is used to access more than 64 KBytes of memory. Port 6 provides chip select signals. Port 2 accepts the fast external interrupt inputs. Port 3 includes alternate functions of timers, serial interfaces and the optional bus control signal BHE/WRH. Port 5 is used for timer control signals. All port lines that are not used for these alternate functions may be used as general purpose IO lines. Semiconductor Group 2-12 10Jul97@15:19h Architectural Overview / C161 Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 500 KBaud and half-duplex synchronous communication at up to 2 MBaud @ 16 MHz CPU clock. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The SSC supports full-duplex synchronous communication at up to 4 Mbaud @ 16 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data. Semiconductor Group 2-13 10Jul97@15:19h Architectural Overview / C161 General Purpose Timer (GPT) Unit The GPT units represent a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The five 16-bit timers are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Note: GPT1 is provided in all C161 derivatives, while GPT2 is only provided in the C161O. Each GPT1 timer can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events (via TxIN). Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the `gate' level on its external input pin TxIN. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal (TxEUD) to facilitate eg. position tracking. The core timers T3 and T6 have output toggle latches (TxOTL) which change their state on each timer over-flow/underflow. The state of these latches may be used internally to concatenate the core timers with the respective auxiliary timers resulting in 32/33-bit timers/counters for measuring long time periods with high resolution. The state of T3OTL may be output on a port pin (T3OUT). Various reload or capture functions can be selected to reload timers or capture a timer's contents triggered by an external signal or a selectable transition of toggle latch TxOTL. The GPT2 timers operate in timer mode. The maximum resolution of the timers in module GPT1 is 500 ns (@ 16 MHz CPU clock). With its maximum resolution of 250 ns (@ 16 MHz CPU clock) the GPT2 timers provide precise event control and time measurement. Note: The C161V does not provide external connections for its timers. Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to reset. The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced Semiconductor Group 2-14 10Jul97@15:19h Architectural Overview / C161 by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 31 s and 525 ms can be monitored (@ 16 MHz). The default Watchdog Timer interval after reset is 8.2 ms (@ 16 MHz). 2.4 Protected Bits The C161 provides a special mechanism to protect bits which can be modified by the on-chip hardware from being changed unintentionally by software accesses to related bits (see also chapter "The Central Processing Unit"). The following bits are protected: Register T2IC, T3IC, T4IC T5IC, T6IC CRIC T3CON, T6CON S0TIC, S0TBIC S0RIC, S0EIC S0CON SSCTIC, SSCRIC SSCEIC SSCCON SSCCON SSCCON TFR TFR 1) Bit Name T2IR, T3IR, T4IR T5IR, T6IR CRIR T3OTL, T6OTL S0TIR, S0TBIR S0RIR, S0EIR S0REN SSCTIR, SSCRIR SSCEIR SSCBSY SSCBE, SSCPE SSCRE, SSCTE TFR.15,14,13 TFR.7,3,2,1,0 1) Notes GPT1 timer interrupt request flags GPT2 timer interrupt request flags 1) GPT2 CAPREL interrupt request flag GPTx timer output toggle latches ASC0 transmit(buffer) interrupt request flags ASC0 receive/error interrupt request flags ASC0 receiver enable flag SSC transmit/receive interrupt request flags SSC error interrupt request flag SSC busy flag SSC error flags SSC error flags Class A trap flags Class B trap flags Only in the C161O. = 29 protected bits in the C161O, 26 protected bits in the C161V and C161K. Semiconductor Group 2-15 15Jul97@11:09h Memory Organization / C161 3 Memory Organization The memory space of the C161 is configured in a "Von Neumann" architecture. This means that code and data are accessed within the same linear address space. All of the physically separated memory areas, including internal ROM/Flash (where integrated), internal RAM, the internal Special Function Register Areas (SFRs and ESFRs), the address areas for integrated XBUS peripherals (eg. SSP module) and external memory are mapped into one common address space. The C161 provides a total addressable memory space of 16 MBytes. This address space is arranged as 256 segments of 64 KBytes each, and each segment is again subdivided into four data pages of 16 KBytes each (see figure below). Figure 3-1 Memory Areas and Address Space Semiconductor Group 3-1 15Jul97@11:09h Memory Organization / C161 Most internal memory areas are mapped into segment 0, the system segment. The upper 4 KByte of segment 0 (00'F000H...00'FFFFH) hold the Internal RAM and Special Function Register Areas (SFR and ESFR). The lower 32 KByte of segment 0 (00'0000H...00'7FFFH) may be occupied by a part of the on-chip ROM or Flash memory and is called the Internal ROM area. This ROM area can be remapped to segment 1 (01'0000H...01'7FFFH), to enable external memory access in the lower half of segment 0, or the internal ROM may be disabled at all. Code and data may be stored in any part of the internal memory areas, except for the SFR blocks, which may be used for control / data, but not for instructions. Note: Accesses to the internal ROM area on ROMless devices will produce unpredictable results. Bytes are stored at even or odd byte addresses. Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte address. Double words (code only) are stored in ascending memory locations as two subsequent words. Single bits are always stored in the specified bit position at a word address. Bit position 0 is the least significant bit of the byte at an even byte address, and bit position 15 is the most significant bit of the byte at the next odd byte address. Bit addressing is supported for a part of the Special Function Registers, a part of the internal RAM and for the General Purpose Registers. Figure 3-2 Storage of Words, Byte and Bits in a Byte Organized Memory Note: Byte units forming a single word or a double word must always be stored within the same physical (internal, external, ROM, RAM) and organizational (page, segment) memory area. Semiconductor Group 3-2 15Jul97@11:09h Memory Organization / C161 3.1 Internal ROM The C161 may reserve an address area of variable size (depending on the version) for on-chip mask-programmable ROM (organized as X * 32) or Flash memory. The lower 32 KByte of the onchip ROM/Flash are referred to as "Internal ROM Area". Internal ROM accesses are globally enabled or disabled via bit ROMEN in register SYSCON. This bit is set during reset according to the level on pin EA, or may be altered via software. If enabled, the internal ROM area occupies the lower 32 KByte of either segment 0 or segment 1. This ROM mapping is controlled by bit ROMS1 in register SYSCON. Note: The size of the internal ROM area is independent of the size of the actual implemented ROM. Also devices with less than 32 KByte of ROM or with no ROM at all will have this 32 KByte area occupied, if the ROM is enabled. Devices with larger ROMs provide the mapping option only for the ROM area. Devices with a ROM size above 32 KByte expand the ROM area from the middle of segment 1, ie. starting at address 01'8000H. The internal ROM/Flash can be used for both code (instructions) and data (constants, tables, etc.) storage. Code fetches are always made on even byte addresses. The highest possible code storage location in the internal ROM is either xx'xxFE H for single word instructions, or xx'xxFC H for double word instructions. The respective location must contain a branch instruction (unconditional), because sequential boundary crossing from internal ROM to external memory is not supported and causes erroneous results. Any word and byte data read accesses may use the indirect or long 16-bit addressing modes. There is no short addressing mode for internal ROM operands. Any word data access is made to an even byte address. The highest possible word data storage location in the internal ROM is xx'xxFE H. For PEC data transfers the internal ROM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. The internal ROM is not provided for single bit storage, and therefore it is not bit addressable. Note: The `x' in the locations above depend on the available ROM/Flash memory and on the mapping. The internal ROM may be enabled, disabled or mapped into segment 0 or segment 1 under software control. Chapter "System Programming" shows how to do this and reminds of the precautions that must be taken in order to prevent the system from crashing. Semiconductor Group 3-3 15Jul97@10:59h Memory Organization / C161 3.2 Internal RAM and SFR Area The RAM/SFR area is located within data page 3 and provides access to the on-chip RAM (IRAM, organized as xK*16) and to two 512 Byte blocks of Special Function Registers (SFRs). The C161O provides 2 KByte of IRAM, the C161V and the C161K provide 1 KByte. The internal RAM serves for several purposes: * System Stack (programmable size) * General Purpose Register Banks (GPRs) * Source and destination pointers for the Peripheral Event Controller (PEC) * Variable and other data storage, or * Code storage. Figure 3-3 Internal RAM Area and SFR Areas Note: The upper 256 Bytes of SFR area, ESFR area and internal RAM are bit-addressable (see shaded blocks in the figure above). Semiconductor Group 3-4 15Jul97@11:09h Memory Organization / C161 Code accesses are always made on even byte addresses. The highest possible code storage location in the internal RAM is either 00'FDFEH for single word instructions or 00'FDFCH for double word instructions. The respective location must contain a branch instruction (unconditional), because sequential boundary crossing from internal RAM to the SFR area is not supported and causes erroneous results. Any word and byte data in the internal RAM can be accessed via indirect or long 16-bit addressing modes, if the selected DPP register points to data page 3. Any word data access is made on an even byte address. The highest possible word data storage location in the internal RAM is 00'FDFEH. For PEC data transfers, the internal RAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. The upper 256 Byte of the internal RAM (00'FD00H through 00'FDFFH) and the GPRs of the current bank are provided for single bit storage, and thus they are bit addressable. System Stack The system stack may be defined within the internal RAM. The size of the system stack is controlled by bitfield STKSZ in register SYSCON (see table below). 1) 2) Stack Size (Words) 256 128 64 32 512 ----1024/512 2) 1) Internal RAM Addresses (Words) 00'FBFEH...00'FA00H (Default after Reset) 00'FBFEH...00'FB00H 00'FBFEH...00'FB80H 00'FBFEH...00'FBC0H 00'FBFEH...00'F800H Reserved. Do not use this combination. Reserved. Do not use this combination. 00'FDFEH...00'F600H (Note: No circular stack) This option is not available on the C161V and C161K, as their IRAM area begins at 00'FA00H. The non circular stack" option is also available on the C161V and C161K. However, the maximum stack size here is 512 words as their IRAM area is 00'FDFEH...00'FA00H. For all system stack operations the on-chip RAM is accessed via the Stack Pointer (SP) register. The stack grows downward from higher towards lower RAM address locations. Only word accesses are supported to the system stack. A stack overflow (STKOV) and a stack underflow (STKUN) register are provided to control the lower and upper limits of the selected stack area. These two stack boundary registers can be used not only for protection against data destruction, but also allow to implement a circular stack with hardware supported system stack flushing and filling (except for option '111'). The technique of implementing this circular stack is described in chapter "System Programming". Semiconductor Group 3-5 15Jul97@11:09h Memory Organization / C161 General Purpose Registers The General Purpose Registers (GPRs) use a block of 16 consecutive words within the internal RAM. The Context Pointer (CP) register determines the base address of the currently active register bank. This register bank may consist of up to 16 word GPRs (R0, R1, ..., R15) and/or of up to 16 byte GPRs (RL0, RH0, ..., RL7, RH7). The sixteen byte GPRs are mapped onto the first eight word GPRs (see table below). In contrast to the system stack, a register bank grows from lower towards higher address locations and occupies a maximum space of 32 Byte. The GPRs are accessed via short 2-, 4- or 8-bit addressing modes using the Context Pointer (CP) register as base address (independent of the current DPP register contents). Additionally, each bit in the currently active register bank can be accessed individually. Mapping of General Purpose Registers to RAM Addresses Internal RAM Address The C161 supports fast register bank (context) switching. Multiple register banks can physically exist within the internal RAM at the same time. Only the register bank selected by the Context Pointer register (CP) is active at a given time, however. Selecting a new active register bank is simply done by updating the CP register. A particular Switch Context (SCXT) instruction performs register bank switching and an automatic saving of the previous context. The number of implemented register banks (arbitrary sizes) is only limited by the size of the available internal RAM. Details on using, switching and overlapping register banks are described in chapter "System Programming". Semiconductor Group 3-6 15Jul97@11:09h Memory Organization / C161 PEC Source and Destination Pointers The 16 word locations in the internal RAM from 00'FCE0H to 00'FCFEH (just below the bitaddressable section) are provided as source and destination address pointers for data transfers on the eight PEC channels. Each channel uses a pair of pointers stored in two subsequent word locations with the source pointer (SRCPx) on the lower and the destination pointer (DSTPx) on the higher word address (x = 7...0). Figure 3-4 Location of the PEC Pointers Whenever a PEC data transfer is performed, the pair of source and destination pointers, which is selected by the specified PEC channel number, is accessed independent of the current DPP register contents and also the locations referred to by these pointers are accessed independent of the current DPP register contents. If a PEC channel is not used, the corresponding pointer locations area available and can be used for word or byte data storage. For more details about the use of the source and destination pointers for PEC data transfers see section "Interrupt and Trap Functions". Semiconductor Group 3-7 15Jul97@11:09h Memory Organization / C161 Special Function Registers The functions of the CPU, the bus interface, the IO ports and the on-chip peripherals of the C161 are controlled via a number of so-called Special Function Registers (SFRs). These SFRs are arranged within two areas of 512 Byte size each. The first register block, the SFR area, is located in the 512 Bytes above the internal RAM (00'FFFFH...00'FE00H), the second register block, the Extended SFR (ESFR) area, is located in the 512 Bytes below the internal RAM (00'F1FFH...00'F000H). Special function registers can be addressed via indirect and long 16-bit addressing modes. Using an 8-bit offset together with an implicit base address allows to address word SFRs and their respective low bytes. However, this does not work for the respective high bytes! Note: Writing to any byte of an SFR causes the non-addressed complementary byte to be cleared! The upper half of each register block is bit-addressable, so the respective control/status bits can directly be modified or checked using bit addressing. When accessing registers in the ESFR area using 8-bit addresses or direct bit addressing, an Extend Register (EXTR) instruction is required before, to switch the short addressing mechanism from the standard SFR area to the Extended SFR area. This is not required for 16-bit and indirect addresses. The GPRs R15...R0 are duplicated, ie. they are accessible within both register blocks via short 2-, 4- or 8-bit addresses without switching. Example: EXTR MOV BFLDL BSET MOV #4 ODP2, #data16 DP6, #mask, #data8 DP1H.7 T8REL, R1 ;Switch to ESFR area for the next 4 instructions ;ODP2 uses 8-bit reg addressing ;Bit addressing for bit fields ;Bit addressing for single bits ;T8REL uses 16-bit address, R1 is duplicated... ;...and also accessible via the ESFR mode ;(EXTR is not required for this access) ;The scope of the EXTR #4 instruction ends here! ;T8REL uses 16-bit address, R1 is duplicated... ;...and does not require switching ;------MOV ;------------------T8REL, R1 In order to minimize the use of the EXTR instructions the ESFR area mostly holds registers which are mainly required for initialization and mode selection. Registers that need to be accessed frequently are allocated to the standard SFR area, wherever possible. Note: The tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions, or issue a warning in case of missing or excessive EXTR instructions. Semiconductor Group 3-8 15Jul97@11:09h Memory Organization / C161 3.3 External Memory Space The C161 is capable of using an address space of up to 4 MByte. Only parts of this address space are occupied by internal memory areas. All addresses which are not used for on-chip memory (ROM or RAM) or for registers may reference external memory locations. This external memory is accessed via the C161's external bus interface. Four memory bank sizes are supported: * Non-segmented mode: 64 KByte * 2-bit segmented mode: 256 KByte * 4-bit segmented mode: 1 MByte * 6-bit segmented mode: 4 MByte with A15...A0 on PORT0 or PORT1 with A17...A16 on Port 4 and A15...A0 on PORT0 or PORT1 with A19...A16 on Port 4 and A15...A0 on PORT0 or PORT1 with A21...A16 on Port 4 and A15...A0 on PORT0 or PORT1 Each bank can be directly addressed via the address bus, while the programmable chip select signals can be used to select various memory banks. The C161 also supports four different bus types: * Multiplexed 16-bit Bus * Multiplexed 8-bit Bus * Demultiplexed 16-bit Bus * Demultiplexed 8-bit Bus with address and data on PORT0 (Default after Reset) with address and data on PORT0/P0L with address on PORT1 and data on PORT0 (not on the C161V) with address on PORT1 and data on P0L (not on the C161V) Memory model and bus mode are selected during reset by pin EA and PORT0 pins. For further details about the external bus configuration and control please refer to chapter "The External Bus Interface". External word and byte data can only be accessed via indirect or long 16-bit addressing modes using one of the four DPP registers. There is no short addressing mode for external operands. Any word data access is made to an even byte address. For PEC data transfers the external memory in segment 0 can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. The external memory is not provided for single bit storage and therefore it is not bit addressable. Semiconductor Group 3-9 15Jul97@11:09h Memory Organization / C161 3.4 Crossing Memory Boundaries The address space of the C161 is implicitly divided into equally sized blocks of different granularity and into logical memory areas. Crossing the boundaries between these blocks (code or data) or areas requires special attention to ensure that the controller executes the desired operations. Memory Areas are partitions of the address space that represent different kinds of memory (if provided at all). These memory areas are the internal RAM/SFR area, the internal ROM (if available), the on-chip X-Peripherals (if integrated) and the external memory. Accessing subsequent data locations that belong to different memory areas is no problem. However, when executing code, the different memory areas must be switched explicitly via branch instructions. Sequential boundary crossing is not supported and leads to erroneous results. Note: Changing from the external memory area to the internal RAM/SFR area takes place within segment 0. Segments are contiguous blocks of 64 KByte each. They are referenced via the code segment pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme. During code fetching segments are not changed automatically, but rather must be switched explicitly. The instructions JMPS, CALLS and RETS will do this. In larger sequential programs make sure that the highest used code location of a segment contains an unconditional branch instruction to the respective following segment, to prevent the prefetcher from trying to leave the current segment. Data Pages are contiguous blocks of 16 KByte each. They are referenced via the data page pointers DPP3...0 and via an explicit data page number for data accesses overriding the standard DPP scheme. Each DPP register can select one of the possible 1024 data pages. The DPP register that is used for the current access is selected via the two upper bits of the 16-bit data address. Subsequent 16-bit data addresses that cross the 16 KByte data page boundaries therefore will use different data page pointers, while the physical locations need not be subsequent within memory. Semiconductor Group 3-10 10Jul97@15:19h The Central Processing Unit (CPU) / C161 4 The Central Processing Unit (CPU) Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and to store the previously calculated results. As the CPU is the main engine of the C161 controller, it is also affected by certain actions of the peripheral subsystem. Since a four stage pipeline is implemented in the C161, up to four instructions can be processed in parallel. Most instructions of the C161 are executed in one machine cycle (ie. 100 ns @ 20 MHz CPU clock) due to this parallelism. This chapter describes how the pipeline works for sequential and branch instructions in general, and which hardware provisions have been made to speed the execution of jump instructions in particular. The general instruction timing is described including standard and exceptional timing. While internal memory accesses are normally performed by the CPU itself, external peripheral or memory accesses are performed by a particular on-chip External Bus Controller (EBC), which is automatically invoked by the CPU whenever a code or data address refers to the external address space. If possible, the CPU continues operating while an external memory access is in progress. If external data are required but are not yet available, or if a new external memory access is requested by the CPU, before a previous access has been completed, the CPU will be held by the EBC until the request can be satisfied. The EBC is described in a dedicated chapter. Figure 4-1 CPU Block Diagram Semiconductor Group 4-1 10Jul97@15:19h The Central Processing Unit (CPU) / C161 The on-chip peripheral units of the C161 work nearly independent of the CPU with a separate clock generator. Data and control information is interchanged between the CPU and these peripherals via Special Function Registers (SFRs). Whenever peripherals need a non-deterministic CPU action, an on-chip Interrupt Controller compares all pending peripheral service requests against each other and prioritizes one of them. If the priority of the current CPU operation is lower than the priority of the selected peripheral request, an interrupt will occur. Basically, there are two types of interrupt processing: * Standard interrupt processing forces the CPU to save the current program status and the return address on the stack before branching to the interrupt vector jump table. * PEC interrupt processing steals just one machine cycle from the current CPU activity to perform a single data transfer via the on-chip Peripheral Event Controller (PEC). System errors detected during program execution (socalled hardware traps) or an external nonmaskable interrupt are also processed as standard interrupts with a very high priority. In contrast to other on-chip peripherals, there is a closer conjunction between the watchdog timer and the CPU. If enabled, the watchdog timer expects to be serviced by the CPU within a programmable period of time, otherwise it will reset the chip. Thus, the watchdog timer is able to prevent the CPU from going totally astray when executing erroneous code. After reset, the watchdog timer starts counting automatically, but it can be disabled via software, if desired. Beside its normal operation there are the following particular CPU states: * Reset state: Any reset (hardware, software, watchdog) forces the CPU into a predefined active state. * IDLE state: The clock signal to the CPU itself is switched off, while the clocks for the on-chip peripherals keep running. * POWER DOWN state: All of the on-chip clocks are switched off. A transition into an active CPU state is forced by an interrupt (if being IDLE) or by a reset (if being in POWER DOWN mode). The IDLE, POWER DOWN and RESET states can be entered by particular C161 system control instructions. A set of Special Function Registers is dedicated to the functions of the CPU core: * * * * * * * * General System Configuration CPU Status Indication and Control Code Access Control Data Paging Control GPRs Access Control System Stack Access Control Multiply and Divide Support ALU Constants Support : SYSCON (RP0H) : PSW : IP, CSP : DPP0, DPP1, DPP2, DPP3 : CP : SP, STKUN, STKOV : MDL, MDH, MDC : ZEROS, ONES Semiconductor Group 4-2 10Jul97@15:19h The Central Processing Unit (CPU) / C161 4.1 Instruction Pipelining The instruction pipeline of the C161 partitiones instruction processing into four stages of which each one has its individual task: 1st ->FETCH: In this stage the instruction selected by the Instruction Pointer (IP) and the Code Segment Pointer (CSP) is fetched from either the internal ROM, internal RAM, or external memory. 2nd ->DECODE: In this stage the instructions are decoded and, if required, the operand addresses are calculated and the respective operands are fetched. For all instructions, which implicitly access the system stack, the SP register is either decremented or incremented, as specified. For branch instructions the Instruction Pointer and the Code Segment Pointer are updated with the desired branch target address (provided that the branch is taken). 3rd ->EXECUTE: In this stage an operation is performed on the previously fetched operands in the ALU. Additionally, the condition flags in the PSW register are updated as specified by the instruction. All explicit writes to the SFR memory space and all auto-increment or auto-decrement writes to GPRs used as indirect address pointers are performed during the execute stage of an instruction, too. 4th ->WRITE BACK: In this stage all external operands and the remaining operands within the internal RAM space are written back. A particularity of the C161 are the so-called injected instructions. These injected instructions are generated internally by the machine to provide the time needed to process instructions, which cannot be processed within one machine cycle. They are automatically injected into the decode stage of the pipeline, and then they pass through the remaining stages like every standard instruction. Program interrupts are performed by means of injected instructions, too. Although these internally injected instructions will not be noticed in reality, they are introduced here to ease the explanation of the pipeline in the following. Sequential Instruction Processing Each single instruction has to pass through each of the four pipeline stages regardless of whether all possible stage operations are really performed or not. Since passing through one pipeline stage takes at least one machine cycle, any isolated instruction takes at least four machine cycles to be completed. Pipelining, however, allows parallel (ie. simultaneous) processing of up to four instructions. Thus, most of the instructions seem to be processed during one machine cycle as soon as the pipeline has been filled once after reset (see figure below). Instruction pipelining increases the average instruction throughput considered over a certain period of time. In the following, any execution time specification of an instruction always refers to the average execution time due to pipelined parallel instruction processing. Semiconductor Group 4-3 10Jul97@15:19h The Central Processing Unit (CPU) / C161 1 Machine Cycle FETCH DECODE EXECUTE WRITEBACK time I1 I2 I1 I3 I2 I1 I4 I3 I2 I1 I5 I4 I3 I2 I6 I5 I4 I3 Figure 4-2 Sequential Instruction Pipelining Standard Branch Instruction Processing Instruction pipelining helps to speed sequential program processing. In the case that a branch is taken, the instruction which has already been fetched providently is mostly not the instruction which must be decoded next. Thus, at least one additional machine cycle is normally required to fetch the branch target instruction. This extra machine cycle is provided by means of an injected instruction (see figure below). 1 Machine Cycle Injection In+2 BRANCH In ... ITARGET (IINJECT) BRANCH In ITARGET+1 ITARGET+2 ITARGET+3 ITARGET (IINJECT) BRANCH ITARGET+1 ITARGET+2 ITARGET (IINJECT) ITARGET+1 ITARGET FETCH DECODE EXECUTE WRITEBACK time BRANCH In ... ... Figure 4-3 Standard Branch Instruction Pipelining If a conditional branch is not taken, there is no deviation from the sequential program flow, and thus no extra time is required. In this case the instruction after the branch instruction will enter the decode stage of the pipeline at the beginning of the next machine cycle after decode of the conditional branch instruction. Semiconductor Group 4-4 10Jul97@15:19h The Central Processing Unit (CPU) / C161 Cache Jump Instruction Processing The C161 incorporates a jump cache to optimize conditional jumps, which are processed repeatedly within a loop. Whenever a jump on cache is taken, the extra time to fetch the branch target instruction can be saved and thus the corresponding cache jump instruction in most cases takes only one machine cycle. This performance is achieved by the following mechanism: Whenever a cache jump instruction passes through the decode stage of the pipeline for the first time (and provided that the jump condition is met), the jump target instruction is fetched as usual, causing a time delay of one machine cycle. In contrast to standard branch instructions, however, the target instruction of a cache jump instruction (JMPA, JMPR, JB, JBC, JNB, JNBS) is additionally stored in the cache after having been fetched. After each repeatedly following execution of the same cache jump instruction, the jump target instruction is not fetched from progam memory but taken from the cache and immediatly injected into the decode stage of the pipeline (see figure below). A time saving jump on cache is always taken after the second and any further occurrence of the same cache jump instruction, unless an instruction which, has the fundamental capability of changing the CSP register contents (JMPS, CALLS, RETS, TRAP, RETI), or any standard interrupt has been processed during the period of time between two following occurrences of the same cache jump instruction. 1 Machine Cycle Injection ITARGET ITARGET+1 ITARGET In+2 Cache Jmp In ... Injection of cached Target Instruction ITARGET+1 ITARGET+2 ITARGET Cache Jmp In ITARGET+1 ITARGET Cache Jmp FETCH DECODE EXECUTE WRITEBACK In+2 Cache Jmp (IINJECT) In ... Cache Jmp (IINJECT) In 1st loop iteration Cache Jmp Repeated loop iteration Figure 4-4 Cache Jump Instruction Pipelining Semiconductor Group 4-5 10Jul97@15:19h The Central Processing Unit (CPU) / C161 Particular Pipeline Effects Since up to four different instructions are processed simultaneously, additional hardware has been spent in the C161 to consider all causal dependencies which may exist on instructions in different pipeline stages without a loss of performance. This extra hardware (ie. for 'forwarding' operand read and write values) resolves most of the possible conflicts (eg. multiple usage of buses) in a time optimized way and thus avoids that the pipeline becomes noticeable for the user in most cases. However, there are some very rare cases, where the circumstance that the C161 is a pipelined machine requires attention by the programmer. In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance. * Context Pointer Updating An instruction, which calculates a physical GPR operand address via the CP register, is mostly not capable of using a new CP value, which is to be updated by an immediately preceding instruction. Thus, to make sure that the new CP value is used, at least one instruction must be inserted between a CP-changing and a subsequent GPR-using instruction, as shown in the following example: In In+1 In+2 : SCXT CP, #0FC00h : .... : MOV R0, #dataX ; select a new context ; must not be an instruction using a GPR ; write to GPR 0 in the new context * Data Page Pointer Updating An instruction, which calculates a physical operand address via a particular DPPn (n=0 to 3) register, is mostly not capable of using a new DPPn register value, which is to be updated by an immediately preceding instruction. Thus, to make sure that the new DPPn register value is used, at least one instruction must be inserted between a DPPn-changing instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode, as shown in the following example: In In+1 In+2 : MOV DPP0, #4 : .... : MOV DPP0:0000H, R1 ; select data page 4 via DPP0 ; must not be an instruction using DPP0 ; move contents of R1 to address location 01'0000 H ; (in data page 4) supposed segmentation is enabled * Explicit Stack Pointer Updating None of the RET, RETI, RETS, RETP or POP instructions is capable of correctly using a new SP register value, which is to be updated by an immediately preceding instruction. Thus, in order to use the new SP register value without erroneously performed stack accesses, at least one instruction must be inserted between an explicitly SP-writing and any subsequent of the just mentioned implicitly SP-using instructions, as shown in the following example: In In+1 In+2 : MOV SP, #0FA40H : .... : POP R0 ; select a new top of stack ; must not be an instruction popping operands ; from the system stack ; pop word value from new top of stack into R0 Note: Conflicts with instructions writing to the stack (PUSH, CALL, SCXT) are solved internally by the CPU logic. Semiconductor Group 4-6 10Jul97@15:19h The Central Processing Unit (CPU) / C161 * External Memory Access Sequences The effect described here will only become noticeable, when watching the external memory access sequences on the external bus (eg. by means of a Logic Analyzer). Different pipeline stages can simultaneously put a request on the External Bus Controller (EBC). The sequence of instructions processed by the CPU may diverge from the sequence of the corresponding external memory accesses performed by the EBC, due to the predefined priority of external memory accesses: 1st Write Data 2nd Fetch Code 3rd Read Data. * Controlling Interrupts Software modifications (implicit or explicit) of the PSW are done in the execute phase of the respective instructions. In order to maintain fast interrupt responses, however, the current interrupt prioritization round does not consider these changes, ie. an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or after the following instructions. Timecritical instruction sequences therefore should not begin directly after the instruction disabling interrupts, as shown in the following example: INT_OFF: BCLR IEN IN-1 CRIT_1ST: IN ... CRIT_LAST: IN+x INT_ON: BSET IEN ; globally disable interrupts ; non-critical instruction ; begin of uninterruptable critical sequence ; end of uninterruptable critical sequence ; globally re-enable interrupts Note: The described delay of 1 instruction also applies for enabling the interrupts system ie. no interrupt requests are acknowledged until the instruction following the enabling instruction. * Initialization of Port Pins Modifications of the direction of port pins (input or output) become effective only after the instruction following the modifying instruction. As bit instructions (BSET, BCLR) use internal read-modify-write sequences accessing the whole port, instructions modifying the port direction should be followed by an instruction that does not access the same port (see example below). WRONG: BSET DP3.13 BSET P3.5 BSET DP3.13 NOP BSET P3.5 ; change direction of P3.13 to output ; P3.13 is still input, the rd-mod-wr reads pin P3.13 ; change direction of P3.13 to output ; any instruction not accessing port 3 ; P3.13 is now output, ; the rd-mod-wr reads the P3.13 output latch RIGHT: Semiconductor Group 4-7 10Jul97@15:19h The Central Processing Unit (CPU) / C161 * Changing the System Configuration The instruction following an instruction that changes the system configuration via register SYSCON (eg. the mapping of the internal ROM, segmentation, stack size) cannot use the new resources (eg. ROM or stack). In these cases an instruction that does not access these resources should be inserted. Code accesses to the new ROM area are only possible after an absolute branch to this area. Note: As a rule, instructions that change ROM mapping should be executed from internal RAM or external memory. * BUSCON/ADDRSEL The instruction following an instruction that changes the properties of an external address area cannot access operands within the new area. In these cases an instruction that does not access this address area should be inserted. Code accesses to the new address area should be made after an absolute branch to this area. Note: As a rule, instructions that change external bus properties should not be executed from the respective external memory area. * Timing Instruction pipelining reduces the average instruction processing time in a wide scale (from four to one machine cycles, mostly). However, there are some rare cases, where a particular pipeline situation causes the processing time for a single instruction to be extended either by a half or by one machine cycle. Although this additional time represents only a tiny part of the total program execution time, it might be of interest to avoid these pipeline-caused time delays in time critical program modules. Besides a general execution time description, the following section provides some hints on how to optimize time-critical program parts with regard to such pipeline-caused timing particularities. Semiconductor Group 4-8 10Jul97@15:19h The Central Processing Unit (CPU) / C161 4.2 Bit-Handling and Bit-Protection The C161 provides several mechanisms to manipulate bits. These mechanisms either manipulate software flags within the internal RAM, control on-chip peripherals via control bits in their respective SFRs or control IO functions via port pins. The instructions BSET, BCLR, BAND, BOR, BXOR, BMOV, BMOVN explicitly set or clear specific bits. The instructions BFLDL and BFLDH allow to manipulate up to 8 bits of a specific byte at one time. The instructions JBC and JNBS implicitly clear or set the specified bit when the jump is taken. The instructions JB and JNB (also conditional jump instructions that refer to flags) evaluate the specified bit to determine if the jump is to be taken. Note: Bit operations on undefined bit locations will always read a bit value of `0', while the write access will not effect the respective bit location. All instructions that manipulate single bits or bit groups internally use a read-modify-write sequence that accesses the whole word, which contains the specified bit(s). This method has several consequences: * Bits can only be modified within the internal address areas, ie. internal RAM and SFRs. External locations cannot be used with bit instructions. The upper 256 bytes of the SFR area, the ESFR area and the internal RAM are bit-addressable (see chapter "Memory Organization"), ie. those register bits located within the respective sections can be directly manipulated using bit instructions. The other SFRs must be accessed byte/word wise. Note: All GPRs are bit-addressable independent of the allocation of the register bank via the context pointer CP. Even GPRs which are allocated to not bit-addressable RAM locations provide this feature. * The read-modify-write approach may be critical with hardware-effected bits. In these cases the hardware may change specific bits while the read-modify-write operation is in progress, where the writeback would overwrite the new bit value generated by the hardware. The solution is either the implemented hardware protection (see below) or realized through special programming (see "Particular Pipeline Effects"). Protected bits are not changed during the read-modify-write sequence, ie. when hardware sets eg. an interrupt request flag between the read and the write of the read-modify-write sequence. The hardware protection logic guarantees that only the intended bit(s) is/are effected by the write-back operation. Note: If a conflict occurs between a bit manipulation generated by hardware and an intended software access the software access has priority and determines the final value of the respective bit. A summary of the protected bits implemented in the C161 can be found at the end of chapter "Architectural Overview". Semiconductor Group 4-9 10Jul97@15:19h The Central Processing Unit (CPU) / C161 4.3 Instruction State Times Basically, the time to execute an instruction depends on where the instruction is fetched from, and where possible operands are read from or written to. The fastest processing mode of the C161 is to execute a program fetched from the internal ROM. In that case most of the instructions can be processed within just one machine cycle, which is also the general minimum execution time. All external memory accesses are performed by the C161's on-chip External Bus Controller (EBC), which works in parallel with the CPU. This section summarizes the execution times in a very condensed way. A detailled description of the execution times for the various instructions and the specific exceptions can be found in the "C16x Family Instruction Set Manual". The table below shows the minimum execution times required to process a C161 instruction fetched from the internal ROM, the internal RAM or from external memory. These execution times apply to most of the C161 instructions - except some of the branches, the multiplication, the division and a special move instruction. In case of internal ROM program execution there is no execution time dependency on the instruction length except for some special branch situations. The numbers in the table are in units of [ns], refer to a CPU clock of 20 MHz and assume no waitstates. Minimum Execution Times Instruction Fetch Memory Area Internal ROM Internal RAM 16-bit Demux Bus 16-bit Mux Bus 8-bit Demux Bus 8-bit Mux Bus Word Instruction 100 300 100 150 200 300 Doubleword Instruction 100 400 200 300 400 600 Word Operand Access Read from 100 0/50 100 150 200 300 Write to --0 100 150 200 300 Execution from the internal RAM provides flexibility in terms of loadable and modifyable code on the account of execution time. Execution from external memory strongly depends on the selected bus mode and the programming of the bus cycles (waitstates). The operand and instruction accesses listed below can extend the execution time of an instruction: * Internal ROM operand reads (same for byte and word operand reads) * Internal RAM operand reads via indirect addressing modes * Internal SFR operand reads immediately after writing * External operand reads * External operand writes * Jumps to non-aligned double word instructions in the internal ROM space * Testing Branch Conditions immediately after PSW writes Semiconductor Group 4-10 10Jul97@15:19h The Central Processing Unit (CPU) / C161 4.4 CPU Special Function Registers The core CPU requires a set of Special Function Registers (SFRs) to maintain the system state information, to supply the ALU with register-addressable constants and to control system and bus configuration, multiply and divide ALU operations, code memory segmentation, data memory paging, and accesses to the General Purpose Registers and the System Stack. The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR. Since all SFRs can simply be controlled by means of any instruction, which is capable of addressing the SFR memory space, a lot of flexibility has been gained, without the need to create a set of system-specific instructions. Note, however, that there are user access restrictions for some of the CPU core SFRs to ensure proper processor operations. The instruction pointer IP and code segment pointer CSP cannot be accessed directly at all. They can only be changed indirectly via branch instructions. The PSW, SP, and MDC registers can be modified not only explicitly by the programmer, but also implicitly by the CPU during normal instruction processing. Note that any explicit write request (via software) to an SFR supersedes a simultaneous modification by hardware of the same register. Note: Any write operation to a single byte of an SFR clears the non-addressed complementary byte within the specified SFR. Non-implemented (reserved) SFR bits cannot be modified, and will always supply a read value of '0'. The System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT0 pins during reset (see hardware effectable bits). Semiconductor Group 4-11 10Jul97@15:19h The Central Processing Unit (CPU) / C161 SYSCON (FF12H / 89H) 15 14 STKSZ rw 13 12 11 10 9 8 ROM SGT ROM BYT S1 DIS EN DIS rw rw rw rw SFR 7 WR CFG rw 6 5 4 - Reset Value: 0XX0H 3 2 1 VISI 0 XPER- XPEN BLE SHARE rw rw rw Bit Function XPER-SHARE XBUS Peripheral Share Mode Control `0': External accesses to XBUS peripherals are disabled `1': XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control `0': Accesses to XBUS peripherals are done internally `1': XBUS peripheral accesses are made visible on the external pins XBUS Peripheral Enable Bit `0': Accesses to the on-chip X-Peripherals and their functions are disabled `1': The on-chip X-Peripherals are enabled and can be accessed Note: This bit is valid only for derivatives that contain X-Peripherals. Write Configuration Control (Set according to pin P0H.0 during reset) `0': Pins WR and BHE retain their normal function `1': Pin WR acts as WRL, pin BHE acts as WRH Disable/Enable Control for Pin BHE (Set according to data bus width) `0': Pin BHE enabled `1': Pin BHE disabled, pin may be used for general purpose IO Internal ROM Enable (Set according to pin EA during reset) `0': Internal ROM disabled: accesses to the ROM area use the external bus `1': Internal ROM enabled Segmentation Disable/Enable Control `0': Segmentation enabled (CSP is saved/restored during interrupt entry/exit) `1': Segmentation disabled (Only IP is saved/restored) Internal ROM Mapping `0': Internal ROM area mapped to segment 0 (00'0000H...00'7FFFH) `1': Internal ROM area mapped to segment 1 (01'0000H...01'7FFFH) System Stack Size Selects the size of the system stack (in the internal RAM) from 32 to 1024 words XPEN WRCFG BYTDIS ROMEN SGTDIS ROMS1 STKSZ Note: Register SYSCON cannot be changed after execution of the EINIT instruction. The function of bits XPER-SHARE, VISIBLE, WRCFG, BYTDIS, ROMEN and ROMS1 is described in more detail in chapter "The External Bus Controller". Semiconductor Group 4-12 10Jul97@15:19h The Central Processing Unit (CPU) / C161 Segmentation Disable/Enable Control (SGTDIS) Bit SGTDIS allows to select either the segmented or non-segmented memory mode. In non-segmented memory mode (SGTDIS='1') it is assumed that the code address space is restricted to 64 KBytes (segment 0) and thus 16 bits are sufficient to represent all code addresses. For implicit stack operations (CALL or RET) the CSP register is totally ignored and only the IP is saved to and restored from the stack. In segmented memory mode (SGTDIS='0') it is assumed that the whole address space is available for instructions. For implicit stack operations (CALL or RET) the CSP register and the IP are saved to and restored from the stack. After reset the segmented memory mode is selected. Note: Bit SGTDIS controls if the CSP register is pushed onto the system stack in addition to the IP register before an interrupt service routine is entered, and it is repopped when the interrupt service routine is left again. System Stack Size (STKSZ) This bitfield defines the size of the physical system stack, which is located in the internal RAM of the C161. An area of 32...512 words (256 words in the C161V and C161K) or all of the internal RAM may be dedicated to the system stack. A so-called "circular stack" mechanism allows to use a bigger virtual stack than this dedicated RAM area. These techniques as well as the encoding of bitfield STKSZ are described in more detail in chapter "System Programming". Semiconductor Group 4-13 10Jul97@15:19h The Central Processing Unit (CPU) / C161 The Processor Status Word PSW This bit-addressable register reflects the current state of the microcontroller. Two groups of bits represent the current ALU status, and the current CPU interrupt status. A separate bit (USR0) within register PSW is provided as a general purpose user flag. PSW (FF10H / 88H) 15 14 13 12 11 IEN rw 10 9 8 - SFR 7 6 USR0 rw 5 MUL IP rw 4 E rw Reset Value: 0000H 3 Z rw 2 V rw 1 C rw 0 N rw ILVL rw Bit N C V Z E MULIP Function Negative Result Set, when the result of an ALU operation is negative. Carry Flag Set, when the result of an ALU operation produces a carry bit. Overflow Result Set, when the result of an ALU operation produces an overflow. Zero Flag Set, when the result of an ALU operation is zero. End of Table Flag Set, when the source operand of an instruction is 8000H or 80H. Multiplication/Division In Progress `0': There is no multiplication/division in progress. `1': A multiplication/division has been interrupted. User General Purpose Flag May be used by the application software. Interrupt Control Fields Define the response to interrupt requests. (Described in section "Interrupt and Trap Functions") USR0 ILVL, IEN ALU Status (N, C, V, Z, E, MULIP) The condition flags (N, C, V, Z, E) within the PSW indicate the ALU status due to the last recently performed ALU operation. They are set by most of the instructions due to specific rules, which depend on the ALU or data movement operation performed by an instruction. After execution of an instruction which explicitly updates the PSW register, the condition flags cannot be interpreted as described in the following, because any explicit write to the PSW register supersedes the condition flag values, which are implicitly generated by the CPU. Explicitly reading the PSW register supplies a read value which represents the state of the PSW register after execution of the immediately preceding instruction. Note: After reset, all of the ALU status bits are cleared. Semiconductor Group 4-14 10Jul97@15:19h The Central Processing Unit (CPU) / C161 * N-Flag: For most of the ALU operations, the N-flag is set to '1', if the most significant bit of the result contains a '1', otherwise it is cleared. In the case of integer operations the N-flag can be interpreted as the sign bit of the result (negative: N='1', positive: N='0'). Negative numbers are always represented as the 2's complement of the corresponding positive number. The range of signed numbers extends from '-8000H' to '+7FFFH' for the word data type, or from '-80H' to '+7FH' for the byte data type.For Boolean bit operations with only one operand the N-flag represents the previous state of the specified bit. For Boolean bit operations with two operands the N-flag represents the logical XORing of the two specified bits. * C-Flag: After an addition the C-flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated. After a subtraction or a comparison the C-flag indicates a borrow, which represents the logical negation of a carry for the addition. This means that the C-flag is set to '1', if no carry from the most significant bit of the specified word or byte data type has been generated during a subtraction, which is performed internally by the ALU as a 2's complement addition, and the C-flag is cleared when this complement addition caused a carry. The C-flag is always cleared for logical, multiply and divide ALU operations, because these operations cannot cause a carry anyhow. For shift and rotate operations the C-flag represents the value of the bit shifted out last. If a shift count of zero is specified, the C-flag will be cleared. The C-flag is also cleared for a prioritize ALU operation, because a '1' is never shifted out of the MSB during the normalization of an operand. For Boolean bit operations with only one operand the C-flag is always cleared. For Boolean bit operations with two operands the C-flag represents the logical ANDing of the two specified bits. * V-Flag: For addition, subtraction and 2's complementation the V-flag is always set to '1', if the result overflows the maximum range of signed numbers, which are representable by either 16 bits for word operations ('-8000H' to '+7FFFH'), or by 8 bits for byte operations ('-80H' to '+7FH'), otherwise the V-flag is cleared. Note that the result of an integer addition, integer subtraction, or 2's complement is not valid, if the V-flag indicates an arithmetic overflow. For multiplication and division the V-flag is set to '1', if the result cannot be represented in a word data type, otherwise it is cleared. Note that a division by zero will always cause an overflow. In contrast to the result of a division, the result of a multiplication is valid regardless of whether the Vflag is set to '1' or not. Since logical ALU operations cannot produce an invalid result, the V-flag is cleared by these operations. The V-flag is also used as 'Sticky Bit' for rotate right and shift right operations. With only using the C-flag, a rounding error caused by a shift right operation can be estimated up to a quantity of one half of the LSB of the result. In conjunction with the V-flag, the C-flag allows evaluating the rounding error with a finer resolution (see table below). For Boolean bit operations with only one operand the V-flag is always cleared. For Boolean bit operations with two operands the V-flag represents the logical ORing of the two specified bits. Semiconductor Group 4-15 10Jul97@15:19h The Central Processing Unit (CPU) / C161 Shift Right Rounding Error Evaluation C-Flag 0 0 1 1 V-Flag 0 1 0 1 Rounding Error Quantity 0< No rounding error Rounding error Rounding error Rounding error < = > 1 1 /2 LSB /2 LSB 1/ LSB 2 * Z-Flag: The Z-flag is normally set to '1', if the result of an ALU operation equals zero, otherwise it is cleared. For the addition and subtraction with carry the Z-flag is only set to '1', if the Z-flag already contains a '1' and the result of the current ALU operation additionally equals zero. This mechanism is provided for the support of multiple precision calculations. For Boolean bit operations with only one operand the Z-flag represents the logical negation of the previous state of the specified bit. For Boolean bit operations with two operands the Z-flag represents the logical NORing of the two specified bits. For the prioritize ALU operation the Z-flag indicates, if the second operand was zero or not. * E-Flag: The E-flag can be altered by instructions, which perform ALU or data movement operations. The E-flag is cleared by those instructions which cannot be reasonably used for table search operations. In all other cases the E-flag is set depending on the value of the source operand to signify whether the end of a search table is reached or not. If the value of the source operand of an instruction equals the lowest negative number, which is representable by the data format of the corresponding instruction ('8000 H' for the word data type, or '80H' for the byte data type), the E-flag is set to '1', otherwise it is cleared. * MULIP-Flag: The MULIP-flag will be set to '1' by hardware upon the entrance into an interrupt service routine, when a multiply or divide ALU operation was interrupted before completion. Depending on the state of the MULIP bit, the hardware decides whether a multiplication or division must be continued or not after the end of an interrupt service. The MULIP bit is overwritten with the contents of the stacked MULIP-flag when the return-from-interrupt-instruction (RETI) is executed. This normally means that the MULIP-flag is cleared again after that. Note: The MULIP flag is a part of the task environment! When the interrupting service routine does not return to the interrupted multiply/divide instruction (ie. in case of a task scheduler that switches between independent tasks), the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered. Semiconductor Group 4-16 10Jul97@15:19h The Central Processing Unit (CPU) / C161 CPU Interrupt Status (IEN, ILVL) The Interrupt Enable bit allows to globally enable (IEN='1') or disable (IEN='0') interrupts. The fourbit Interrupt Level field (ILVL) specifies the priority of the current CPU activity. The interrupt level is updated by hardware upon entry into an interrupt service routine, but it can also be modified via software to prevent other interrupts from being acknowledged. In case an interrupt level '15' has been assigned to the CPU, it has the highest possible priority, and thus the current CPU operation cannot be interrupted except by hardware traps or external non-maskable interrupts. For details please refer to chapter "Interrupt and Trap Functions". After reset all interrupts are globally disabled, and the lowest priority (ILVL=0) is assigned to the initial CPU activity. The Instruction Pointer IP This register determines the 16-bit intra-segment address of the currently fetched instruction within the code segment selected by the CSP register. The IP register is not mapped into the C161's address space, and thus it is not directly accessable by the programmer. The IP can, however, be modified indirectly via the stack by means of a return instruction. The IP register is implicitly updated by the CPU for branch instructions and after instruction fetch operations. IP (---- / --) 15 14 13 12 11 10 9 8 ip (r)(w) --7 6 5 4 Reset Value: 0000H 3 2 1 0 Bit ip Function Specifies the intra segment offset, from where the current instruction is to be fetched. IP refers to the current segment Semiconductor Group 4-17 10Jul97@15:19h The Central Processing Unit (CPU) / C161 The Code Segment Pointer CSP This non-bit addressable register selects the code segment being used at run-time to access instructions. The lower 8 bits of register CSP select one of up to 256 segments of 64 Kbytes each, while the upper 8 bits are reserved for future use. CSP (FE08H / 04H) 15 14 13 12 11 10 9 8 - SFR 7 6 5 4 Reset Value: 0000H 3 2 1 0 SEGNR r Bit SEGNR Function Segment Number Specifies the code segment, from where the current instruction is to be fetched. SEGNR is ignored, when segmentation is disabled. Code memory addresses are generated by directly extending the 16-bit contents of the IP register by the contents of the CSP register as shown in the figure below. In case of the segmented memory mode the selected number of segment address bits (7...0, 3...0 or 1...0) of register CSP is output on the segment address pins A23/A19/A17...A16 of Port 4 for all external code accesses. For non-segmented memory mode or Single Chip Mode the content of this register is not significant, because all code acccesses are automatically restricted to segment 0. Note: The CSP register can only be read but not written by data operations. It is, however, modified either directly by means of the JMPS and CALLS instructions, or indirectly via the stack by means of the RETS and RETI instructions. Upon the acceptance of an interrupt or the execution of a software TRAP instruction, the CSP register is automatically set to zero. Semiconductor Group 4-18 10Jul97@15:19h The Central Processing Unit (CPU) / C161 Figure 4-5 Addressing via the Code Segment Pointer Note: When segmentation is disabled, the IP value is used directly as the 16-bit address. Semiconductor Group 4-19 10Jul97@15:19h The Central Processing Unit (CPU) / C161 The Data Page Pointers DPP0, DPP1, DPP2, DPP3 These four non-bit addressable registers select up to four different data pages being active simultaneously at run-time. The lower 10 bits of each DPP register select one of the 1024 possible 16-Kbyte data pages while the upper 6 bits are reserved for future use. The DPP registers allow to access the entire memory space in pages of 16 Kbytes each. The DPP registers are implicitly used, whenever data accesses to any memory location are made via indirect or direct long 16-bit addressing modes (except for override accesses via EXTended instructions and PEC data transfers). After reset, the Data Page Pointers are initialized in a way that all indirect or direct long 16-bit addresses result in identical 18-bit addresses. This allows to access data pages 3...0 within segment 0 as shown in the figure below. If the user does not want to use any data paging, no further action is required. DPP0 (FE00H / 00H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: 0000H 3 2 1 0 DPP0PN rw DPP1 (FE02H / 01H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: 0001H 3 2 1 0 DPP1PN rw DPP2 (FE04H / 02H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: 0002H 3 2 1 0 DPP2PN rw DPP3 (FE06H / 03H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: 0003H 3 2 1 0 DPP3PN rw Bit DPPxPN Function Data Page Number of DPPx Specifies the data page selected via DPPx. Only the least significant two bits of DPPx are significant, when segmentation is disabled. Semiconductor Group 4-20 10Jul97@15:19h The Central Processing Unit (CPU) / C161 Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16-bit address with the contents of the DDP register selected by the upper two bits of the 16-bit address. The content of the selected DPP register specifies one of the 1024 possible data pages. This data page base address together with the 14-bit page offset forms the physical 24/20/18-bit address. In case of non-segmented memory mode, only the two least significant bits of the implicitly selected DPP register are used to generate the physical address. Thus, extreme care should be taken when changing the content of a DPP register, if a non-segmented memory model is selected, because otherwise unexpected results could occur. In case of the segmented memory mode the selected number of segment address bits (9...2, 5...2 or 3...2) of the respective DPP register is output on the segment address pins A23/A19/A17...A16 of Port 4 for all external data accesses. A DPP register can be updated via any instruction, which is capable of modifying an SFR. Note: Due to the internal instruction pipeline, a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the instruction updating the DPP register. After reset or with segmentation disabled the DPP registers select data pages 3...0. All of the internal memory is accessible in these cases. Figure 4-6 Addressing via the Data Page Pointers Semiconductor Group 4-21 10Jul97@15:19h The Central Processing Unit (CPU) / C161 The Context Pointer CP This non-bit addressable register is used to select the current register context. This means that the CP register value determines the address of the first General Purpose Register (GPR) within the current register bank of up to 16 wordwide and/or bytewide GPRs. CP (FE10H / 08H) 15 1 r 14 1 r 13 1 r 12 1 r 11 10 9 8 SFR 7 6 cp rw 5 4 Reset Value: FC00H 3 2 1 0 0 r Bit cp Function Modifiable portion of register CP Specifies the (word) base address of the current register bank. When writing a value to register CP with bits CP.11...CP.9 = `000', bits CP.11...CP.10 are set to `11' by hardware, in all other cases all bits of bit field "cp" receive the written value. Note: It is the user's responsibility that the physical GPR address specified via CP register plus short GPR address must always be an internal RAM location. If this condition is not met, unexpected results may occur. * Do not set CP below 00'F600H (C161O) or below 00'FA00H (C161V, C161K) * Do not set CP above 00'FDFEH * Be careful using the upper GPRs with CP above 00'FDE0 H The CP register can be updated via any instruction which is capable of modifying an SFR. Note: Due to the internal instruction pipeline, a new CP value is not yet usable for GPR address calculations of the instruction immediately following the instruction updating the CP register. The Switch Context instruction (SCXT) allows to save the content of register CP on the stack and updating it with a new value in just one machine cycle. Semiconductor Group 4-22 10Jul97@15:19h The Central Processing Unit (CPU) / C161 Figure 4-7 Register Bank Selection via Register CP Several addressing modes use register CP implicitly for address calculations. The addressing modes mentioned below are described in chapter "Instruction Set Summary". Short 4-Bit GPR Addresses (mnemonic: Rw or Rb) specify an address relative to the memory location specified by the contents of the CP register, ie. the base of the current register bank. Depending on whether a relative word (Rw) or byte (Rb) GPR address is specified, the short 4-bit GPR address is either multiplied by two or not before it is added to the content of register CP (see figure below). Thus, both byte and word GPR accesses are possible in this way. GPRs used as indirect address pointers are always accessed wordwise. For some instructions only the first four GPRs can be used as indirect address pointers. These GPRs are specified via short 2bit GPR addresses. The respective physical address calculation is identical to that for the short 4bit GPR addresses. Short 8-Bit Register Addresses (mnemonic: reg or bitoff) within a range from F0H to FFH interpret the four least significant bits as short 4-bit GPR address, while the four most significant bits are ignored. The respective physical GPR address calculation is identical to that for the short 4-bit GPR addresses. For single bit accesses on a GPR, the GPR's word address is calculated as just described, but the position of the bit within the word is specified by a separate additional 4-bit value. Semiconductor Group 4-23 10Jul97@15:19h The Central Processing Unit (CPU) / C161 Figure 4-8 Implicit CP Use by Short GPR Addressing Modes The Stack Pointer SP This non-bit addressable register is used to point to the top of the internal system stack (TOS). The SP register is pre-decremented whenever data is to be pushed onto the stack, and it is postincremented whenever data is to be popped from the stack. Thus, the system stack grows from higher toward lower memory locations. Since the least significant bit of register SP is tied to '0' and bits 15 through 12 are tied to '1' by hardware, the SP register can only contain values from F000 H to FFFEH. This allows to access a physical stack within the internal RAM of the C161. A virtual stack (usually bigger) can be realized via software. This mechanism is supported by registers STKOV and STKUN (see respective descriptions below). The SP register can be updated via any instruction, which is capable of modifying an SFR. Note: Due to the internal instruction pipeline, a POP or RETURN instruction must not immediately follow an instruction updating the SP register. SP (FE12H / 09H) 15 1 r 14 1 r 13 1 r 12 1 r 11 10 9 8 SFR 7 6 sp rw 5 4 Reset Value: FC00H 3 2 1 0 0 r Bit sp Function Modifiable portion of register SP Specifies the top of the internal system stack. Semiconductor Group 4-24 10Jul97@15:19h The Central Processing Unit (CPU) / C161 The Stack Overflow Pointer STKOV This non-bit addressable register is compared against the SP register after each operation, which pushes data onto the system stack (eg. PUSH and CALL instructions or interrupts) and after each subtraction from the SP register. If the content of the SP register is less than the content of the STKOV register, a stack overflow hardware trap will occur. Since the least significant bit of register STKOV is tied to '0' and bits 15 through 12 are tied to '1' by hardware, the STKOV register can only contain values from F000H to FFFEH. STKOV (FE14H / 0AH) 15 1 r 14 1 r 13 1 r 12 1 r 11 10 9 8 SFR 7 6 stkov rw 5 4 Reset Value: FA00H 3 2 1 0 0 r Bit stkov Function Modifiable portion of register STKOV Specifies the lower limit of the internal system stack. The Stack Overflow Trap (entered when (SP) < (STKOV)) may be used in two different ways: * Fatal error indication treats the stack overflow as a system error through the associated trap service routine. Under these circumstances data in the bottom of the stack may have been overwritten by the status information stacked upon servicing the stack overflow trap. * Automatic system stack flushing allows to use the system stack as a 'Stack Cache' for a bigger external user stack. In this case register STKOV should be initialized to a value, which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size. This considers the worst case that will occur, when a stack overflow condition is detected just during entry into an interrupt service routine. Then, six additional stack word locations are required to push IP, PSW, and CSP for both the interrupt service routine and the hardware trap service routine. More details about the stack overflow trap service routine and virtual stack management are given in chapter "System Programming". Semiconductor Group 4-25 10Jul97@15:19h The Central Processing Unit (CPU) / C161 The Stack Underflow Pointer STKUN This non-bit addressable register is compared against the SP register after each operation, which pops data from the system stack (eg. POP and RET instructions) and after each addition to the SP register. If the content of the SP register is greater than the the content of the STKUN register, a stack underflow hardware trap will occur. Since the least significant bit of register STKUN is tied to '0' and bits 15 through 12 are tied to '1' by hardware, the STKUN register can only contain values from F000H to FFFEH. STKUN (FE16H / 0BH) 15 1 r 14 1 r 13 1 r 12 1 r 11 10 9 8 SFR 7 6 stkun rw 5 4 Reset Value: FC00H 3 2 1 0 0 r Bit stkun Function Modifiable portion of register STKUN Specifies the upper limit of the internal system stack. The Stack Underflow Trap (entered when (SP) > (STKUN)) may be used in two different ways: * Fatal error indication treats the stack underflow as a system error through the associated trap service routine. * Automatic system stack refilling allows to use the system stack as a 'Stack Cache' for a bigger external user stack. In this case register STKUN should be initialized to a value, which represents the desired highest Bottom of Stack address. More details about the stack underflow trap service routine and virtual stack management are given in chapter "System Programming". Scope of Stack Limit Control The stack limit control realized by the register pair STKOV and STKUN detects cases where the stack pointer SP is moved outside the defined stack area either by ADD or SUB instructions or by PUSH or POP operations (explicit or implicit, ie. CALL or RET instructions). This control mechanism is not triggered, ie. no stack trap is generated, when * the stack pointer SP is directly updated via MOV instructions * the limits of the stack area (STKOV, STKUN) are changed, so that SP is outside of the new limits. Semiconductor Group 4-26 10Jul97@15:19h The Central Processing Unit (CPU) / C161 The Multiply/Divide High Register MDH This register is a part of the 32-bit multiply/divide register, which is implicitly used by the CPU, when it performs a multiplication or a division. After a multiplication, this non-bit addressable register represents the high order 16 bits of the 32-bit result. For long divisions, the MDH register must be loaded with the high order 16 bits of the 32-bit dividend before the division is started. After any division, register MDH represents the 16-bit remainder. MDH (FE0CH / 06H) 15 14 13 12 11 10 9 8 mdh rw SFR 7 6 5 4 Reset Value: 0000H 3 2 1 0 Bit mdh Function Specifies the high order 16 bits of the 32-bit multiply and divide register MD. Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Control register (MDC) is set to '1'. When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine, register MDH must be saved along with registers MDL and MDC to avoid erroneous results. A detailed description of how to use the MDH register for programming multiply and divide algorithms can be found in chapter "System Programming". The Multiply/Divide Low Register MDL This register is a part of the 32-bit multiply/divide register, which is implicitly used by the CPU, when it performs a multiplication or a division. After a multiplication, this non-bit addressable register represents the low order 16 bits of the 32-bit result. For long divisions, the MDL register must be loaded with the low order 16 bits of the 32-bit dividend before the division is started. After any division, register MDL represents the 16-bit quotient. MDL (FE0EH / 07H) 15 14 13 12 11 10 9 8 mdl rw SFR 7 6 5 4 Reset Value: 0000H 3 2 1 0 Bit mdl Function Specifies the low order 16 bits of the 32-bit multiply and divide register MD. Semiconductor Group 4-27 10Jul97@15:19h The Central Processing Unit (CPU) / C161 Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Control register (MDC) is set to '1'. The MDRIU flag is cleared, whenever the MDL register is read via software. When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine, register MDL must be saved along with registers MDH and MDC to avoid erroneous results. A detailed description of how to use the MDL register for programming multiply and divide algorithms can be found in chapter "System Programming". The Multiply/Divide Control Register MDC This bit addressable 16-bit register is implicitly used by the CPU, when it performs a multiplication or a division. It is used to store the required control information for the corresponding multiply or divide operation. Register MDC is updated by hardware during each single cycle of a multiply or divide instruction. MDC (FF0EH / 87H) 15 14 13 12 11 10 9 8 - SFR 7 !! r(w) 6 !! r(w) 5 !! r(w) 4 MDR IU r(w) Reset Value: 0000H 3 !! r(w) 2 !! r(w) 1 !! r(w) 0 !! r(w) Bit MDRIU Function Multiply/Divide Register In Use `0': Cleared, when register MDL is read via software. `1': Set when register MDL or MDH is written via software, or when a multiply or divide instruction is executed. Internal Machine Status The multiply/divide unit uses these bits to control internal operations. Never modify these bits without saving and restoring register MDC. !! When a division or multiplication was interrupted before its completion and the multiply/divide unit is required, the MDC register must first be saved along with registers MDH and MDL (to be able to restart the interrupted operation later), and then it must be cleared prepare it for the new calculation. After completion of the new division or multiplication, the state of the interrupted multiply or divide operation must be restored. The MDRIU flag is the only portion of the MDC register which might be of interest for the user. The remaining portions of the MDC register are reserved for dedicated use by the hardware, and should never be modified by the user in another way than described above. Otherwise, a correct continuation of an interrupted multiply or divide operation cannot be guaranteed. A detailed description of how to use the MDC register for programming multiply and divide algorithms can be found in chapter "System Programming". Semiconductor Group 4-28 10Jul97@15:19h The Central Processing Unit (CPU) / C161 The Constant Zeros Register ZEROS All bits of this bit-addressable register are fixed to '0' by hardware. This register can be read only. Register ZEROS can be used as a register-addressable constant of all zeros, ie. for bit manipulation or mask generation. It can be accessed via any instruction, which is capable of addressing an SFR. ZEROS (FF1CH / 8EH) 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 10 0 r 9 0 r 8 0 r SFR 7 0 r 6 0 r 5 0 r 4 0 r Reset Value: 0000H 3 0 r 2 0 r 1 0 r 0 0 r The Constant Ones Register ONES All bits of this bit-addressable register are fixed to '1' by hardware. This register can be read only. Register ONES can be used as a register-addressable constant of all ones, ie. for bit manipulation or mask generation. It can be accessed via any instruction, which is capable of addressing an SFR. ONES (FF1EH / 8FH) 15 1 r 14 1 r 13 1 r 12 1 r 11 1 r 10 1 r 9 1 r 8 1 r SFR 7 1 r 6 1 r 5 1 r 4 1 r Reset Value: FFFFH 3 1 r 2 1 r 1 1 r 0 1 r Semiconductor Group 4-29 10Jul97@15:19h Interrupt and Trap Functions / C161 5 Interrupt and Trap Functions The architecture of the C161 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. These mechanisms include: Normal Interrupt Processing The CPU temporarily suspends the current program execution and branches to an interrupt service routine in order to service an interrupt requesting device. The current program status (IP, PSW, in segmentation mode also CSP) is saved on the internal system stack. A prioritization scheme with 16 priority levels allows the user to specify the order in which multiple interrupt requests are to be handled. Interrupt Processing via the Peripheral Event Controller (PEC) A faster alternative to normal software controlled interrupt processing is servicing an interrupt requesting device with the C161's integrated Peripheral Event Controller (PEC). Triggered by an interrupt request, the PEC performs a single word or byte data transfer between any two locations in segment 0 (data pages 0 through 3) through one of eight programmable PEC Service Channels. During a PEC transfer the normal program execution of the CPU is halted for just 1 instruction cycle. No internal program status information needs to be saved. The same prioritization scheme is used for PEC service as for normal interrupt processing. PEC transfers share the 2 highest priority levels. Trap Functions Trap functions are activated in response to special conditions that occur during the execution of instructions. A trap can also be caused externally by the Non-Maskable Interrupt pin NMI. Several hardware trap functions are provided for handling erroneous conditions and exceptions that arise during the execution of an instruction. Hardware traps always have highest priority and cause immediate system reaction. The software trap function is invoked by the TRAP instruction, which generates a software interrupt for a specified interrupt vector. For all types of traps the current program status is saved on the system stack. External Interrupt Processing Although the C161 does not provide dedicated interrupt pins, it allows to connect external interrupt sources and provides several mechanisms to react on external events, including standard inputs, non-maskable interrupts and fast external interrupts. These interrupt functions are alternate port functions, except for the non-maskable interrupt and the reset input. Semiconductor Group 5-1 10Jul97@15:19h Interrupt and Trap Functions / C161 5.1 Interrupt System Structure The C161 provides 20 separate interrupt nodes (14 on the C161V) that may be assigned to 16 priority levels. In order to support modular and consistent software design techniques, each source of an interrupt or PEC request is supplied with a separate interrupt control register and interrupt vector. The control register contains the interrupt request flag, the interrupt enable bit, and the interrupt priority of the associated source. Each source request is activated by one specific event, depending on the selected operating mode of the respective device. The only exceptions are the two serial channels of the C161, where an error interrupt request can be generated by different kinds of error. However, specific status flags which identify the type of error are implemented in the serial channels' control registers. The C161 provides a vectored interrupt system. In this system specific vector locations in the memory space are reserved for the reset, trap, and interrupt service functions. Whenever a request occurs, the CPU branches to the location that is associated with the respective interrupt source. This allows direct identification of the source that caused the request. The only exceptions are the class B hardware traps, which all share the same interrupt vector. The status flags in the Trap Flag Register (TFR) can then be used to determine which exception caused the trap. For the special software TRAP instruction, the vector address is specified by the operand field of the instruction, which is a seven bit trap number. The reserved vector locations build a jump table in the low end of the C161's address space (segment 0). The jump table is made up of the appropriate jump instructions that transfer control to the interrupt or trap service routines, which may be located anywhere within the address space. The entries of the jump table are located at the lowest addresses in code segment 0 of the address space. Each entry occupies 2 words, except for the reset vector and the hardware trap vectors, which occupy 4 or 8 words. The table below lists all sources that are capable of requesting interrupt or PEC service in the C161, the associated interrupt vectors, their locations and the associated trap numbers. It also lists the mnemonics of the affected Interrupt Request flags and their corresponding Interrupt Enable flags. The mnemonics are composed of a part that specifies the respective source, followed by a part that specifies their function (IR=Interrupt Request flag, IE=Interrupt Enable flag). Note: The "External Interrupt Nodes" use naming conventions that are compatible with the respective C167 interrupt nodes Semiconductor Group 5-2 10Jul97@15:19h Interrupt and Trap Functions / C161 Source of Interrupt or PEC Service Request External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Erro Request Flag CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR T2IR T3IR T4IR T5IR T6IR CRIR S0TIR S0TBIR S0RIR S0EIR SSCTIR SSCRIR SSCEIR Enable Flag CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE T2IE T3IE T4IE T5IE T6IE CRIE S0TIE S0TBIE S0RIE S0EIE SSCTIE SSCRIE SSCEIE Interrupt Vector CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT T2INT T3INT T4INT T5INT T6INT CRINT S0TINT S0TBINT S0RINT S0EINT SSCTINT SSCRINT SSCEINT Vector Location 00'0064H 00'0068H 00'006CH 00'0070H 00'0074H 00'0078H 00'007CH 00'0088H 00'008CH 00'0090H 00'0094H 00'0098H 00'009CH 00'00A8H 00'011CH 00'00ACH 00'00B0H 00'00B4H 00'00B8H 00'00BCH Trap Number 19H / 25D 1AH / 26D 1BH / 27D 1CH / 28D 1DH / 29D 1EH / 30D 1FH / 31D 22H / 34D 23H / 35D 24H / 36D 25H / 37D 26H / 38D 27H / 39D 2AH / 42D 47H / 71D 2BH / 43D 2CH / 44D 2DH / 45D 2EH / 46D 2FH / 47D Note: Each entry of the interrupt vector table provides room for two word instructions or one doubleword instruction. The respective vector location results from multiplying the trap number by 4 (4 bytes per entry). The shaded interrupt nodes are only available in the C161O, not in the C161V and the C161K. Semiconductor Group 5-3 10Jul97@15:19h Interrupt and Trap Functions / C161 The table below lists the vector locations for hardware traps and the corresponding status flags in register TFR. It also lists the priorities of trap service for cases, where more than one trap condition might be detected within the same instruction. After any reset (hardware reset, software reset instruction SRST, or reset by watchdog timer overflow) program execution starts at the reset vector at location 00'0000H. Reset conditions have priority over every other system activity and therefore have the highest priority (trap priority III). Software traps may be initiated to any vector location between 00'0000H and 00'01FCH. A service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit field ILVL in register PSW. This means that routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests. Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction Trap Flag Trap Vector RESET RESET RESET Vector Location 00'0000H 00'0000H 00'0000H Trap Number 00H 00H 00H Trap Priority III III III NMI STKOF STKUF UNDOPC PRTFLT ILLOPA ILLINA ILLBUS NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028H 00'0028H 00'0028H 00'0028H 00'0028H 02H 04H 06H 0AH 0AH 0AH 0AH 0AH II II II I I I I I [2CH - 3CH] [0BH - 0FH] Any [00'0000H - 00'01FCH] in steps of 4H Any [00H - 7FH] Current CPU Priority Semiconductor Group 5-4 10Jul97@15:19h Interrupt and Trap Functions / C161 Normal Interrupt Processing and PEC Service During each instruction cycle one out of all sources which require PEC or interrupt processing is selected according to its interrupt priority. This priority of interrupts and PEC requests is programmable in two levels. Each requesting source can be assigned to a specific priority. A second level (called "group priority") allows to specify an internal order for simultaneous requests from a group of different sources on the same priority level. At the end of each instruction cycle the one source request with the highest current priority will be determined by the interrupt system. This request will then be serviced, if its priority is higher than the current CPU priority in register PSW. Interrupt System Register Description Interrupt processing is controlled globally by register PSW through a general interrupt enable bit (IEN) and the CPU priority field (ILVL). Additionally the different interrupt sources are controlled individually by their specific interrupt control registers (...IC). Thus, the acceptance of requests by the CPU is determined by both the individual interrupt control registers and the PSW. PEC services are controlled by the respective PECCx register and the source and destination pointers, which specify the task of the respective PEC service channel. Interrupt Control Registers All interrupt control registers are organized identically. The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source, which is required during one round of prioritization, the upper 8 bits of the respective register are reserved.. All interrupt control registers are bit-addressable and all bits can be read or written via software. This allows each interrupt source to be programmed or modified with just one instruction. When accessing interrupt control registers through instructions which operate on word data types, their upper 8 bits (15...8) will return zeros, when read, and will discard written data. The layout of the Interrupt Control registers shown below applies to each xxIC register, where xx stands for the mnemonic for the respective source. Semiconductor Group 5-5 10Jul97@15:19h Interrupt and Trap Functions / C161 xxIC (yyyyH / zzH) 15 14 13 12 11 10 9 8 7 6 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 xxIR xxIE rw rw GLVL rw Bit GLVL Function Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority Interrupt Priority Level Defines the priority level for the arbitration of requests. FH: Highest priority level 0H: Lowest priority level Interrupt Enable Control Bit (individually enables/disables a specific source) `0': Interrupt request is disabled `1': Interrupt Request is enabled Interrupt Request Flag `0': No request pending `1': This source has raised an interrupt request ILVL xxIE xxIR The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs. It is cleared automatically upon entry into the interrupt service routine or upon a PEC service. In the case of PEC service the Interrupt Request flag remains set, if the COUNT field in register PECCx of the selected PEC channel decrements to zero. This allows a normal CPU interrupt to respond to a completed PEC block transfer. Note: Modifying the Interrupt Request flag via software causes the same effects as if it had been set or cleared by hardware. Interrupt Priority Level and Group Level The four bits of bit field ILVL specify the priority level of a service request for the arbitration of simultaneous requests. The priority increases with the numerical value of ILVL, so 0000 B is the lowest and 1111B is the highest priority level. When more than one interrupt request on a specific level gets active at the same time, the values in the respective bit fields GLVL are used for second level arbitration to select one request for being serviced. Again the group priority increases with the numerical value of GLVL, so 00 B is the lowest and 11B is the highest group priority. Note: All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities. Otherwise an incorrect interrupt vector will be generated. Semiconductor Group 5-6 10Jul97@15:19h Interrupt and Trap Functions / C161 Upon entry into the interrupt service routine, the priority level of the source that won the arbitration and who's priority level is higher than the current CPU level, is copied into bit field ILVL of register PSW after pushing the old PSW contents on the stack. The interrupt system of the C161 allows nesting of up to 15 interrupt service routines of different priority levels (level 0 cannot be arbitrated). Interrupt requests that are programmed to priority levels 15 or 14 (ie, ILVL=111XB) will be serviced by the PEC, unless the COUNT field of the associated PECC register contains zero. In this case the request will instead be serviced by normal interrupt processing. Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing. Note: Priority level 0000B is the default level of the CPU. Therefore a request on level 0 will never be serviced, because it can never interrupt the CPU. However, an enabled interrupt request on level 0000B will terminate the C161's Idle mode and reactivate the CPU. For interrupt requests which are to be serviced by the PEC, the associated PEC channel number is derived from the respective ILVL (LSB) and GLVL (see figure below). So programming a source to priority level 15 (ILVL=1111B) selects the PEC channel group 7...4, programming a source to priority level 14 (ILVL=1110B) selects the PEC channel group 3...0. The actual PEC channel number is then determined by the group priority field GLVL. Interrupt Control Register PEC Control Figure 5-1 Priority Levels and PEC Channels Simultaneous requests for PEC channels are prioritized according to the PEC channel number, where channel 0 has lowest and channel 8 has highest priority. Note: All sources that request PEC service must be programmed to different PEC channels. Otherwise an incorrect PEC channel may be activated. Semiconductor Group 5-7 10Jul97@15:19h Interrupt and Trap Functions / C161 The table below shows in a few examples, which action is executed with a given programming of an interrupt control register. Priority Level ILVL 1111 1111 1110 1101 0001 0001 0000 GLVL 11 10 10 10 11 00 XX COUNT = 00H CPU interrupt, level 15, group priority 3 CPU interrupt, level 15, group priority 2 CPU interrupt, level 14, group priority 2 CPU interrupt, level 13, group priority 2 CPU interrupt, level 1, group priority 3 CPU interrupt, level 1, group priority 0 No service! Type of Service COUNT 00H PEC service, channel 7 PEC service, channel 6 PEC service, channel 2 CPU interrupt, level 13, group priority 2 CPU interrupt, level 1, group priority 3 CPU interrupt, level 1, group priority 0 No service! Note: All requests on levels 13...1 cannot initiate PEC transfers. They are always serviced by an interrupt service routine. No PECC register is associated and no COUNT field is checked. Interrupt Control Functions in the PSW The Processor Status Word (PSW) is functionally divided into 2 parts: the lower byte of the PSW basically represents the arithmetic status of the CPU, the upper byte of the PSW controls the interrupt system of the C161 and the arbitration mechanism for the external bus interface. Note: Pipeline effects have to be considered when enabling/disabling interrupt requests via modifications of register PSW (see chapter "The Central Processing Unit"). Semiconductor Group 5-8 10Jul97@15:19h Interrupt and Trap Functions / C161 PSW (FF10H / 88H) 15 14 13 12 11 IEN rw 10 9 8 - SFR 7 6 USR0 rw 5 MUL IP rw 4 E rw Reset Value: 0000H 3 Z rw 2 V rw 1 C rw 0 N rw ILVL rw Bit N, C, V, Z, E, MULIP, USR0 ILVL Function CPU status flags (Described in section "The Central Processing Unit") Define the current status of the CPU (ALU, multiplication unit). CPU Priority Level Defines the current priority level for the CPU FH: Highest priority level 0H: Lowest priority level Interrupt Enable Control Bit (globally enables/disables interrupt requests) `0': Interrupt requests are disabled `1': Interrupt requests are enabled IEN CPU Priority ILVL defines the current level for the operation of the CPU. This bit field reflects the priority level of the routine that is currently executed. Upon the entry into an interrupt service routine this bit field is updated with the priority level of the request that is being serviced. The PSW is saved on the system stack before. The CPU level determines the minimum interrupt priority level that will be serviced. Any request on the same or a lower level will not be acknowledged. The current CPU priority level may be adjusted via software to control which interrupt request sources will be acknowledged. PEC transfers do not really interrupt the CPU, but rather "steal" a single cycle, so PEC services do not influence the ILVL field in the PSW. Hardware traps switch the CPU level to maximum priority (ie. 15) so no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed. Note: The TRAP instruction does not change the CPU level, so software invoked trap service routines may be interrupted by higher requests. Interrupt Enable bit IEN globally enables or disables PEC operation and the acceptance of interrupts by the CPU. When IEN is cleared, no interrupt requests are accepted by the CPU. When IEN is set to '1', all interrupt sources, which have been individually enabled by the interrupt enable bits in their associated control registers, are globally enabled. Note: Traps are non-maskable and are therefore not affected by the IEN bit. Semiconductor Group 5-9 10Jul97@15:19h Interrupt and Trap Functions / C161 5.2 Operation of the PEC Channels The C161's Peripheral Event Controller (PEC) provides 8 PEC service channels, which move a single byte or word between two locations in segment 0 (data pages 3...0). This is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request (eg. serial channels, etc.). Each channel is controlled by a dedicated PEC Channel Counter/Control register (PECCx) and a pair of pointers for source (SRCPx) and destination (DSTPx) of the data transfer. The PECC registers control the action that is performed by the respective PEC channel. PECCx (FECyH / 6zH, see table) 15 14 13 12 11 10 INC rw 9 8 BWT rw SFR 7 6 5 4 Reset Value: 0000H 3 2 1 0 COUNT rw Bit COUNT BWT Function PEC Transfer Count Counts PEC transfers and influences the channel's action (see table below) Byte / Word Transfer Selection 0: Transfer a Word 1: Transfer a Byte Increment Control (Modification of SRCPx or DSTPx) 0 0: Pointers are not modified 0 1: Increment DSTPx by 1 or 2 (BWT) 1 0: Increment SRCPx by 1 or 2 (BWT) 1 1: Reserved. Do not use this combination. (changed to 10 by hardware) INC PEC Control Register Addresses Register PECC0 PECC1 PECC2 PECC3 Address Reg. Space Register PECC4 PECC5 PECC6 PECC7 Address Reg. Space FEC0H / 60H SFR FEC2H / 61H SFR FEC4H / 62H SFR FEC6H / 63H SFR FEC8H / 64H SFR FECAH / 65H SFR FECCH / 66H SFR FECEH / 67H SFR Byte/Word Transfer bit BWT controls, if a byte or a word is moved during a PEC service cycle. This selection controls the transferred data size and the increment step for the modified pointer. Semiconductor Group 5-10 10Jul97@15:19h Interrupt and Trap Functions / C161 Increment Control Field INC controls, if one of the PEC pointers is incremented after the PEC transfer. It is not possible to increment both pointers, however. If the pointers are not modified (INC='00'), the respective channel will always move data from the same source to the same destination. Note: The reserved combination `11' is changed to `10' by hardware. However, it is not recommended to use this combination. The PEC Transfer Count Field COUNT controls the action of a respective PEC channel, where the content of bit field COUNT at the time the request is activated selects the action. COUNT may allow a specified number of PEC transfers, unlimited transfers or no PEC service at all. The table below summarizes, how the COUNT field itself, the interrupt requests flag IR and the PEC channel action depends on the previous content of COUNT. Previous Modified COUNT COUNT FFH FFH IR after Action of PEC Channel PEC service and Comments `0' `0' `1' (`1') Move a Byte / Word Continuous transfer mode, ie. COUNT is not modified Move a Byte / Word and decrement COUNT Move a Byte / Word Leave request flag set, which triggers another request No action! Activate interrupt service routine rather than PEC channel. FEH..02H FDH..01H 01H 00H 00H 00H The PEC transfer counter allows to service a specified number of requests by the respective PEC channel, and then (when COUNT reaches 00H) activate the interrupt service routine, which is associated with the priority level. After each PEC transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced. Continuous transfers are selected by the value FFH in bit field COUNT. In this case COUNT is not modified and the respective PEC channel services any request until it is disabled again. When COUNT is decremented from 01H to 00H after a transfer, the request flag is not cleared, which generates another request from the same source. When COUNT already contains the value 00H, the respective PEC channel remains idle and the associated interrupt service routine is activated instead. This allows to choose, if a level 15 or 14 request is to be serviced by the PEC or by the interrupt service routine. Note: PEC transfers are only executed, if their priority level is higher than the CPU level, ie. only PEC channels 7...4 are processed, while the CPU executes on level 14. All interrupt request sources that are enabled and programmed for PEC service should use different channels. Otherwise only one transfer will be performed for all simultaneous requests. When COUNT is decremented to 00H, and the CPU is to be interrupted, an incorrect interrupt vector will be generated. Semiconductor Group 5-11 10Jul97@15:19h Interrupt and Trap Functions / C161 The source and destination pointers specifiy the locations between which the data is to be moved. A pair of pointers (SRCPx and DSTPx) is associated with each of the 8 PEC channels. These pointers do not reside in specific SFRs, but are mapped into the internal RAM of the C161 just below the bit-addressable area (see figure below). DSTP7 SRCP7 DSTP6 SRCP6 DSTP5 SRCP5 DSTP4 SRCP4 00'FCFEH 00'FCFCH 00'FCFAH 00'FCF8H 00'FCF6H 00'FCF4H 00'FCF2H 00'FCF0H DSTP3 SRCP3 DSTP2 SRCP2 DSTP1 SRCP1 DSTP0 SRCP0 00'FCEEH 00'FCECH 00'FCEAH 00'FCE8H 00'FCE6H 00'FCE4H 00'FCE2H 00'FCE0H Figure 5-2 Mapping of PEC Pointers into the Internal RAM PEC data transfers do not use the data page pointers DPP3...DPP0. The PEC source and destination pointers are used as 16-bit intra-segment addresses within segment 0, so data can be transferred between any two locations within the first four data pages 3...0. The pointer locations for inactive PEC channels may be used for general data storage. Only the required pointers occupy RAM locations. Note: If word data transfer is selected for a specific PEC channel (ie. BWT='0'), the respective source and destination pointers must both contain a valid word address which points to an even byte boundary. Otherwise the Illegal Word Access trap will be invoked, when this channel is used. Semiconductor Group 5-12 10Jul97@15:19h Interrupt and Trap Functions / C161 5.3 Prioritization of Interrupt and PEC Service Requests Interrupt and PEC service requests from all sources can be enabled, so they are arbitrated and serviced (if they win), or they may be disabled, so their requests are disregarded and not serviced. Enabling and disabling interrupt requests may be done via three mechanisms: Control Bits allow to switch each individual source "ON" or "OFF", so it may generate a request or not. The control bits (xxIE) are located in the respective interrupt control registers. All interrupt requests may be enabled or disabled generally via bit IEN in register PSW. This control bit is the "main switch" that selects, if requests from any source are accepted or not. For a specific request to be arbitrated the respective source's enable bit and the global enable bit must both be set. The Priority Level automatically selects a certain group of interrupt requests that will be acknowledged, disclosing all other requests. The priority level of the source that won the arbitration is compared against the CPU's current level and the source is only serviced, if its level is higher than the current CPU level. Changing the CPU level to a specific value via software blocks all requests on the same or a lower level. An interrupt source that is assigned to level 0 will be disabled and never be serviced. The ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1...4 instructions. This is useful eg. for semaphore handling and does not require to re-enable the interrupt system after the unseparable instruction sequence (see chapter "System Programming"). Interrupt Class Management An interrupt class covers a set of interrupt sources with the same importance, ie. the same priority from the system's viewpoint. Interrupts of the same class must not interrupt each other. The C161 supports this function with two features: Classes with up to 4 members can be established by using the same interrupt priority (ILVL) and assigning a dedicated group level (GLVL) to each member. This functionality is built-in and handled automatically by the interrupt controller. Classes with more than 4 members can be established by using a number of adjacent interrupt priorities (ILVL) and the respective group levels (4 per ILVL). Each interrupt service routine within this class sets the CPU level to the highest interrupt priority within the class. All requests from the same or any lower level are blocked now, ie. no request of this class will be accepted. The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities, depending on the number of members in a class. A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8, which is the highest priority (ILVL) in class 2. Class 1 requests or PEC requests are still serviced in this case. The 19 interrupt sources (excluding PEC requests) are so assigned to 3 classes of priority rather than to 7 different levels, as the hardware support would do. Semiconductor Group 5-13 10Jul97@15:19h Interrupt and Trap Functions / C161 Software controlled Interrupt Classes (Example) ILVL (Priority) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No service! X X X X X X X X Interrupt Class 3 5 sources on 2 levels X X X X X X Interrupt Class 2 9 sources on 3 levels X X X X X Interrupt Class 1 5 sources on 2 levels GLVL 3 2 1 0 PEC service on up to 8 channels Interpretation 5.4 Saving the Status during Interrupt Service Before an interrupt request that has been arbitrated is actually serviced, the status of the current task is automatically saved on the system stack. The CPU status (PSW) is saved along with the location, where the execution of the interrupted task is to be resumed after returning from the service routine. This return location is specified through the Instruction Pointer (IP) and, in case of a segmented memory model, the Code Segment Pointer (CSP). Bit SGTDIS in register SYSCON controls, how the return location is stored. The system stack receives the PSW first, followed by the IP (unsegmented) or followed by CSP and then IP (segmented mode). This optimizes the usage of the system stack, if segmentation is disabled. The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request that is to be serviced, so the CPU now executes on the new level. If a multiplication or division was in progress at the time the interrupt request was acknowledged, bit MULIP in register PSW is set to `1'. In this case the return location that is saved on the stack is not the next instruction in the instruction flow, but rather the multiply or divide instruction itself, as this instruction has been interrupted and will be completed after returning from the service routine. Semiconductor Group 5-14 10Jul97@15:19h Interrupt and Trap Functions / C161 Figure 5-3 Task Status saved on the System Stack The interrupt request flag of the source that is being serviced is cleared. The IP is loaded with the vector associated with the requesting source (the CSP is cleared in case of segmentation) and the first instruction of the service routine is fetched from the respective vector location, which is expected to branch to the service routine itself. The data page pointers and the context pointer are not affected. When the interrupt service routine is left (RETI is executed), the status information is popped from the system stack in the reverse order, taking into account the value of bit SGTDIS. Context Switching An interrupt service routine usually saves all the registers it uses on the stack, and restores them before returning. The more registers a routine uses, the more time is wasted with saving and restoring. The C161 allows to switch the complete bank of CPU registers (GPRs) with a single instruction, so the service routine executes within its own, separate context. The instruction "SCXT CP, #New_Bank" pushes the content of the context pointer (CP) on the system stack and loads CP with the immediate value "New_Bank", which selects a new register bank. The service routine may now use its "own registers". This register bank is preserved, when the service routine terminates, ie. its contents are available on the next call. Before returning (RETI) the previous CP is simply POPped from the system stack, which returns the registers to the original bank. Note: The first instruction following the SCXT instruction must not use a GPR. Resources that are used by the interrupting program must eventually be saved and restored, eg. the DPPs and the registers of the MUL/DIV unit. Semiconductor Group 5-15 10Jul97@15:19h Interrupt and Trap Functions / C161 5.5 Interrupt Response Times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction (I1) being fetched from the interrupt vector location. The basic interrupt response time for the C161 is 3 instruction cycles. Pipeline Stage FETCH DECODE EXECUTE WRITEBACK Cycle 1 N N-1 N-2 N-3 Cycle 2 N+1 N N-1 N-2 Cycle 3 N+2 TRAP (1) N N-1 Cycle 4 I1 TRAP (2) TRAP N IR-Flag 1 0 Interrupt Response Time Figure 5-4 Pipeline Diagram for Interrupt Response Time All instructions in the pipeline including instruction N (during which the interrupt request flag is set) are completed before entering the service routine. The actual execution time for these instructions (eg. waitstates) therefore influences the interrupt response time. In the figure above the respective interrupt request flag is set in cycle 1 (fetching of instruction N). The indicated source wins the prioritization round (during cycle 2). In cycle 3 a TRAP instruction is injected into the decode stage of the pipeline, replacing instruction N+1 and clearing the source's interrupt request flag to '0'. Cycle 4 completes the injected TRAP instruction (save PSW, IP and CSP, if segmented mode) and fetches the first instruction (I1) from the respective vector location. All instructions that entered the pipeline after setting of the interrupt request flag (N+1, N+2) will be executed after returning from the interrupt service routine. The minimum interrupt response time is 5 states (250 ns @ 20 MHz CPU clock). This requires program execution from the internal ROM, no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle. When the interrupt request flag is set during the first state of an instruction cycle, the minimum interrupt response time under these conditions is 6 state times (300 ns @ 20 MHz CPU clock). The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine (including N). Semiconductor Group 5-16 10Jul97@15:19h Interrupt and Trap Functions / C161 * When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, or instruction N explicitly writes to the PSW or the SP, the minimum interrupt response time may be extended by 1 state time for each of these conditions. * When instruction N reads an operand from the internal ROM, or when N is a call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum interrupt response time may additionally be extended by 2 state times during internal ROM program execution. * In case instruction N reads the PSW and instruction N-1 has an effect on the condition flags, the interrupt response time may additionally be extended by 2 state times. The worst case interrupt response time during internal ROM program execution adds to 12 state times (600 ns @ 20 MHz CPU clock). Any reference to external locations increases the interrupt response time due to pipeline related access priorities. The following conditions have to be considered: * Instruction fetch from an external location * Operand read from an external location * Result write-back to an external location Depending on where the instructions, source and destination operands are located, there are a number of combinations. Note, however, that only access conflicts contribute to the delay. A few examples illustrate these delays: * The worst case interrupt response time including external accesses will occur, when instructions N, N+1 and N+2 are executed out of external memory, instructions N-1 and N require external operand read accesses, instructions N-3 through N write back external operands, and the interrupt vector also points to an external location. In this case the interrupt response time is the time to perform 9 word bus accesses, because instruction I1 cannot be fetched via the external bus until all write, fetch and read requests of preceding instructions in the pipeline are terminated. * When the above example has the interrupt vector pointing into the internal ROM, the interrupt response time is 7 word bus accesses plus 2 states, because fetching of instruction I1 from internal ROM can start earlier. * When instructions N, N+1 and N+2 are executed out of external memory and the interrupt vector also points to an external location, but all operands for instructions N-3 through N are in internal memory, then the interrupt response time is the time to perform 3 word bus accesses. * When the above example has the interrupt vector pointing into the internal ROM, the interrupt response time is 1 word bus access plus 4 states. After an interrupt service routine has been terminated by executing the RETI instruction, and if further interrupts are pending, the next interrupt service routine will not be entered until at least two instruction cycles have been executed of the program that was interrupted. In most cases two instructions will be executed during this time. Only one instruction will typically be executed, if the first instruction following the RETI instruction is a branch instruction (without cache hit), or if it reads an operand from internal ROM, or if it is executed out of the internal RAM. Note: A bus access in this context also includes delays caused by an external READY signal or by bus arbitration (HOLD mode). Semiconductor Group 5-17 10Jul97@15:19h Interrupt and Trap Functions / C161 PEC Response Times The PEC response time defines the time from an interrupt request flag of an enabled interrupt source being set until the PEC data transfer being started. The basic PEC response time for the C161 is 2 instruction cycles. Pipeline Stage FETCH DECODE EXECUTE WRITEBACK Cycle 1 N N-1 N-2 N-3 Cycle 2 N+1 N N-1 N-2 Cycle 3 N+2 PEC N N-1 Cycle 4 N+2 N+1 PEC N IR-Flag 1 0 PEC Response Time Figure 5-5 Pipeline Diagram for PEC Response Time In the figure above the respective interrupt request flag is set in cycle 1 (fetching of instruction N). The indicated source wins the prioritization round (during cycle 2). In cycle 3 a PEC transfer "instruction" is injected into the decode stage of the pipeline, suspending instruction N+1 and clearing the source's interrupt request flag to '0'. Cycle 4 completes the injected PEC transfer and resumes the execution of instruction N+1. All instructions that entered the pipeline after setting of the interrupt request flag (N+1, N+2) will be executed after the PEC data transfer. Note: When instruction N reads any of the PEC control registers PECC7...PECC0, while a PEC request wins the current round of prioritization, this round is repeated and the PEC data transfer is started one cycle later. The minimum PEC response time is 3 states (187.5 ns @ 16 MHz CPU clock). This requires program execution from the internal ROM, no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle. When the interrupt request flag is set during the first state of an instruction cycle, the minimum PEC response time under these conditions is 4 state times (250 ns @ 16 MHz CPU clock). Semiconductor Group 5-18 10Jul97@15:19h Interrupt and Trap Functions / C161 The PEC response time is increased by all delays of the instructions in the pipeline that are executed before starting the data transfer (including N). * When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, the minimum PEC response time may be extended by 1 state time for each of these conditions. * When instruction N reads an operand from the internal ROM, or when N is a call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum PEC response time may additionally be extended by 2 state times during internal ROM program execution. * In case instruction N reads the PSW and instruction N-1 has an effect on the condition flags, the PEC response time may additionally be extended by 2 state times. The worst case PEC response time during internal ROM program execution adds to 9 state times (562.5 ns @ 16 MHz CPU clock). Any reference to external locations increases the PEC response time due to pipeline related access priorities. The following conditions have to be considered: * Instruction fetch from an external location * Operand read from an external location * Result write-back to an external location Depending on where the instructions, source and destination operands are located, there are a number of combinations. Note, however, that only access conflicts contribute to the delay. A few examples illustrate these delays: * The worst case interrupt response time including external accesses will occur, when instructions N and N+1 are executed out of external memory, instructions N-1 and N require external operand read accesses and instructions N-3, N-2 and N-1 write back external operands. In this case the PEC response time is the time to perform 7 word bus accesses. * When instructions N and N+1 are executed out of external memory, but all operands for instructions N-3 through N-1 are in internal memory, then the PEC response time is the time to perform 1 word bus access plus 2 state times. Once a request for PEC service has been acknowledged by the CPU, the execution of the next instruction is delayed by 2 state times plus the additional time it might take to fetch the source operand from internal ROM or external memory and to write the destination operand over the external bus in an external program environment. Note: A bus access in this context also includes delays caused by an external READY signal or by bus arbitration (HOLD mode). Semiconductor Group 5-19 10Jul97@15:19h Interrupt and Trap Functions / C161 5.6 External Interrupts Although the C161 has no dedicated INTR input pins, it provides many possibilities to react on external asynchronous events by using a number of IO lines for interrupt input. The interrupt function may either be combined with the pin's main function or may be used instead of it, ie. if the main pin function is not required. Interrupt signals may be connected to: * T4IN, T2IN, the timer input pins, * CAPIN, the capture input of GPT2 For each of these pins either a positive, a negative, or both a positive and a negative external transition can be selected to cause an interrupt or PEC service request. The edge selection is performed in the control register of the peripheral device associated with the respective port pin. The peripheral must be programmed to a specific operating mode to allow generation of an interrupt by the external signal. The priority of the interrupt request is determined by the interrupt control register of the respective peripheral interrupt source, and the interrupt vector of this source will be used to service the external interrupt request. Note: In order to use any of the listed pins as external interrupt input, it must be switched to input mode via its direction control bit DPx.y in the respective port direction control register DPx. Pins to be used as External Interrupt Inputs Port Pin P3.7/T2IN P3.5/T4IN P3.2/CAPIN Original Function Auxiliary timer T2 input pin Auxiliary timer T4 input pin GPT2 capture input pin Control Register T2CON T4CON T5CON Pins T2IN or T4IN can be used as external interrupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode. This mode is selected by programming the mode control fields T2M or T4M in control registers T2CON or T4CON to 101B. The active edge of the external input signal is determined by bit fields T2I or T4I. When these fields are programmed to X01B, interrupt request flags T2IR or T4IR in registers T2IC or T4IC will be set on a positive external transition at pins T2IN or T4IN, respectively. When T2I or T4I are programmed to X10B, then a negative external transition will set the corresponding request flag. When T2I or T4I are programmed to X11B, both a positive and a negative transition will set the request flag. In all three cases, the contents of the core timer T3 will be captured into the auxiliary timer registers T2 or T4 based on the transition at pins T2IN or T4IN. When the interrupt enable bits T2IE or T4IE are set, a PEC request or an interrupt request for vector T2INT or T4INT will be generated. Pin CAPIN differs slightly from the timer input pins as it can be used as external interrupt input pin without affecting peripheral functions. When the capture mode enable bit T5SC in register T5CON is cleared to '0', signal transitions on pin CAPIN will only set the interrupt request flag CRIR in register CRIC, and the capture function of register CAPREL is not activated. Note: The GPT2 unit is only available on the C161O, not on the C161V and the C161K. Semiconductor Group 5-20 10Jul97@15:19h Interrupt and Trap Functions / C161 So register CAPREL can still be used as reload register for GPT2 timer T5, while pin CAPIN serves as external interrupt input. Bit field CI in register T5CON selects the effective transition of the external interrupt input signal. When CI is programmed to 01 B, a positive external transition will set the interrupt request flag. CI=10B selects a negative transition to set the interrupt request flag, and with CI=11B, both a positive and a negative transition will set the request flag. When the interrupt enable bit CRIE is set, an interrupt request for vector CRINT or a PEC request will be generated. Note: The non-maskable interrupt input pin NMI and the reset input RSTIN provide another possibility for the CPU to react on an external input signal. NMI and RSTIN are dedicated input pins, which cause hardware traps. Fast External Interrupts The input pins that may be used for external interrupts are sampled every 500 ns (@ 16 MHz CPU clock), ie. external events are scanned and detected in timeframes of 400 ns. The C161 provides 7 interrupt inputs (4 on the C161V and C161K) that are sampled every 62.5 ns (@ 16 MHz CPU clock), so external events are captured faster than with standard interrupt inputs. The pins of Port 2 (P2.15...P2.9) can individually be programmed to this fast interrupt mode, where also the trigger transition (rising, falling or both) can be selected. The External Interrupt Control register EXICON controls this feature for all 7 pins. EXICON (F1C0H / E0H) 15 14 13 12 11 10 9 ESFR 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 - EXI7ES rw EXI6ES rw EXI5ES rw EXI4ES rw EXI3ES rw EXI2ES rw EXI1ES rw Bit EXIxES Function External Interrupt x Edge Selection Field (x=7...1) 0 0: Fast external interrupts disabled: standard mode 0 1: Interrupt on positive edge (rising) 1 0: Interrupt on negative edge (falling) 1 1: Interrupt on any edge (rising or falling) These fast external interrupt nodes and vectors are named according to the C167's CAPCOM channels CC15...CC9, so interrupt nodes receive equal names throughout the architecture. See register description below. Note: The fast external interrupt inputs are sampled every 62.5 ns. The interrupt request arbitration and processing, however, is executed every 250 ns (both @ 16 MHz CPU clock). Semiconductor Group 5-21 10Jul97@15:19h Interrupt and Trap Functions / C161 The interrupt control registers listed below (CC15IC...CC9IC) control the fast external interrupts of the C161. They are named according to the C167's CAPCOM channels, so interrupt nodes receive equal names throughout the architecture. CCxIC (See Table) 15 14 13 12 11 10 9 8 SFR 7 CCx IR 6 CCx IE rw 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 GLVL rw - - - - - - - - rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. Fast External Interrupt Control Register Addresses Register CC9IC CC10IC CC11IC CC12IC CC13IC CC14IC CC15IC Address FF8AH / C5H FF8CH / C6H FF8EH / C7H FF90H / C8H FF92H / C9H FF94H / CAH FF96H / CBH External Interrupt EX1IN EX2IN EX3IN EX4IN EX5IN EX6IN EX7IN Semiconductor Group 5-22 10Jul97@15:19h Interrupt and Trap Functions / C161 5.7 Trap Functions Traps interrupt the current execution similar to standard interrupts. However, trap functions offer the possibility to bypass the interrupt system's prioritization process in cases where immediate system reaction is required. Trap functions are not maskable and always have priority over interrupt requests on any priority level. The C161 provides two different kinds of trapping mechanisms. Hardware traps are triggered by events that occur during program execution (eg. illegal access or undefined opcode), software traps are initiated via an instruction within the current execution flow. Software Traps The TRAP instruction is used to cause a software call to an interrupt service routine. The trap number that is specified in the operand field of the trap instruction determines which vector location in the address range from 00'0000H through 00'01FCH will be branched to. Executing a TRAP instruction causes a similar effect as if an interrupt at the same vector had occurred. PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and a jump is taken to the specified vector location. When segmentation is enabled and a trap is executed, the CSP for the trap service routine is set to code segment 0. No Interrupt Request flags are affected by the TRAP instruction. The interrupt service routine called by a TRAP instruction must be terminated with a RETI (return from interrupt) instruction to ensure correct operation. Note: The CPU level in register PSW is not modified by the TRAP instruction, so the service routine is executed on the same priority level from which it was invoked. Therefore, the service routine entered by the TRAP instruction can be interrupted by other traps or higher priority interrupts, other than when triggered by a hardware trap. Hardware Traps Hardware traps are issued by faults or specific system states that occur during runtime of a program (not identified at assembly time). A hardware trap may also be triggered intentionally, eg. to emulate additional instructions by generating an Illegal Opcode trap. The C161 distinguishes eight different hardware trap functions. When a hardware trap condition has been detected, the CPU branches to the trap vector location for the respective trap condition. Depending on the trap condition, the instruction which caused the trap is either completed or cancelled (ie. it has no effect on the system state) before the trap handling routine is entered. Hardware traps are non-maskable and always have priority over every other CPU activity. If several hardware trap conditions are detected within the same instruction cycle, the highest priority trap is serviced (see table in section "Interrupt System Structure"). PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and the CPU level in register PSW is set to the highest possible priority level (ie. level 15), disabling all interrupts. The CSP is set to code segment zero, if segmentation is enabled. A trap service routine must be terminated with the RETI instruction. Semiconductor Group 5-23 10Jul97@15:19h Interrupt and Trap Functions / C161 The eight hardware trap functions of the C161 are divided into two classes: Class A traps are * external Non-Maskable Interrupt (NMI) * Stack Overflow * Stack Underflow trap These traps share the same trap priority, but have an individual vector address. Class B traps are * Undefined Opcode * Protection Fault * Illegal Word Operand Access * Illegal Instruction Access * Illegal External Bus Access Trap These traps share the same trap priority, and the same vector address. The bit-addressable Trap Flag Register (TFR) allows a trap service routine to identify the kind of trap which caused the exception. Each trap function is indicated by a separate request flag. When a hardware trap occurs, the corresponding request flag in register TFR is set to '1'. TFR (FFACH / D6H) 15 NMI rw 14 STK OF rw 13 STK UF rw 12 11 10 9 8 - SFR 7 UND OPC rw 6 5 4 - Reset Value: 0000H 3 2 1 ILL INA rw 0 ILL BUS rw PRT ILL FLT OPA rw rw Bit ILLBUS ILLINA ILLOPA PRTFLT UNDOPC STKUF STKOF NMI Function Illegal External Bus Access Flag An external access has been attempted with no external bus defined. Illegal Instruction Access Flag A branch to an odd address has been attempted. Illegal Word Operand Access Flag A word operand access (read or write) to an odd address has been attempted. Protection Fault Flag A protected instruction with an illegal format has been detected. Undefined Opcode Flag The currently decoded instruction has no valid C161 opcode. Stack Underflow Flag The current stack pointer value exceeds the content of register STKUN. Stack Overflow Flag The current stack pointer value falls below the content of register STKOV. Non Maskable Interrupt Flag A negative transition (falling edge) has been detected on pin NMI. Semiconductor Group 5-24 10Jul97@15:19h Interrupt and Trap Functions / C161 Note: The trap service routine must clear the respective trap flag, otherwise a new trap will be requested after exiting the service routine. Setting a trap request flag by software causes the same effects as if it had been set by hardware. The reset functions (hardware, software, watchdog) may be regarded as a type of trap. Reset functions have the highest system priority (trap priority III). Class A traps have the second highest priority (trap priority II), on the 3rd rank are class B traps, so a class A trap can interrupt a class B trap. If more than one class A trap occur at a time, they are prioritized internally, with the NMI trap on the highest and the stack underflow trap on the lowest priority. All class B traps have the same trap priority (trap priority I). When several class B traps get active at a time, the corresponding flags in the TFR register are set and the trap service routine is entered. Since all class B traps have the same vector, the priority of service of simultaneously occurring class B traps is determined by software in the trap service routine. A class A trap occurring during the execution of a class B trap service routine will be serviced immediately. During the execution of a class A trap service routine, however, any class B trap occurring will not be serviced until the class A trap service routine is exited with a RETI instruction. In this case, the occurrence of the class B trap condition is stored in the TFR register, but the IP value of the instruction which caused this trap is lost. In the case where e.g. an Undefined Opcode trap (class B) occurs simultaneously with an NMI trap (class A), both the NMI and the UNDOPC flag is set, the IP of the instruction with the undefined opcode is pushed onto the system stack, but the NMI trap is executed. After return from the NMI service routine, the IP is popped from the stack and immediately pushed again because of the pending UNDOPC trap. External NMI Trap Whenever a high to low transition on the dedicated external NMI pin (Non-Maskable Interrupt) is detected, the NMI flag in register TFR is set and the CPU will enter the NMI trap routine. The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap. Stack Overflow Trap Whenever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV, the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine. Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP. When an implicit decrement of the SP is made through a PUSH or CALL instruction, or upon interrupt or trap entry, the IP value pushed is the address of the following instruction. When the SP is decremented by a subtract instruction, the IP value pushed represents the address of the instruction after the instruction following the subtract instruction. For recovery from stack overflow it must be ensured that there is enough excess space on the stack for saving the current system state (PSW, IP, in segmented mode also CSP) twice. Otherwise, a system reset should be generated. Semiconductor Group 5-25 10Jul97@15:19h Interrupt and Trap Functions / C161 Stack Underflow Trap Whenever the stack pointer is incremented to a value which is greater than the value in the stack underflow register STKUN, the STKUF flag is set in register TFR and the CPU will enter the stack underflow trap routine. Again, which IP value will be pushed onto the system stack depends on which operation caused the increment of the SP. When an implicit increment of the SP is made through a POP or return instruction, the IP value pushed is the address of the following instruction. When the SP is incremented by an add instruction, the pushed IP value represents the address of the instruction after the instruction following the add instruction. Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid C161 opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine. The IP value pushed onto the system stack is the address of the instruction that caused the trap. This can be used to emulate unimplemented instructions. The trap service routine can examine the faulting instruction to decode operands for unimplemented opcodes based on the stacked IP. In order to resume processing, the stacked IP value must be incremented by the size of the undefined instruction, which is determined by the user, before a RETI instruction is executed. Protection Fault Trap Whenever one of the special protected instructions is executed where the opcode of that instruction is not repeated twice in the second word of the instruction and the byte following the opcode is not the complement of the opcode, the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine. The protected instructions include DISWDT, EINIT, IDLE, PWRDN, SRST, and SRVWDT. The IP value pushed onto the system stack for the protection fault trap is the address of the instruction that caused the trap. Illegal Word Operand Access Trap Whenever a word operand read or write access is attempted to an odd byte address, the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine. The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap. Illegal Instruction Access Trap Whenever a branch is made to an odd byte address, the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine. The IP value pushed onto the system stack is the illegal odd target address of the branch instruction. Illegal External Bus Access Trap Whenever the CPU requests an external instruction fetch, data read or data write, and no external bus configuration has been specified, the ILLBUS flag in register TFR is set and the CPU enters the illegal bus access trap routine. The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap. Semiconductor Group 5-26 10Jul97@15:19h Parallel Ports / C161 6 Parallel Ports In order to accept or generate single external control signals or parallel data, the C161 provides up to 63 parallel IO lines organized into six IO ports and one input port: PORT0 made of P0H and P0L (8-bit), PORT1 made of P1H and P1L (8-bit), Port 2 (7-bit), Port 4 (6-bit), Port 6 (4-bit), Port 3 (12-bit) and Port 5 (2-bit). These port lines may be used for general purpose Input/Output controlled via software or may be used implicitly by the C161's integrated peripherals or the External Bus Controller. All port lines are bit addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers (except Port 5, of course). The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three IO ports (2, 3, 6) can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. A write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A read-modify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. Writing to a pin configured as an output (DPx.y=`1') causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin. Data Input / Output Registers Direction Control Registers Open Drain Control Registers P0L P0H P1L P1H P2 P3 P4 P5 P6 DP0L DP0H DP1L DP1H DP2 DP3 DP4 E E E E ODP2 ODP3 E E DP6 ODP6 E Figure 6-1 SFRs and Pins associated with the Parallel Ports Semiconductor Group 6-1 10Jul97@15:19h Parallel Ports / C161 In the C161 certain ports provide Open Drain Control, which allows to switch the output driver of a port pin from a push/pull configuration to an open drain configuration. In push/pull mode a port output driver has an upper and a lower transistor, thus it can actively drive the line either to a high or a low level. In open drain mode the upper transistor is always switched off, and the output driver can only actively drive the line to a low level. When writing a `1' to the port latch, the lower transistor is switched off and the output enters a high-impedance state. The high level must then be provided by an external pullup device. With this feature, it is possible to connect several port pins together to a Wired-AND configuration, saving external glue logic and/or additional software overhead for enabling/disabling output signals. This feature is implemented for ports P2, P3 and P6 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx. These registers allow the individual bitwise selection of the open drain mode for each port line. If the respective control bit ODPx.y is `0' (default after reset), the output driver is in the push/pull mode. If ODPx.y is `1', the open drain configuration is selected. Note that all ODPx registers are located in the ESFR space. Figure 6-2 Output Drivers in Push/Pull Mode and in Open Drain Mode Alternate Port Functions Each port line has one programmable alternate input or output function associated with it. PORT0 and PORT1 may be used as the address and data lines when accessing external memory. Port 4 outputs the additional segment address bits A21/19/17...A16 in systems where more than 64 KBytes of memory are to be accessed directly. Port 6 provides the optional chip select outputs. Port 2 is used for fast external interrupt inputs. Port 3 includes alternate input/output functions of timers, serial interfaces and the optional bus control signal BHE/WRH. Port 5 is used for timer control signals. Semiconductor Group 6-2 10Jul97@15:19h Parallel Ports / C161 If an alternate output function of a pin is to be used, the direction of this pin must be programmed for output (DPx.y=`1'), except for some signals that are used directly after reset and are configured automatically. Otherwise the pin remains in the high-impedance state and is not effected by the alternate output function. The respective port latch should hold a `1', because its output is ANDed with the alternate output data. If an alternate input function of a pin is used, the direction of the pin must be programmed for input (DPx.y=`0') if an external device is driving the pin. The input direction is the default after reset. If no external device is connected to the pin, however, one can also set the direction for this pin to output. In this case, the pin reflects the state of the port output latch. Thus, the alternate input function reads the value stored in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data. Obviously, this cannot be done through instructions. In these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled. To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output. There is one basic structure for all port lines with only an alternate input function. Port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode. All port lines that are not used for these alternate functions may be used as general purpose IO lines. When using port pins for general purpose output, the initial output value should be written to the port latch prior to enabling the output drivers, in order to avoid undesired transitions on the output pins. This applies to single pins as well as to pin groups (see examples below). SINGLE_BIT: BSET BSET P4.7 DP4.7 ; Initial output level is "high" ; Switch on the output driver ; Initial output level is "high" ; Switch on the output drivers BIT_GROUP: BFLDH P4, #24H, #24H BFLDH DP4, #24H, #24H Note: When using several BSET pairs to control more pins of one port, these pairs must be separated by instructions, which do not reference the respective port (see "Particular Pipeline Effects" in chapter "The Central Processing Unit"). Each of these ports and the alternate input and output functions are described in detail in the following subsections. Semiconductor Group 6-3 10Jul97@15:19h Parallel Ports / C161 6.1 PORT0 The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0, respectively. Both halfs of PORT0 can be written (eg. via a PEC transfer) without effecting the other half. If this port is used for general purpose IO, the direction of each line can be configured via the corresponding direction registers DP0H and DP0L. P0L (FF00H / 80H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: - - 00H 3 2 1 0 P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0 rw rw rw rw rw rw rw rw P0H (FF02H / 81H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: - - 00H 3 2 1 0 P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 rw rw rw rw rw rw rw rw Bit P0X.y Function Port data register P0H or P0L bit y DP0L (F100H / 80H) 15 14 13 12 11 10 9 ESFR 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 DP0L DP0L DP0L DP0L DP0L DP0L DP0L DP0L .0 .7 .6 .5 .4 .3 .2 .1 rw rw rw rw rw rw rw rw DP0H (F102H / 81H) 15 14 13 12 11 10 9 ESFR 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 DP0H DP0H DP0H DP0H DP0H DP0H DP0H DP0H .7 .6 .5 .4 .3 .2 .1 .0 rw rw rw rw rw rw rw rw Bit DP0X.y Function Port direction register DP0H or DP0L bit y DP0X.y = 0: Port line P0X.y is an input (high-impedance) DP0X.y = 1: Port line P0X.y is an output Semiconductor Group 6-4 10Jul97@15:19h Parallel Ports / C161 Alternate Functions of PORT0 When an external bus is enabled, PORT0 is used as data bus or address/data bus. Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for IO (provided that no other bus mode is enabled). PORT0 is also used to select the system startup configuration. During reset, PORT0 is configured to input, and each line is held high through an internal pullup device. Each line can now be individually pulled to a low level (see DC-level specifications in the respective Data Sheets) through an external pulldown device. A default configuration is selected when the respective PORT0 lines are at a high level. Through pulling individual lines to a low level, this default can be changed according to the needs of the applications. The internal pullup devices are designed such that an external pulldown resistors (see Data Sheet specification) can be used to apply a correct low level. These external pulldown resistors can remain connected to the PORT0 pins also during normal operation, however, care has to be taken such that they do not disturb the normal function of PORT0 (this might be the case, for example, if the external resistor is too strong). With the end of reset, the selected bus configuration will be written to the BUSCON0 register. The configuration of the high byte of PORT0, will be copied into the special register RP0H. This readonly register holds the selection for the number of chip selects and segment addresses. Software can read this register in order to react according to the selected configuration, if required. When the reset is terminated, the internal pullup devices are switched off, and PORT0 will be switched to the appropriate operating mode. During external accesses in multiplexed bus modes PORT0 first outputs the 16-bit intra-segment address as an alternate output function. PORT0 is then switched to high-impedance input mode to read the incoming instruction or data. In 8-bit data bus mode, two memory cycles are required for word accesses, the first for the low byte and the second for the high byte of the word. During write cycles PORT0 outputs the data byte or word after outputting the address. During external accesses in demultiplexed bus modes PORT0 reads the incoming instruction or data word or outputs the data byte or word. Alternate Function P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0 a) b) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit Demux Bus c) AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 8-bit MUX Bus d) AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 16-bit MUX Bus P0H PORT0 P0L D7 D6 D5 D4 D3 D2 D1 D0 8-bit Demux Bus General Purpose Input/Output Figure 6-3 PORT0 IO and Alternate Functions Semiconductor Group 6-5 10Jul97@15:19h Parallel Ports / C161 When an external bus mode is enabled, the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware. The input of the port output latch is disconnected from the internal bus and is switched to the line labeled "Alternate Data Output" via a multiplexer. The alternate data can be the 16-bit intrasegment address or the 8/16-bit data information. The incoming data on PORT0 is read on the line "Alternate Data Input". While an external bus mode is enabled, the user software should not write to the port output latch, otherwise unpredictable results may occur. When the external bus modes are disabled, the contents of the direction register last written by the user becomes active. The figure below shows the structure of a PORT0 pin. y = 7...0 Figure 6-4 Block Diagram of a PORT0 Pin Semiconductor Group 6-6 10Jul97@15:19h Parallel Ports / C161 6.2 PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halfs of PORT1 can be written (eg. via a PEC transfer) without effecting the other half. If this port is used for general purpose IO, the direction of each line can be configured via the corresponding direction registers DP1H and DP1L. P1L (FF04H / 82H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: - - 00H 3 2 1 0 P1L.7 P1L.6 P1L.5 P1L.4 P1L.3 P1L.2 P1L.1 P1L.0 rw rw rw rw rw rw rw rw P1H (FF06H / 83H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: - - 00H 3 2 1 0 P1H.7 P1H.6 P1H.5 P1H.4 P1H.3 P1H.2 P1H.1 P1H.0 rw rw rw rw rw rw rw rw Bit P1X.y Function Port data register P1H or P1L bit y DP1L (F104H / 82H) 15 14 13 12 11 10 9 ESFR 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 DP1L DP1L DP1L DP1L DP1L DP1L DP1L DP1L .7 .6 .5 .4 .3 .2 .1 .0 rw rw rw rw rw rw rw rw DP1H (F106H / 83H) 15 14 13 12 11 10 9 ESFR 8 7 6 5 4 Reset Value: - - 00H 3 2 1 0 DP1H DP1H DP1H DP1H DP1H DP1H DP1H DP1H .7 .6 .5 .4 .3 .2 .1 .0 rw rw rw rw rw rw rw rw Bit DP1X.y Function Port direction register DP1H or DP1L bit y DP1X.y = 0: Port line P1X.y is an input (high-impedance) DP1X.y = 1: Port line P1X.y is an output Semiconductor Group 6-7 10Jul97@15:19h Parallel Ports / C161 Alternate Functions of PORT1 When a demultiplexed external bus is enabled, PORT1 is used as address bus. Note that demultiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port lines can be used for general purpose IO. During external accesses in demultiplexed bus modes PORT1 outputs the 16-bit intra-segment address as an alternate output function. During external accesses in multiplexed bus modes, when no BUSCON register selects a demultiplexed bus mode, PORT1 is not used and is available for general purpose IO. Alternate Function P1H.7 P1H.6 P1H.5 P1H.4 P1H.3 P1H.2 P1H.1 P1H.0 P1L.7 P1L.6 P1L.5 P1L.4 P1L.3 P1L.2 P1L.1 P1L.0 a) A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 8/16-bit Demux Bus P1H PORT1 P1L General Purpose Input/Output Figure 6-5 PORT1 IO and Alternate Functions Note: Demultiplexed bus modes are only available on the C161K and C161O. When an external bus mode is enabled, the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware. The input of the port output latch is disconnected from the internal bus and is switched to the line labeled "Alternate Data Output" via a multiplexer. The alternate data is the 16-bit intrasegment address. While an external bus mode is enabled, the user software should not write to the port output latch, otherwise unpredictable results may occur. When the external bus modes are disabled, the contents of the direction register last written by the user becomes active. Semiconductor Group 6-8 10Jul97@15:19h Parallel Ports / C161 The figure below shows the structure of a PORT1 pin. y = 7...0 Figure 6-6 Block Diagram of a PORT1 Pin Semiconductor Group 6-9 10Jul97@15:19h Parallel Ports / C161 6.3 Port 2 In the C161 Port 2 is a 7-bit port. If Port 2 is used for general purpose IO, the direction of each line can be configured via the corresponding direction register DP2. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP2. P2 (FFC0H / E0H) 15 14 13 12 11 10 9 8 - SFR 7 6 5 4 Reset Value: 00 - -H 3 2 1 0 P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 rw rw rw rw rw rw rw Bit P2.y Function Port data register P2 bit y DP2 (FFC2H / E1H) 15 DP2 .15 rw 14 DP2 .14 rw 13 DP2 .13 rw 12 DP2 .12 rw 11 DP2 .11 rw 10 DP2 .10 rw 9 DP2 .9 rw 8 - SFR 7 6 5 4 Reset Value: 00 - -H 3 2 1 0 - - - - - - - - Bit DP2.y Function Port direction register DP2 bit y DP2.y = 0: Port line P2.y is an input (high-impedance) DP2.y = 1: Port line P2.y is an output ODP2 (F1C2H / E1H) 15 14 13 12 11 10 9 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 .15 .14 .13 .12 .11 .10 .9 rw rw rw rw rw rw rw ESFR 8 7 6 5 4 Reset Value: 00 - -H 3 2 1 0 - - - - Bit ODP2.y Function Port 2 Open Drain control register bit y ODP2.y = 0: Port line P2.y output driver in push/pull mode ODP2.y = 1: Port line P2.y output driver in open drain mode Semiconductor Group 6-10 10Jul97@15:19h Parallel Ports / C161 Alternate Functions of Port 2 All Port 2 lines (P2.15...P2.9) can serve as Fast External Interrupt inputs (EX7IN...EX1IN). Note: EX7IN...EX5IN on P2.15...P2.13 are only available on the C161O. The table below summarizes the alternate functions of Port 2. Port 2 Pin P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 Alternate Function EX1IN EX2IN EX3IN EX4IN EX5IN EX6IN EX7IN Fast External Interrupt 1 Input Fast External Interrupt 2 Input Fast External Interrupt 3 Input Fast External Interrupt 4 Input Fast External Interrupt 5 Input Fast External Interrupt 6 Input Fast External Interrupt 7 Input Alternate Function P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 - a) Port 2 EX7IN EX6IN EX5IN EX4IN EX3IN EX2IN EX1IN Fast External Interrupt Input General Purpose Input/Output Figure 6-7 Port 2 IO and Alternate Functions Semiconductor Group 6-11 10Jul97@15:19h Parallel Ports / C161 y = 15...8 Figure 6-8 Block Diagram of a Port 2 Pin Semiconductor Group 6-12 10Jul97@15:19h Parallel Ports / C161 6.4 Port 3 If this 12-bit port is used for general purpose IO, the direction of each line can be configured via the corresponding direction register DP3. Most port lines can be switched into push/pull or open drain mode via the open drain control register ODP2 (pin P3.12 does not support open drain mode!). P3 (FFC4H / E2H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: 0000H 3 2 1 0 - P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 rw rw rw rw rw rw rw rw rw rw rw rw Bit P3.y Function Port data register P3 bit y DP3 (FFC6H / E3H) 15 14 13 DP3 .13 rw 12 DP3 .12 rw 11 DP3 .11 rw 10 DP3 .10 rw 9 DP3 .9 rw 8 SFR 7 DP3 .7 rw 6 DP3 .6 rw 5 DP3 .5 rw 4 DP3 .4 rw Reset Value: 0000H 3 DP3 .3 rw 2 DP3 .2 rw 1 0 - DP3 .8 rw Bit DP3.y Function Port direction register DP3 bit y DP3.y = 0: Port line P3.y is an input (high-impedance) DP3.y = 1: Port line P3.y is an output ESFR 11 10 9 8 7 6 5 4 ODP3 (F1C6H / E3H) 15 14 13 ODP3 .13 rw 12 - Reset Value: 0000H 3 2 1 0 - ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 .11 .10 .9 .8 .7 .6 .5 .4 .3 .2 rw rw rw rw rw rw rw rw rw rw Bit ODP3.y Function Port 3 Open Drain control register bit y ODP3.y = 0: Port line P3.y output driver in push/pull mode ODP3.y = 1: Port line P3.y output driver in open drain mode Semiconductor Group 6-13 10Jul97@15:19h Parallel Ports / C161 Alternate Functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines, the two serial interfaces and the control lines BHE and CLKOUT. The table below summarizes the alternate functions of Port 3. Port 3 Pin P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 Alternate Function CAPIN T3OUT T3EUD T4IN T3IN T2IN MRST MTSR TxD0 RxD0 BHE/WRH SCLK GPT2 Capture Input Timer 3 Toggle Output Timer 3 External Up/Down Control Input Timer 4 Count Input Timer 3 Count Input Timer 2 Count Input SSC Master Receive / Slave Transmit SSC Master Transmit / Slave Receive ASC0 Transmit Data Output ASC0 Receive Data Input Byte High Enable / Write High Output SSC Shift Clock Input/Output Alternate Function No Pin P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 - a) b) Port 3 SCLK BHE RxD0 TxD0 MTSR *) MRST *) T2IN T3IN T4IN T3EUD T3OUT CAPIN WRH General Purpose Input/Output Figure 6-9 Port 3 IO and Alternate Functions Note: The alternate functions of P3.13...P3.8 are available on all derivatives. The alternate functions of P3.7...P3.3 are only available on the C161K and the C161O. The alternate function of P3.2 is only available on the C161O. Semiconductor Group 6-14 10Jul97@15:19h Parallel Ports / C161 The port structure of the Port 3 pins depends on their alternate function (see figures below). When the on-chip peripheral associated with a Port 3 pin is configured to use the alternate input function, it reads the input latch, which represents the state of the pin, via the line labeled "Alternate Data Input". Port 3 pins with alternate input functions are: T2IN, T3IN, T4IN, T3EUD and CAPIN (where implemented). When the on-chip peripheral associated with a Port 3 pin is configured to use the alternate output function, its "Alternate Data Output" line is ANDed with the port output latch line. When using these alternate functions, the user must set the direction of the port line to output (DP3.y=1) and must set the port output latch (P3.y=1). Otherwise the pin is in its high-impedance state (when configured as input) or the pin is stuck at '0' (when the port output latch is cleared). When the alternate output functions are not used, the "Alternate Data Output" line is in its inactive state, which is a high level ('1'). Port 3 pins with alternate output functions are: T3OUT and TxD0. When the on-chip peripheral associated with a Port 3 pin is configured to use both the alternate input and output function, the descriptions above apply to the respective current operating mode. The direction must be set accordingly. Port 3 pins with alternate input/output functions are: MTSR, MRST, RxD0 and SCLK. Semiconductor Group 6-15 10Jul97@15:19h Parallel Ports / C161 y = 13, 11...0 Figure 6-10 Block Diagram of a Port 3 Pin with Alternate Input or Alternate Output Function Semiconductor Group 6-16 10Jul97@15:19h Parallel Ports / C161 Pin P3.12 (BHE/WRH) is one more pin with an alternate output function. However, its structure is slightly different (see figure below), because after reset the BHE or WRH function must be used depending on the system startup configuration. In these cases there is no possibility to program any port latches before. Thus the apprppriate alternate function is selected automatically. If BHE/WRH is not used in the system, this pin can be used for general purpose IO by disabling the alternate function (BYTDIS = `1' / WRCFG='0'). x = 15, 12 Figure 6-11 Block Diagram of Pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) Note: Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit DP3.12='1' is not required. During bus hold pin P3.12 is switched back to its standard function and is then controlled by DP3.12 and P3.12. Keep DP3.12 = '0' in this case to ensure floating in hold mode. Semiconductor Group 6-17 10Jul97@15:19h Parallel Ports / C161 6.5 Port 4 If this 6-bit port is used for general purpose IO, the direction of each line can be configured via the corresponding direction register DP4. P4 (FFC8H / E4H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: - - 00H 3 2 1 0 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 rw rw rw rw rw rw - - - - - - - - - Bit P4.y Function Port data register P4 bit y DP4 (FFCAH / E5H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: - - 00H 3 2 1 0 DP4.5 DP4.4 DP4.3 DP4.2 DP4.1 DP4.0 rw rw rw rw rw rw - - - - - - - - - Bit DP4.y Function Port direction register DP4 bit y DP4.y = 0: Port line P4.y is an input (high-impedance) DP4.y = 1: Port line P4.y is an output Alternate Functions of Port 4 During external bus cycles that use segmentation (ie. an address space above 64 KByte) a number of Port 4 pins may output the segment address lines. The number of pins that is used for segment address output determines the external address space which is directly accessible. The other pins of Port 4 (if any) may be used for general purpose IO. If segment address lines are selected, the alternate function of Port 4 may be necessary to access eg. external memory directly after reset. For this reason Port 4 will be switched to its alternate function automatically. The number of segment address lines is selected via PORT0 during reset. The selected value can be read from bitfield SALSEL in register RP0H (read only) eg. in order to check the configuration during run time. The table below summarizes the alternate functions of Port 4 depending on the number of selected segment address lines (coded via bitfield SALSEL). Semiconductor Group 6-18 10Jul97@15:19h Parallel Ports / C161 Port 4 Pin P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 Std. Function Altern. Function Altern. Function Altern. Function SALSEL=01 64 KB SALSEL=11 256KB SALSEL=00 1 MB SALSEL=10 4 MB Gen. purpose IO Gen. purpose IO Gen. purpose IO Gen. purpose IO Gen. purpose IO Gen. purpose IO Seg. Address A16 Seg. Address A17 Gen. purpose IO Gen. purpose IO Gen. purpose IO Gen. purpose IO Seg. Address A16 Seg. Address A17 Seg. Address A18 Seg. Address A19 Gen. purpose IO Gen. purpose IO Seg. Address A16 Seg. Address A17 Seg. Address A18 Seg. Address A19 Seg. Address A20 Seg. Address A21 Alternate Function P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 a) A21 A20 A19 A18 A17 A16 Port 4 General Purpose Input/Output Figure 6-12 Port 4 IO and Alternate Functions Semiconductor Group 6-19 10Jul97@15:19h Parallel Ports / C161 y = 7...0 Figure 6-13 Block Diagram of a Port 4 Pin Semiconductor Group 6-20 10Jul97@15:19h Parallel Ports / C161 6.6 Port 5 This 2-bit input port can only read data. There is no output latch and no direction register. Data written to P5 will be lost. P5 (FFA2H / D1H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: X - - -H 3 2 1 0 P5.15 P5.14 r r - Bit P5.y Function Port data register P5 bit y (Read only) Alternate Functions of Port 5 Each line of Port 5 serves as external timer control line for GPT1. The table below summarizes the alternate functions of Port 5. Port 5 Pin P5.14 P5.15 Alternate Function T4EUD T2EUD Timer 4 external Up/Down Control Input Timer 2 external Up/Down Control Input Alternate Function P5.15 P5.14 - a) T2EUD T4EUD - Port 5 General Purpose Input Figure 6-14 Port 5 IO and Alternate Functions Note: The alternate functions of P5.15...P5.14 are only available on the C161K and the C161O. Semiconductor Group 6-21 10Jul97@15:19h Parallel Ports / C161 Port 5 pins have a special port structure (see figure below), because it is an input only port. y = 15...10 Figure 6-15 Block Diagram of a Port 5 Pin Semiconductor Group 6-22 10Jul97@15:19h Parallel Ports / C161 6.7 Port 6 If this 4-bit port is used for general purpose IO, the direction of each line can be configured via the corresponding direction register DP6. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP6. P6 (FFCCH / E6H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 - Reset Value: - - - 0H 3 2 1 0 P6.3 P6.2 P6.1 P6.0 rw rw rw rw - - - - - - - - - Bit P6.y Function Port data register P6 bit y DP6 (FFCEH / E7H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 - Reset Value: - - - 0H 3 2 1 0 DP6.3 DP6.2 DP6.1 DP6.0 rw rw rw rw - - - - - - - - - Bit DP6.y Function Port direction register DP6 bit y DP6.y = 0: Port line P6.y is an input (high-impedance) DP6.y = 1: Port line P6.y is an output ODP6 (F1CEH / E7H) 15 14 13 12 11 10 9 ESFR 8 7 6 5 4 - Reset Value: - - - 0H 3 2 1 0 ODP6 ODP6 ODP6 ODP6 .3 .2 .1 .0 rw rw rw rw - - - - - - - - - Bit ODP6.y Function Port 6 Open Drain control register bit y ODP6.y = 0: Port line P6.y output driver in push/pull mode ODP6.y = 1: Port line P6.y output driver in open drain mode Semiconductor Group 6-23 10Jul97@15:19h Parallel Ports / C161 Alternate Functions of Port 6 A programmable number of chip select signals (CS3...CS0) derived from the bus control registers (BUSCON3...BUSCON0) can be output on the 4 pins of Port 6. The number of chip select signals is selected via PORT0 during reset. The selected value can be read from bitfield CSSEL in register RP0H (read only) eg. in order to check the configuration during run time. The table below summarizes the alternate functions of Port 6 depending on the number of selected chip select lines (coded via bitfield CSSEL). Port 6 Pin P6.0 P6.1 P6.2 P6.3 Altern. Function CSSEL = 10 Gen. purpose IO Gen. purpose IO Gen. purpose IO Gen. purpose IO Altern. Function CSSEL = 01 Chip select CS0 Chip select CS1 Gen. purpose IO Gen. purpose IO Altern. Function CSSEL = 00 Chip select CS0 Chip select CS1 Chip select CS2 Gen. purpose IO Altern. Function CSSEL = 11 Chip select Chip select Chip select Chip select CS0 CS1 CS2 CS3 Alternate Function P6.3 P6.2 P6.1 P6.0 a) CS3 CS2 CS1 CS0 Port 6 General Purpose Input/Output Figure 6-16 Port 6 IO and Alternate Functions The chip select lines of Port 6 additionally have an internal weak pullup device. This device is switched on during reset. After reset the CS function must be used, if selected so. In this case there is no possibility to program any port latches before. Thus the alternate function (CS) is selected automatically in this case. Note: The open drain output option can only be selected via software earliest during the initialization routine; at least signal CS0 will be in push/pull output driver mode directly after reset. Semiconductor Group 6-24 10Jul97@15:19h Parallel Ports / C161 Figure 6-17 Block Diagram of Port 6 Pins with an alternate output function Semiconductor Group 6-25 10Jul97@15:19h Dedicated Pins / C161 7 Dedicated Pins Most of the input/output or control signals of the functional the C161 are realized as alternate functions of pins of the parallel ports. There is, however, a number of signals that use separate pins, including the oscillator, special control signals and, of course, the power supply. The table below summarizes the 17 dedicated pins of the C161. Pin(s) ALE RD WR/WRL EA NMI RSTIN RSTOUT XTAL1, XTAL2 VCC, VSS Function Address Latch Enable External Read Strobe External Write/Write Low Strobe External Access Enable Non-Maskable Interrupt Input Reset Input Reset Output Oscillator Input/Output Digital Power Supply and Ground (4 pins each) The Address Latch Enable signal ALE controls external address latches that provide a stable address in multiplexed bus modes. ALE is activated for every external bus cycle independent of the selected bus mode, ie. it is also activated for bus cycles with a demultiplexed address bus. When an external bus is enabled (one or more of the BUSACT bits set) also X-Peripheral accesses will generate an active ALE signal. ALE is not activated for internal accesses, ie. accesses to ROM/Flash (if provided), the internal RAM and the special function registers. In single chip mode, ie. when no external bus is enabled (no BUSACT bit set), ALE will also remain inactive for X-Peripheral accesses. The External Read Strobe RD controls the output drivers of external memory or peripherals when the C161 reads data from these external devices. During reset and during Hold mode an internal pullup ensures an inactive (high) level on the RD output. During accesses to on-chip X-Peripherals RD remains inactive (high). The External Write Strobe WR/WRL controls the data transfer from the C161 to an external memory or peripheral device. This pin may either provide an general WR signal activated for both byte and word write accesses, or specifically control the low byte of an external 16-bit device (WRL) together with the signal WRH (alternate function of P3.12/BHE). During reset and during Hold mode an internal pullup ensures an inactive (high) level on the WR/WRL output. During accesses to onchip X-Peripherals WR/WRL remains inactive (high). Semiconductor Group 7-1 10Jul97@15:19h Dedicated Pins / C161 The External Access Enable Pin EA determines, if the C161 after reset starts fetching code from the internal ROM area (EA='1') or via the external bus interface (EA='0'). Be sure to hold this input high for ROMless devices. The Non-Maskable Interrupt Input NMI allows to trigger a high priority trap via an external signal (eg. a power-fail signal). It also serves to validate the PWRDN instruction that switches the C161 into Power-Down mode. The NMI pin is sampled with every CPU clock cycle to detect transitions. The Oscillator Input XTAL1 and Output XTAL2 connect the internal Pierce oscillator to the external crystal. The oscillator provides an inverter and a feedback element. The standard external oscillator circuitry (see figure below) comprises the crystal, two low end capacitors and series resistor to limit the current through the crystal. The additional LC combination is only required for 3rd overtone crystals to suppress oscillation in the fundamental mode. A test resistor (R Q) may be temporarily inserted to measure the oscillation allowance of the oscillator circuitry. An external clock signal may be fed to the input XTAL1, leaving XTAL2 open. Note: It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Figure 7-1 External Oscillator Circuitry The Reset Input RSTIN allows to put the C161 into the well defined reset condition either at powerup or external events like a hardware failure or manual reset. The input voltage threshold of the RSTIN pin is raised compared to the standard pins in order to minimize the noise sensitivity of the reset input. The Reset Output RSTOUT provides a special reset signal for external circuitry. RSTOUT is activated at the beginning of the reset sequence, triggered via RSTIN, a watchdog timer overflow or by the SRST instruction. RSTOUT remains active (low) until the EINIT instruction is executed. This allows to initialize the controller before the external circuitry is activated. Semiconductor Group 7-2 10Jul97@15:19h Dedicated Pins / C161 The Power Supply pins VCC and VSS provide the power supply for the digital logic of the C161. The respective VCC/VSS pairs should be decoupled as close to the pins as possible. For best results it is recommended to implement two-level decoupling, eg. (the widely used) 100 nF in parallel with 30...40 pF capacitors which deliver the peak currents. Note: All VCC pins and all VSS pins must be connected to the power supply and ground, respectively. Semiconductor Group 7-3 10Jul97@15:19h The External Bus Interface / C161 8 The External Bus Interface Although the C161 provides a powerful set of on-chip peripherals and on-chip RAM and ROM (except for ROMless versions) areas, these internal units only cover a small fraction of its address space of up to 16 MByte. The external bus interface allows to access external peripherals and additional volatile and non-volatile memory (up to 4 MByte). The external bus interface provides a number of configurations, so it can be taylored to fit perfectly into a given application system. Ports & Direction Control Alternate Functions Address Registers Mode Registers Control Registers P0L / P0H P1L / P1H DP3 P3 P4 ODP6 DP6 P6 E ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 PORT0 PORT1 ALE RD WR/WRL BHE/WRH EA RSTIN BUSCON0 BUSCON1 BUSCON2 BUSCON3 BUSCON4 SYSCON RP0H P0L/P0H P1L/P1H DP3 P3 P4 ODP6 DP6 P6 PORT0 Data Registers PORT1 Data Registers Port 3 Direction Control Register Port 3 Data Register Port 4 Data Register Port 6 Open Drain Control Register Port 6 Direction Control Register Port 6 Data Register ADDRSELx BUSCONx SYSCON RP0H Address Range Select Register 1...4 Bus Mode Control Register 0...4 System Control Register Port P0H Reset Configuration Register Control Registers Figure 8-1 SFRs and Port Pins Associated with the External Bus Interface Accesses to external memory or peripherals are executed by the integrated External Bus Controller (EBC). The function of the EBC is controlled via the SYSCON register and the BUSCONx and ADDRSELx registers. The BUSCONx registers specify the external bus cycles in terms of address (mux/demux), data (16-bit/8-bit), chip selects and length (waitstates / ALE / RW delay). These parameters are used for accesses within a specific address area which is defined via the corresponding register ADDRSELx. The four pairs BUSCON1/ADDRSEL1...BUSCON4/ADDRSEL4 allow to define four independent "address windows", while all external accesses outside these windows are controlled via register BUSCON0. Semiconductor Group 8-1 10Jul97@15:19h The External Bus Interface / C161 Single Chip Mode Single chip mode is entered, when pin EA is high during reset. In this case register BUSCON0 is initialized with 0000H, which also resets bit BUSACT0, so no external bus is enabled. In single chip mode the C161 operates only with and out of internal resources. No external bus is configured and no external peripherals and/or memory can be accessed. Also no port lines are occupied for the bus interface. When running in single chip mode, however, external access may be enabled by configuring an external bus under software control. Single chip mode allows the C161 to start execution out of the internal program memory (Mask-ROM or Flash memory). Note: Any attempt to access a location in the external memory space in single chip mode results in the hardware trap ILLBUS. 8.1 External Bus Modes When the external bus interface is enabled (bit BUSACTx='1') and configured (bitfield BTYP), the C161 uses a subset of its port lines together with some control lines to build the external bus. BTYP Encoding 00 01 10 11 *) External Data Bus Width 8-bit Data 8-bit Data 16-bit Data 16-bit Data External Address Bus Mode Demultiplexed Addresses Multiplexed Addresses Demultiplexed Addresses Multiplexed Addresses *) *) C161O only. The bus configuration (BTYP) for the address windows (BUSCON4...BUSCON1) is selected via software typically during the initialization of the system. The bus configuration (BTYP) for the default address range (BUSCON0) is selected via PORT0 during reset, provided that pin EA is low during reset. Otherwise BUSCON0 may be programmed via software just like the other BUSCON registers. The 16 MByte address space of the C161 is divided into 256 segments of 64 KByte each. 64 of these segments (4 MByte) may be mapped to the external bus. The 16-bit intra-segment address is output on PORT0 for multiplexed bus modes or on PORT1 for demultiplexed bus modes. When segmentation is disabled, only one 64 KByte segment can be used and accessed. Otherwise additional address lines may be output on Port 4, and/or several chip select lines may be used to select different memory banks or peripherals. These functions are selected during reset via bitfields SALSEL and CSSEL of register RP0H, respectively. Note: Bit SGTDIS of register SYSCON defines, if the CSP register is saved during interrupt entry (segmentation active) or not (segmentation disabled). Semiconductor Group 8-2 10Jul97@15:19h The External Bus Interface / C161 Multiplexed Bus Modes In the multiplexed bus modes the 16-bit intra-segment address as well as the data use PORT0. The address is time-multiplexed with the data and has to be latched externally. The width of the required latch depends on the selected data bus width, ie. an 8-bit data bus requires a byte latch (the address bits A15...A8 on P0H do not change, while P0L multiplexes address and data), a 16-bit data bus requires a word latch (the least significant address line A0 is not relevant for word accesses). The upper address lines (An...A16) are permanently output on Port 4 (if segmentation is enabled) and do not require latches. The EBC initiates an external access by generating the Address Latch Enable signal (ALE) and then placing an address on the bus. The falling edge of ALE triggers an external latch to capture the address. After a period of time during which the address must have been latched externally, the address is removed from the bus. The EBC now activates the respective command signal (RD, WR, WRL, WRH). Data is driven onto the bus either by the EBC (for write cycles) or by the external memory/peripheral (for read cycles). After a period of time, which is determined by the access time of the memory/peripheral, data become valid. Read cycles: Input data is latched and the command signal is now deactivated. This causes the accessed device to remove its data from the bus which is then tri-stated again. Write cycles: The command signal is now deactivated. The data remain valid on the bus until the next external bus cycle is started. Figure 8-2 Multiplexed Bus Cycle Semiconductor Group 8-3 10Jul97@15:19h The External Bus Interface / C161 Demultiplexed Bus Modes In the demultiplexed bus modes the 16-bit intra-segment address is permanently output on PORT1, while the data uses PORT0 (16-bit data) or P0L (8-bit data). The upper address lines are permanently output on Port 4 (if selected via SALSEL during reset). No address latches are required. The EBC initiates an external access by placing an address on the address bus. After a programmable period of time the EBC activates the respective command signal (RD, WR, WRL, WRH). Data is driven onto the data bus either by the EBC (for write cycles) or by the external memory/peripheral (for read cycles). After a period of time, which is determined by the access time of the memory/peripheral, data become valid. Read cycles: Input data is latched and the command signal is now deactivated. This causes the accessed device to remove its data from the data bus which is then tri-stated again. Write cycles: The command signal is now deactivated. If a subsequent external bus cycle is required, the EBC places the respective address on the address bus. The data remain valid on the bus until the next external bus cycle is started. Figure 8-3 Demultiplexed Bus Cycle Note: Demultiplexed bus modes are only provided on the C161O. Semiconductor Group 8-4 10Jul97@15:19h The External Bus Interface / C161 Switching between the Bus Modes The EBC allows to switch between different bus modes dynamically, ie. subsequent external bus cycles may be executed in different ways. Certain address areas may use multiplexed or demultiplexed buses or use predefined waitstates. A change of the external bus characteristics can be initiated in two different ways: Reprogramming the BUSCON and/or ADDRSEL registers allows to either change the bus mode for a given address window, or change the size of an address window that uses a certain bus mode. Reprogramming allows to use a great number of different address windows (more than BUSCONs are available) on the expense of the overhead for changing the registers and keeping appropriate tables. Switching between predefined address windows automatically selects the bus mode that is associated with the respective window. Predefined address windows allow to use different bus modes without any overhead, but restrict their number to the number of BUSCONs. However, as BUSCON0 controls all address areas, which are not covered by the other BUSCONs, this allows to have gaps between these windows, which use the bus mode of BUSCON0. PORT1 will output the intra-segment address, when any of the BUSCON registers selects a demultiplexed bus mode, even if the current bus cycle uses a multiplexed bus mode. This allows to have an external address decoder connected to PORT1 only, while using it for all kinds of bus cycles. Note: Never change the configuration for an address area that currently supplies the instruction stream. Due to the internal pipelining it is very difficult to determine the first instruction fetch that will use the new configuration. Only change the configuration for address areas that are not currently accessed. This applies to BUSCON registers as well as to ADDRSEL registers. The usage of the BUSCON/ADDRSEL registers is controlled via the issued addresses. When an access (code fetch or data) is initiated, the respective generated physical address defines, if the access is made internally, uses one of the address windows defined by ADDRSEL4...1, or uses the default configuration in BUSCON0. After initializing the active registers, they are selected and evaluated automatically by interpreting the physical address. No additional switching or selecting is necessary during run time, except when more than the four address windows plus the default is to be used. Switching from demultiplexed to multiplexed bus mode represents a special case. The bus cycle is started by activating ALE and driving the address to Port 4 and PORT1 as usual, if another BUSCON register selects a demultiplexed bus. However, in the multiplexed bus modes the address is also required on PORT0. In this special case the address on PORT0 is delayed by one CPU clock cycle, which delays the complete (multiplexed) bus cycle and extends the corresponding ALE signal (see figure below). This extra time is required to allow the previously selected device (via demultiplexed bus) to release the data bus, which would be available in a demultiplexed bus cycle. Semiconductor Group 8-5 10Jul97@15:19h The External Bus Interface / C161 Figure 8-4 Switching from Demultiplexed to Multiplexed Bus Mode Semiconductor Group 8-6 10Jul97@15:19h The External Bus Interface / C161 External Data Bus Width The EBC can operate on 8-bit or 16-bit wide external memory/peripherals. A 16-bit data bus uses PORT0, while an 8-bit data bus only uses P0L, the lower byte of PORT0. This saves on address latches, bus transceivers, bus routing and memory cost on the expense of transfer time. The EBC can control word accesses on an 8-bit data bus as well as byte accesses on a 16-bit data bus. Word accesses on an 8-bit data bus are automatically split into two subsequent byte accesses, where the low byte is accessed first, then the high byte. The assembly of bytes to words and the disassembly of words into bytes is handled by the EBC and is transparent to the CPU and the programmer. Byte accesses on a 16-bit data bus require that the upper and lower half of the memory can be accessed individually. In this case the upper byte is selected with the BHE signal, while the lower byte is selected with the A0 signal. So the two bytes of the memory can be enabled independent from each other, or together when accessing words. When writing bytes to an external 16-bit device, which has a single CS input, but two WR enable inputs (for the two bytes), the EBC can directly generate these two write control signals. This saves the external combination of the WR signal with A0 or BHE. In this case pin WR serves as WRL (write low byte) and pin BHE serves as WRH (write high byte). Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE. The respective byte will be written on both data bus halfs. When reading bytes from an external 16-bit device, whole words may be read and the C161 automatically selects the byte to be input and discards the other. However, care must be taken when reading devices that change state when being read, like FIFOs, interrupt status registers, etc. In this case individual bytes should be selected using BHE and A0. Bus Mode 8-bit Multiplexed 8-bit Demultipl. 16-bit Multiplexed 16-bit Demultipl. Transfer Rate (Speed factor for byte/word/dword access) Very low Low High Very high ( 1.5 / 3 / 6 ) (1/2/4) ( 1.5 / 1.5 / 3 ) (1/1/2) System Requirements Low (8-bit latch, byte bus) Free IO Lines P1H, P1L Very low (no latch, byte bus) P0H High (16-bit latch, word bus) P1H, P1L Low (no latch, word bus) --- Note: PORT1 gets available for general purpose IO, when none of the BUSCON registers selects a demultiplexed bus mode (where available). Disable/Enable Control for Pin BHE (BYTDIS) Bit BYTDIS is provided for controlling the active low Byte High Enable (BHE) pin. The function of the BHE pin is enabled, if the BYTDIS bit contains a '0'. Otherwise, it is disabled and the pin can be used as standard IO pin. The BHE pin is implicitly used by the External Bus Controller to select one of two byte-organized memory chips, which are connected to the C161 via a word-wide external data bus. After reset the BHE function is automatically enabled (BYTDIS = '0'), if a 16-bit data bus is selected during reset, otherwise it is disabled (BYTDIS='1'). It may be disabled, if byte access to 16-bit memory is not required, and the BHE signal is not used. Semiconductor Group 8-7 10Jul97@15:19h The External Bus Interface / C161 Segment Address Generation During external accesses the EBC generates a (programmable) number of address lines on Port 4, which extend the 16-bit address output on PORT0 or PORT1, and so increase the accessible address space. The number of segment address lines is selected during reset and coded in bit field SALSEL in register RP0H (see table below). SALSEL 11 10 01 00 Segment Address Lines Two: Six: None Four: A19...A16 A17...A16 A21...A16 Directly accessible Address Space 256 4 64 1 KByte (Default without pull-downs) MByte (Maximum) KByte (Minimum) MByte Note: The total accessible address space may be increased by accessing several banks which are distinguished by individual chip select signals. CS Signal Generation During external accesses the EBC can generate a (programmable) number of CS lines on Port 6, which allow to directly select external peripherals or memory banks without requiring an external decoder. The number of CS lines is selected during reset and coded in bit field CSSEL in register RP0H (see table below). CSSEL 11 10 01 00 Chip Select Lines Four: None Two: Three: CS1...CS0 CS2...CS0 CS3...CS0 Note Default without pull-downs Port 6 pins free for IO The CSx outputs are associated with the BUSCONx registers and are driven active (low) for any access within the address area defined for the respective BUSCON register. For any access outside this defined address area the respective CSx signal will go inactive (high). At the beginning of each external bus cycle the corresponding valid CS signal is determined and activated. All other CS lines are deactivated (driven high) at the same time. Note: The CSx signals will not be updated for an access to any internal address area (ie. when no external bus cycle is started), even if this area is covered by the respective ADDRSELx register. An access to an on-chip X-Peripheral deactivates all external CS signals. Upon accesses to address windows without a selected CS line all selected CS lines are deactivated. The CSx signals are not available on the C161V. Semiconductor Group 8-8 10Jul97@15:19h The External Bus Interface / C161 The chip select signals allow to be operated in four different modes, which are selected via bits CSWENx and CSRENx in the respective BUSCONx register. CSWENx CSRENx 0 0 1 1 0 1 0 1 Chip Select Mode Address Chip Select (Default after Reset, mode for CS0) Read Chip Select Write Chip Select Read/Write Chip Select Address Chip Select signals remain active until an access to another address window. An address chip select becomes active with the falling edge of ALE and becomes inactive with the falling edge of ALE of an external bus cycle that accesses a different address area. No spikes will be generated on the chip select lines. Read or Write Chip Select signals remain active only as long as the associated control signal (RD or WR) is active. This also includes the programmable read/write delay. Read chip select is only activated for read cycles, write chip select is only activated for write cycles, read/write chip select is activated for both read and write cycles (write cycles are assumed, if any of the signals WRH or WRL gets active). These modes save external glue logic, when accessing external devices like latches or drivers that only provide a single enable input. Note: CS0 provides an address chip select directly after reset (except for single chip mode) when the first instruction is fetched. Internal pullup devices hold all CS lines high during reset. After the end of a reset sequence the pullup devices are switched off and the pin drivers control the pin levels on the selected CS lines. Not selected CS lines will enter the high-impedance state and are available for general purpose IO. Segment Address versus Chip Select The external bus interface of the C161 supports many configurations for the external memory. By increasing the number of segment address lines the C161 can address a linear address space of 256 KByte, 1 MByte or 4 MByte. This allows to implement a large sequential memory area, and also allows to access a great number of external devices, using an external decoder. By increasing the number of CS lines the C161 can access memory banks or peripherals without external glue logic. These two features may be combined to optimize the overall system performance. Enabling 4 segment address lines and 5 chip select lines eg. allows to access five memory banks of 1 MByte each. So the available address space is 5 MByte (without glue logic). Note: Bit SGTDIS of register SYSCON defines, if the CSP register is saved during interrupt entry (segmentation active) or not (segmentation disabled). Semiconductor Group 8-9 10Jul97@15:19h The External Bus Interface / C161 8.2 Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user programmable to allow to adapt it to a wide range of different external bus and memory configurations with different types of memories and/or peripherals. The following parameters of an external bus cycle are programmable: * ALE Control defines the ALE signal length and the address hold time after its falling edge * Memory Cycle Time (extendable with 1...15 waitstates) defines the allowable access time * Memory Tri-State Time (extendable with 1 waitstate) defines the time for a data driver to float * Read/Write Delay Time defines when a command is activated after the falling edge of ALE Note: Internal accesses are executed with maximum speed and therefore are not programmable. External acceses use the slowest possible bus cycle after reset. The bus cycle timing may then be optimized by the initialization software. ALECTL Figure 8-5 Programmable External Bus Cycle MCTC MTTC Semiconductor Group 8-10 10Jul97@15:19h The External Bus Interface / C161 ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bits in the BUSCON registers. When bit ALECTL is set to `1', external bus cycles accessing the respective address window will have their ALE signal prolonged by half a CPU clock (31.25 ns at fCPU = 16 MHz). Also the address hold time after the falling edge of ALE (on a multiplexed bus) will be prolonged by half a CPU clock, so the data transfer within a bus cycle refers to the same CLKOUT edges as usual (ie. the data transfer is delayed by one CPU clock). This allows more time for the address to be latched. Note: ALECTL0 is `1' after reset to select the slowest possible bus cycle, the other ALECTLx are `0' after reset. Figure 8-6 ALE Length Control Semiconductor Group 8-11 10Jul97@15:19h The External Bus Interface / C161 Programmable Memory Cycle Time The C161 allows the user to adjust the controller's external bus cycles to the access time of the respective memory or peripheral. This access time is the total time required to move the data to the destination. It represents the period of time during which the controller's signals do not change. Figure 8-7 Memory Cycle Time The external bus cycles of the C161 can be extended for a memory or peripheral, which cannot keep pace with the controller's maximum speed, by introducing wait states during the access (see figure above). During these memory cycle time wait states, the CPU is idle, if this access is required for the execution of the current instruction. The memory cycle time wait states can be programmed in increments of one CPU clock (62.5 ns at fCPU = 16 MHz) within a range from 0 to 15 (default after reset) via the MCTC fields of the BUSCON registers. 15- Semiconductor Group 8-12 10Jul97@15:19h The External Bus Interface / C161 Programmable Memory Tri-State Time The C161 allows the user to adjust the time between two subsequent external accesses to account for the tri-state time of the external device. The tri-state time defines, when the external device has released the bus after deactivation of the read command (RD). Figure 8-8 Memory Tri-State Time The output of the next address on the external bus can be delayed for a memory or peripheral, which needs more time to switch off its bus drivers, by introducing a wait state after the previous bus cycle (see figure above). During this memory tri-state time wait state, the CPU is not idle, so CPU operations will only be slowed down if a subsequent external instruction or data fetch operation is required during the next instruction cycle. The memory tri-state time waitstate requires one CPU clock (62.5 ns at fCPU = 16 MHz) and is controlled via the MTTCx bits of the BUSCON registers. A waitstate will be inserted, if bit MTTCx is `0' (default after reset). Note: External bus cycles in multiplexed bus modes implicitly add one tri-state time waitstate in addition to the programmable MTTC waitstate. Semiconductor Group 8-13 10Jul97@15:19h The External Bus Interface / C161 Read/Write Signal Delay The C161 allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals. The read/write delay controls the time between the falling edge of ALE and the falling edge of the command. Without read/write delay the falling edges of ALE and command(s) are coincident (except for propagation delays). With the delay enabled, the command(s) become active half a CPU clock (31.25 ns at fCPU = 16 MHz) after the falling edge of ALE. The read/write delay does not extend the memory cycle time, and does not slow down the controller in general. In multiplexed bus modes, however, the data drivers of an external device may conflict with the C161's address, when the early RD signal is used. Therefore multiplexed bus cycles should always be programmed with read/write delay. 1) The data drivers from the previous bus cycle should be disabled when the RD signal becomes active. Figure 8-9 Read/Write Delay The read/write delay is controlled via the RWDCx bits in the BUSCON registers. The command(s) will be delayed, if bit RWDCx is `0' (default after reset). Semiconductor Group 8-14 10Jul97@15:19h The External Bus Interface / C161 8.3 Controlling the External Bus Controller A set of registers controls the functions of the EBC. General features like the usage of interface pins (WR, BHE), segmentation and internal ROM mapping are controlled via register SYSCON. The properties of a bus cycle like chip select mode, length of ALE, external bus mode, read/write delay and waitstates are controlled via registers BUSCON4...BUSCON0. Four of these registers (BUSCON4...BUSCON1) have an address select register (ADDRSEL4...ADDRSEL1) associated with them, which allows to specify up to four address areas and the individual bus characteristics within these areas. All accesses that are not covered by these four areas are then controlled via BUSCON0. This allows to use memory components or peripherals with different interfaces within the same system, while optimizing accesses to each of them. Semiconductor Group 8-15 10Jul97@15:19h The External Bus Interface / C161 SYSCON (FF12H / 89H) 15 14 STKSZ rw 13 12 11 10 9 8 ROM SGT ROM BYT S1 DIS EN DIS rw rw rw rw SFR 7 WR CFG rw 6 5 4 - Reset Value: 0XX0H 3 2 1 VISI 0 XPER- XPEN BLE SHARE rw rw rw Bit Function XPER-SHARE XBUS Peripheral Share Mode Control `0': External accesses to XBUS peripherals are disabled `1': XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control `0': Accesses to XBUS peripherals are done internally `1': XBUS peripheral accesses are made visible on the external pins XBUS Peripheral Enable Bit `0': Accesses to the on-chip X-Peripherals and their functions are disabled `1': The on-chip X-Peripherals are enabled and can be accessed Write Configuration Control (Set according to pin P0H.0 during reset) `0': Pins WR and BHE retain their normal function `1': Pin WR acts as WRL, pin BHE acts as WRH Disable/Enable Control for Pin BHE (Set according to data bus width) `0': Pin BHE enabled `1': Pin BHE disabled, pin may be used for general purpose IO Internal ROM Enable (Set according to pin EA during reset) `0': Internal ROM disabled: accesses to the ROM area use the external bus `1': Internal ROM enabled Segmentation Disable/Enable Control `0': Segmentation enabled (CSP is saved/restored during interrupt entry/exit) `1': Segmentation disabled (Only IP is saved/restored) Internal ROM Mapping `0': Internal ROM area mapped to segment 0 (00'0000H...00'7FFFH) `1': Internal ROM area mapped to segment 1 (01'0000H...01'7FFFH) System Stack Size Selects the size of the system stack (in the internal RAM) from 32 to 1024 words XPEN WRCFG BYTDIS ROMEN SGTDIS ROMS1 STKSZ Note: Register SYSCON cannot be changed after execution of the EINIT instruction. Bit SGTDIS controls the correct stack operation (push/pop of CSP or not) during traps and interrupts. Semiconductor Group 8-16 10Jul97@15:19h The External Bus Interface / C161 The layout of the five BUSCON registers is identical. Registers BUSCON4...BUSCON1, which control the selected address windows, are completely under software control, while register BUSCON0, which eg. is also used for the very first code access after reset, is partly controlled by hardware, ie. it is initialized via PORT0 during the reset sequence. This hardware control allows to define an appropriate external bus for systems, where no internal program memory is provided. BUSCON0 (FF0CH / 86H) 15 14 13 rw 12 11 10 9 8 CSW CSR EN0 EN0 rw rw BUS ALE ACT0 CTL0 rw rw SFR 7 6 5 4 MTT RWD C0 C0 rw rw Reset Value: 0XX0H 3 2 1 0 BTYP rw MCTC rw BUSCON1 (FF14H / 8AH) 15 14 13 rw 12 11 10 9 8 CSW CSR EN1 EN1 rw rw BUS ALE ACT1 CTL1 rw rw SFR 7 6 5 4 MTT RWD C1 C1 rw rw Reset Value: 0000H 3 2 1 0 BTYP rw MCTC rw BUSCON2 (FF16H / 8BH) 15 14 13 rw 12 11 10 9 8 CSW CSR EN2 EN2 rw rw BUS ALE ACT2 CTL2 rw rw SFR 7 6 5 4 MTT RWD C2 C2 rw rw Reset Value: 0000H 3 2 1 0 BTYP rw MCTC rw BUSCON3 (FF18H / 8CH) 15 14 13 rw 12 11 10 9 8 CSW CSR EN3 EN3 rw rw BUS ALE ACT3 CTL3 rw rw SFR 7 6 5 4 MTT RWD C3 C3 rw rw Reset Value: 0000H 3 2 1 0 BTYP rw MCTC rw BUSCON4 (FF1AH / 8DH) 15 14 13 rw 12 11 10 9 8 CSW CSR EN4 EN4 rw rw BUS ALE ACT4 CTL4 rw rw SFR 7 6 5 4 MTT RWD C4 C4 rw rw Reset Value: 0000H 3 2 1 0 BTYP rw MCTC rw Note: BUSCON0 is initialized with 0000 H, if pin EA is high during reset. If pin EA is low during reset, bits BUSACT0 and ALECTL0 are set (`1') and bit field BTYP is loaded with the bus configuration selected via PORT0. Semiconductor Group 8-17 10Jul97@15:19h The External Bus Interface / C161 Bit MCTC Function Memory Cycle Time Control (Number of memory cycle time wait states) 0 0 0 0 : 15 waitstates (Number = 15 - RWDCx MTTCx BTYP ALECTLx BUSACTx CSRENx CSWENx Semiconductor Group 8-18 10Jul97@15:19h The External Bus Interface / C161 ADDRSEL1 (FE18H / 0CH) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: 0000H 3 2 1 0 RGSAD rw RGSZ rw ADDRSEL2 (FE1AH / 0DH) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: 0000H 3 2 1 0 RGSAD rw RGSZ rw ADDRSEL3(FE1CH / 0EH) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: 0000H 3 2 1 0 RGSAD rw RGSZ rw ADDRSEL4 (FE1EH / 0FH) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 Reset Value: 0000H 3 2 1 0 RGSAD rw RGSZ rw Bit RGSZ Function Range Size Selection Defines the size of the address area controlled by the respective BUSCONx/ ADDRSELx register pair. See table below. Range Start Address Defines the upper bits of the start address (A23...) of the respective address area. See table below. RGSAD Note: There is no register ADDRSEL0, as register BUSCON0 controls all external accesses outside the four address windows of BUSCON4...BUSCON1 within the complete address space. Semiconductor Group 8-19 10Jul97@15:19h The External Bus Interface / C161 Definition of Address Areas The four register pairs BUSCON4/ADDRSEL4...BUSCON1/ADDRSEL1 allow to define 4 separate address areas within the address space of the C161. Within each of these address areas external accesses can be controlled by one of the four different bus modes, independent of each other and of the bus mode specified in register BUSCON0. Each ADDRSELx register in a way cuts out an address window, within which the parameters in register BUSCONx are used to control external accesses. The range start address of such a window defines the upper address bits, which are not used within the address window of the specified size (see table below). For a given window size only those upper address bits of the start address are used (marked "R"), which are not implicitly used for addresses inside the window. The lower bits of the start address (marked "x") are disregarded. Bit field RGSZ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 11xx Resulting Window Size 4 KByte 8 KByte 16 KByte 32 KByte 64 KByte 128 KByte 256 KByte 512 KByte 1 MByte 2 MByte 4 MByte 8 MByte Reserved. Relevant Bits (R) of Start Address (A23...A12) R R R R R R R R R R R R R R R R R R R R R R R x R R R R R R R R R R x x R R R R R R R R R x x x R R R R R R R R x x x x R R R R R R R x x x x x R R R R R R x x x x x x R R R R R x x x x x x x R R R R x x x x x x x x R R R x x x x x x x x x R R x x x x x x x x x x R x x x x x x x x x x x Note: Only the address lines A22...A12 of the internal 24-bit address are externally available on port pins. This may lead to multiple mapping or overlapping of larger address windows. Semiconductor Group 8-20 10Jul97@15:19h The External Bus Interface / C161 Address Window Arbitration For each access the EBC compares the current address with all address select registers (programmable ADDRSELx and hardwired XADRSx). This comparison is done in four levels. Priority 1: The hardwired XADRSx registers are evaluated first. A match with one of these registers directs the access to the respective X-Peripheral using the corresponding XBCONx register and ignoring all other ADDRSELx registers. Priority 2: Registers ADDRSEL2 and ADDRSEL4 are evaluated before ADDRSEL1 and ADDRSEL3, respectively. A match with one of these registers directs the access to the respective external area using the corresponding BUSCONx register and ignoring registers ADDRSEL1/3 (see figure below). Priority 3: A match with registers ADDRSEL1 or ADDRSEL3 directs the access to the respective external area using the corresponding XBCONx register. Priority 4: If there is no match with any XADRSx or ADDRSELx register the access to the external bus uses register BUSCON0. XBCON0 Active Window Inactive Window BUSCON2 BUSCON1 BUSCON0 BUSCON4 BUSCON3 Figure 8-10 Address Window Arbitration Note: Only the indicated overlaps are defined. All other overlaps lead to erroneous bus cycles. Eg. ADDRSEL4 may not overlap ADDRSEL2 or ADDRSEL1. The hardwired XADRSx registers are defined non-overlapping. Semiconductor Group 8-21 10Jul97@15:19h The External Bus Interface / C161 RP0H (F108H / 84H) 15 14 13 12 11 10 9 8 SFR 7 6 CLKCFG 5 4 Reset Value: - - XXH 3 2 1 0 WRC r SALSEL r CSSEL r - - - - - - - - r Bit WRC Function Write Configuration 0: Pins WR and BHE operate as WRL and WRH signals 1: Pins WR and BHE operate as WR and BHE signals Chip Select Line Selection (Number of active CS outputs) 0 0: 3 CS lines: CS2...CS0 0 1: 2 CS lines: CS1...CS0 1 0: No CS lines at all 1 1: 4 CS lines: CS3...CS0 (Default without pulldowns) Segment Address Line Selection (Number of active segment address outputs) 0 0: 4-bit segment address: A19...A16 0 1: No segment address lines at all 1 0: 6-bit segment address: A21...A16 1 1: 2-bit segment address: A17...A16 (Default without pulldowns) Clock Generation Mode Configuration These pins define the clock generation mode, ie. the mechanism how the the internal CPU clock is generated from the externally applied (XTAL1) input clock. CSSEL SALSEL CLKCFG Note: RP0H cannot be changed via software, but rather allows to check the current configuration. Precautions and Hints * The external bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT bit set. * PORT1 will output the intra-segment address as long as at least one of the BUSCON registers selects a demultiplexed external bus, even for multiplexed bus cycles. * Not all address areas defined via registers ADDRSELx may overlap each other. The operation of the EBC will be unpredictable in such a case. See chapter Address Window Arbitration". * The address areas defined via registers ADDRSELx may overlap internal address areas. Internal accesses will be executed in this case. * For any access to an internal address area the EBC will remain inactive (see EBC Idle State). Semiconductor Group 8-22 10Jul97@15:19h The External Bus Interface / C161 8.4 EBC Idle State When the external bus interface is enabled, but no external access is currently executed, the EBC is idle. As long as only internal resources (from an architecture point of view) like IRAM, GPRs or SFRs, etc. are used the external bus interface does not change (see table below). Accesses to on-chip X-Peripherals are also controlled by the EBC. However, even though an XPeripheral appears like an external peripheral to the controller, the respective accesses do not generate valid external bus cycles. Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus interface (see table below). The address" mentioned above includes PORT1, Port 4, BHE and ALE which also pulses for an XBUS cycle. The external CS signals on Port 6 are driven inactive (high) because the EBC switches to an internal XCS signal. The external control signals (RD and WR or WRL/WRH if enabled) remain inactive (high). Status of the external bus interface during EBC idle state: Pins PORT0 PORT1 Port 4 Port 6 BHE ALE RD WR/WRL WRH Internal accesses only Tristated (floating) Last used external address (if used for the bus interface) Last used external segment address (on selected pins) Active external CS signal corresponding to last used address Level corresponding to last external access Inactive (low) Inactive (high) Inactive (high) Inactive (high) XBUS accesses Tristated (floating) for read accesses XBUS write data for write accesses Last used XBUS address (if used for the bus interface) Last used XBUS segment address (on selected pins) Inactive (high) for selected CS signals Level corresponding to last XBUS access Pulses as defined for X-Peripheral Inactive (high) Inactive (high) Inactive (high) Semiconductor Group 8-23 10Jul97@15:19h The External Bus Interface / C161 8.5 The XBUS Interface The C161 provides an on-chip interface (the XBUS interface), which allows to connect integrated customer/application specific peripherals to the standard controller core. The XBUS is an internal representation of the external bus interface, ie. it is operated in the same way. The current XBUS interface is prepared to support up to 3 X-Peripherals. For each peripheral on the XBUS (X-Peripheral) there is a separate address window controlled by an XBCON and an XADRS register. As an interface to a peripheral in many cases is represented by just a few registers, the XADRS registers select smaller address windows than the standard ADDRSEL registers. As the register pairs control integrated peripherals rather than externally connected ones, they are fixed by mask programming rather than being user programmable. X-Peripheral accesses provide the same choices as external accesses, so these peripherals may be bytewide or wordwide, with or without a separate address bus. Interrupt nodes and configuration pins (on PORT0) are provided for X-Peripherals to be integrated. Note: If you plan to develop a peripheral of your own to be integrated into a C161 device to create a customer specific version, please ask for the specification of the XBUS interface and for further support. Semiconductor Group 8-24 10Jul97@15:19h The General Purpose Timer Units / C161 9 The General Purpose Timer Units The General Purpose Timer Units GPT1 and GPT2 represent very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2 (C161O only). Block GPT1 contains 3 timers/counters with a maximum resolution of 500 ns (@ 16 MHz CPU clock), while block GPT2 contains 2 timers/counters with a maximum resolution of 250 ns (@ 16 MHz CPU clock) and a 16-bit Capture/Reload register (CAPREL). Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer. In the GPT2 block, the additional CAPREL register supports capture and reload operation with extended functionality. Each block may have alternate input/output functions and specific interrupts associated with it. 9.1 Timer Block GPT1 From a programmer's point of view, the GPT1 block is composed of a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded. Ports & Direction Control Alternate Functions Data Registers Control Registers Interrupt Control ODP3 DP3 P3 P5 T2IN/P3.7 T3IN/P3.6 T4IN/P3.5 T3OUT/P3.3 ODP3 DP3 P3 T2CON T3CON T4CON T2EUD/P5.15 T3EUD/P3.4 T4EUD/P5.14 T2 T3 T4 T2CON T3CON T4CON T2IC T3IC T4IC Port 3 Open Drain Control Register Port 3 Direction Control Register Port 3 Data Register GPT1 Timer 2 Control Register GPT1 Timer 3 Control Register GPT1 Timer 4 Control Register T2 T3 T4 T2IC T3IC T4IC GPT1 Timer 2 Register GPT1 Timer 3 Register GPT1 Timer 4 Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Interrupt Control Register Figure 9-1 SFRs and Port Pins Associated with Timer Block GPT1 Note: External GPT1 control is provided on the C161K and the C161O, not on the C161V. Semiconductor Group 9-1 10Jul97@15:19h The General Purpose Timer Units / C161 All three timers of block GPT1 (T2, T3, T4) can run in 3 basic modes, which are timer, gated timer, and counter mode, and all timers can either count up or down. Each timer has an alternate input function pin on Port 3 associated with it which serves as the gate control in gated timer mode, or as the count input in counter mode. The count direction (Up / Down) may be programmed via software or may be dynamically altered by a signal at an external control input pin. Each overflow/underflow of core timer T3 may be indicated on an alternate output function pin. The auxiliary timers T2 and T4 may additionally be concatenated with the core timer, or used as capture or reload registers for the core timer. Note: External GPT1 control is provided on the C161K and the C161O, not on the C161V. The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2, T3, or T4, which are located in the non-bitaddressable SFR space. When any of the timer registers is written to by the CPU in the state immediately before a timer increment, decrement, reload, or capture is to be performed, the CPU write operation has priority in order to guarantee correct results. Figure 9-2 GPT1 Block Diagram Semiconductor Group 9-2 10Jul97@15:19h The General Purpose Timer Units / C161 GPT1 Core Timer T3 The core timer T3 is configured and controlled via its bitaddressable control register T3CON. T3CON (FF42H / A1H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 T3M rw T3 T3 OTL T3OE UDE T3UD T3R rw rw rw rw rw Reset Value: 0000H 3 2 1 T3I rw 0 Bit T3I T3M Function Timer 3 Input Selection Depends on the operating mode, see respective sections. Timer 3 Mode Control (Basic Operating Mode) 000: Timer Mode 001: Counter Mode 1) 010: Gated Timer with Gate active low 1) 011: Gated Timer with Gate active high 1) 1XX: Reserved. Do not use this combination. Timer 3 Run Bit T3R = `0': Timer / Counter 3 stops T3R = `1': Timer / Counter 3 runs Timer 3 Up / Down Control 2) Timer 3 External Up/Down Enable 2) Alternate Output Function Enable 1) T3OE = `0': Alternate Output Function Disabled T3OE = `1': Alternate Output Function Enabled Timer 3 Output Toggle Latch Toggles on each overflow / underflow of T3. Can be set or reset by software. T3R T3UD T3UDE T3OE T3OTL 1) 2) This function cannot be selected on the C161V. For the effects of bits T3UD and T3UDE refer to the direction table below. Timer 3 Run Bit The timer can be started or stopped by software through bit T3R (Timer T3 Run Bit). If T3R=`0', the timer stops. Setting T3R to `1' will start the timer. In gated timer mode, the timer will only run if T3R=`1' and the gate is active (high or low, as programmed). Semiconductor Group 9-3 10Jul97@15:19h The General Purpose Timer Units / C161 Count Direction Control The count direction of the core timer can be controlled either by software or by the external input pin T3EUD (Timer T3 External Up/Down Control Input), which is the alternate input function of port pin P3.4. These options are selected by bits T3UD and T3UDE in control register T3CON. When the up/ down control is done by software (bit T3UDE=`0'), the count direction can be altered by setting or clearing bit T3UD. When T3UDE=`1', pin T3EUD is selected to be the controlling source of the count direction. However, bit T3UD can still be used to reverse the actual count direction, as shown in the table below. If T3UD=`0' and pin T3EUD shows a low level, the timer is counting up. With a high level at T3EUD the timer is counting down. If T3UD=`1', a high level at pin T3EUD specifies counting up, and a low level specifies counting down. The count direction can be changed regardless of whether the timer is running or not. When pin T3EUD/P3.4 is used as external count direction control input, it must be configured as input, ie. its corresponding direction control bit DP3.4 must be set to `0'. GPT1 Core Timer T3 Count Direction Control Pin TxEUD X X 0 1 0 1 Bit TxUDE 0 0 1 1 1 1 Bit TxUD 0 1 0 0 1 1 Count Direction Count Up Count Down Count Up Count Down Count Down Count Up Note: The direction control works the same for core timer T3 and for auxiliary timers T2 and T4. Therefore the pins and bits are named Tx... External GPT1 control is provided on the C161K and the C161O, not on the C161V. Timer 3 Output Toggle Latch An overflow or underflow of timer T3 will clock the toggle bit T3OTL in control register T3CON. T3OTL can also be set or reset by software. Bit T3OE (Alternate Output Function Enable) in register T3CON enables the state of T3OTL to be an alternate function of the external output pin T3OUT/ P3.3. For that purpose, a `1' must be written into port data latch P3.3 and pin T3OUT/P3.3 must be configured as output by setting direction control bit DP3.3 to `1'. If T3OE=`1', pin T3OUT then outputs the state of T3OTL. If T3OE=`0', pin T3OUT can be used as general purpose IO pin. In addition, T3OTL can be used in conjunction with the timer over/underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4. For this purpose, the state of T3OTL does not have to be available at pin T3OUT, because an internal connection is provided for this option. Note: External GPT1 control is provided on the C161K and the C161O, not on the C161V. Semiconductor Group 9-4 10Jul97@15:19h The General Purpose Timer Units / C161 Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to `000 B'. In this mode, T3 is clocked with the internal system clock (CPU clock) divided by a programmable prescaler, which is selected by bit field T3I. The input frequency fT3 for timer T3 and its resolution rT3 are scaled linearly with lower clock frequencies fCPU, as can be seen from the following formula: fT3 = fCPU 8 * 2 T3EUD T3OUT = = P3.4 P3.3 x=3 Figure 9-3 Block Diagram of Core Timer T3 in Timer Mode The timer input frequencies, resolution and periods which result from the selected prescaler option when using a 16 MHz CPU clock are listed in the table below. This table also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in timer and gated timer mode. Note that some numbers may be rounded to 3 significant digits. GPT1 Timer Input Frequencies, Resolution and Periods fCPU = 16 MHz Prescaler factor Input Frequency Resolution Period Timer Input Selection T2I / T3I / T4I 000B 8 2 MHz 500 ns 33 ms 001B 16 1 MHz 1 s 66 ms 010B 32 500 kHz 2 s 011B 64 250 kHz 4 s 100B 128 125 kHz 8 s 101B 256 62.5 kHz 16 s 110B 512 31.25 kHz 32 s 2.1 s 111B 1024 15.625 kHz 64 s 4.2 s 131 ms 262 ms 524 ms 1.05 s Semiconductor Group 9-5 10Jul97@15:19h The General Purpose Timer Units / C161 Timer 3 in Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to `010B' or `011B'. Bit T3M.0 (T3CON.3) selects the active level of the gate input. In gated timer mode the same options for the input frequency as for the timer mode are available. However, the input clock to the timer in this mode is gated by the external input pin T3IN (Timer T3 External Input), which is an alternate function of P3.6. To enable this operation pin T3IN/P3.6 must be configured as input, ie. direction control bit DP3.6 must contain `0'. Note: External GPT1 control is provided on the C161K and the C161O, not on the C161V. T3IN T3EUD T3OUT = = = P3.6 P3.4 P3.3 x=3 Figure 9-4 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M.0=`0', the timer is enabled when T3IN shows a low level. A high level at this pin stops the timer. If T3M.0=`1', pin T3IN must have a high level in order to enable the timer. In addition, the timer can be turned on or off by software using bit T3R. The timer will only run, if T3R=`1' and the gate is active. It will stop, if either T3R=`0' or the gate is inactive. Note: A transition of the gate signal at pin T3IN does not cause an interrupt request. Semiconductor Group 9-6 10Jul97@15:19h The General Purpose Timer Units / C161 Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON to `001 B'. In counter mode timer T3 is clocked by a transition at the external input pin T3IN, which is an alternate function of P3.6. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this pin. Bit field T3I in control register T3CON selects the triggering transition (see table below). Note: External GPT1 control is provided on the C161K and the C161O, not on the C161V. T3IN T3EUD T3OUT = = = P3.6 P3.4 P3.3 x=3 Figure 9-5 Block Diagram of Core Timer T3 in Counter Mode GPT1 Core Timer T3 (Counter Mode) Input Edge Selection T3I 000 001 010 011 1XX Triggering Edge for Counter Increment / Decrement None. Counter T3 is disabled Positive transition (rising edge) on T3IN Negative transition (falling edge) on T3IN Any transition (rising or falling edge) on T3IN Reserved. Do not use this combination For counter operation, pin T3IN/P3.6 must be configured as input, ie. direction control bit DP3.6 must be `0'. The maximum input frequency which is allowed in counter mode is fCPU/16 (1 MHz @ fCPU= 16 MHz). To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized, its level should be held high or low for at least 8 fCPU cycles before it changes. Semiconductor Group 9-7 10Jul97@15:19h The General Purpose Timer Units / C161 GPT1 Auxiliary Timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality. They can be configured for timer, gated timer, or counter mode with the same options for the timer frequencies and the count signal as the core timer T3. In addition to these 3 counting modes, the auxiliary timers can be concatenated with the core timer, or they may be used as reload or capture registers in conjunction with the core timer. Note: The auxiliary timers have no output toggle latch and no alternate output function. The individual configuration for timers T2 and T4 is determined by their bitaddressable control registers T2CON and T4CON, which are both organized identically. Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers. T2CON (FF40H / A0H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 T2M rw T2 UDE T2UD T2R rw rw rw Reset Value: 0000H 3 2 1 T2I rw 0 T4CON (FF44H / A2H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 T4M rw T4 UDE T4UD T4R rw rw rw Reset Value: 0000H 3 2 1 T4I rw 0 Bit TxI TxM Function Timer x Input Selection Depends on the Operating Mode, see respective sections. Timer x Mode Control (Basic Operating Mode) 000: Timer Mode 001: Counter Mode 1) 010: Gated Timer with Gate active low 1) 011: Gated Timer with Gate active high 1) 100: Reload Mode 1) 101: Capture Mode 1) 11X: Reserved. Do not use this combination Timer x Run Bit TxR = `0': Timer / Counter x stops TxR = `1': Timer / Counter x runs Timer x Up / Down Control 2) Timer x External Up/Down Enable 2) TxR TxUD TxUDE 1) 2) This function cannot be selected on the C161V. For the effects of bits T3UD and T3UDE refer to the direction table below. 9-8 Semiconductor Group 10Jul97@15:19h The General Purpose Timer Units / C161 Count Direction Control for Auxiliary Timers The count direction of the auxiliary timers can be controlled in the same way as for the core timer T3. The description and the table apply accordingly. Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode, their operation is the same as described for the core timer T3. The descriptions, figures and tables apply accordingly with one exception: * There is no output toggle latch and no alternate output pin for T2 and T4. Note: External GPT1 control is provided on the C161K and the C161O, not on the C161V. Semiconductor Group 9-9 10Jul97@15:19h The General Purpose Timer Units / C161 Timers T2 and T4 in Counter Mode Counter mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to `001B'. In counter mode timers T2 and T4 can be clocked either by a transition at the respective external input pin TxIN, or by a transition of timer T3's output toggle latch T3OTL. x = 2,4 Figure 9-6 Block Diagram of an Auxiliary Timer in Counter Mode The event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin, or at the toggle latch T3OTL. Bit field TxI in the respective control register TxCON selects the triggering transition (see table below). GPT1 Auxiliary Timer (Counter Mode) Input Edge Selection T2I / T4I X00 001 010 011 101 110 111 Triggering Edge for Counter Increment / Decrement None. Counter Tx is disabled Positive transition (rising edge) on TxIN Negative transition (falling edge) on TxIN Any transition (rising or falling edge) on TxIN Positive transition (rising edge) of output toggle latch T3OTL Negative transition (falling edge) of output toggle latch T3OTL Any transition (rising or falling edge) of output toggle latch T3OTL Note: Only state transitions of T3OTL which are caused by the overflows/underflows of T3 will trigger the counter function of T2/T4. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. Semiconductor Group 9-10 10Jul97@15:19h The General Purpose Timer Units / C161 For counter operation, pin TxIN must be configured as input, ie. the respective direction control bit must be `0'. The maximum input frequency which is allowed in counter mode is fCPU/16 (1 MHz @ fCPU= 16 MHz). To ensure that a transition of the count input signal which is applied to TxIN is correctly recognized, its level should be held for at least 8 fCPU cycles before it changes. Note: External GPT1 control is provided on the C161K and the C161O, not on the C161V. Timer Concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer. Depending on which transition of T3OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a 33-bit timer/counter. * 32-bit Timer/Counter: If both a positive and a negative transition of T3OTL is used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T3. Thus, the two timers form a 32-bit timer. * 33-bit Timer/Counter: If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T3. This configuration forms a 33-bit timer (16-bit core timer+T3OTL+16-bit auxiliary timer). The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. T3 can operate in timer, gated timer or counter mode in this case. T3OUT *) = P3.3 x = 2,4 y = 3 Note: Line only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 9-7 Concatenation of Core Timer T3 and an Auxiliary Timer Semiconductor Group 9-11 10Jul97@15:19h The General Purpose Timer Units / C161 Auxiliary Timer in Reload Mode Reload mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to `100B'. In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register, triggered by one of two different signals. The trigger signal is selected the same way as the clock source for counter mode (see table above), ie. a transition of the auxiliary timer's input or the output toggle latch T3OTL may trigger the reload. Note: When programmed for reload mode, the respective auxiliary timer (T2 or T4) stops independent of its run flag T2R or T4R. *) Note: Line only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 9-8 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal T3 is loaded with the contents of the respective timer register (T2 or T4) and the interrupt request flag (T2IR or T4IR) is set. Note: When a T3OTL transition is selected for the trigger signal, also the interrupt request flag T3IR will be set upon a trigger, indicating T3's overflow or underflow. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. The reload mode triggered by T3OTL can be used in a number of different configurations. Depending on the selected active transition the following functions can be performed: * If both a positive and a negative transition of T3OTL is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows. This is the standard reload mode (reload on overflow/underflow). * If either a positive or a negative transition of T3OTL is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow. Semiconductor Group 9-12 10Jul97@15:19h The General Purpose Timer Units / C161 * Using this "single-transition" mode for both auxiliary timers allows to perform very flexible pulse width modulation (PWM). One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL, the other is programmed for a reload on a negative transition of T3OTL. With this combination the core timer is alternately reloaded from the two auxiliary timers. The figure below shows an example for the generation of a PWM signal using the alternate reload mechanism. T2 defines the high time of the PWM signal (reloaded on positive transitions) and T4 defines the low time of the PWM signal (reloaded on negative transitions). The PWM signal can be output on T3OUT with T3OE=`1', P3.3=`1' and DP3.3=`1'. With this method the high and low time of the PWM signal can be varied in a wide range. Note: The output toggle latch T3OTL is accessible via software and may be changed, if required, to modify the PWM signal. However, this will NOT trigger the reloading of T3. *) Note: Lines only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 9-9 GPT1 Timer Reload Configuration for PWM Generation Note: Although it is possible, it should be avoided to select the same reload trigger event for both auxiliary timers. In this case both reload registers would try to load the core timer at the same time. If this combination is selected, T2 is disregarded and the contents of T4 is reloaded. External GPT1 control is provided on the C161K and the C161O, not on the C161V. Semiconductor Group 9-13 10Jul97@15:19h The General Purpose Timer Units / C161 Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to `101B'. In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer's external input pin TxIN. The capture trigger signal can be a positive, a negative, or both a positive and a negative transition. The two least significant bits of bit field TxI are used to select the active transition (see table in the counter mode section), while the most significant bit TxI.2 is irrelevant for capture mode. It is recommended to keep this bit cleared (TxI.2 = `0'). Note: When programmed for capture mode, the respective auxiliary timer (T2 or T4) stops independent of its run flag T2R or T4R. Figure 9-10 GPT1 Auxiliary Timer in Capture Mode Upon a trigger (selected transition) at the corresponding input pin TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set. Note: The direction control bits DP3.7 (for T2IN) and DP3.5 (for T4IN) must be set to '0', and the level of the capture trigger signal should be held high or low for at least 8 fCPU cycles before it changes to ensure correct edge detection. External GPT1 control is provided on the C161K and the C161O, not on the C161V. Semiconductor Group 9-14 10Jul97@15:19h The General Purpose Timer Units / C161 Interrupt Control for GPT1 Timers When a timer overflows from FFFFH to 0000H (when counting up), or when it underflows from 0000H to FFFFH (when counting down), its interrupt request flag (T2IR, T3IR or T4IR) in register TxIC will be set. This will cause an interrupt to the respective timer interrupt vector (T2INT, T3INT or T4INT) or trigger a PEC service, if the respective interrupt enable bit (T2IE, T3IE or T4IE in register TxIC) is set. There is an interrupt control register for each of the three timers. T2IC (FF60H / B0H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 T2IR T2IE rw rw GLVL rw T3IC (FF62H / B1H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 T3IR T3IE rw rw GLVL rw T4IC (FF64H / B2H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 T4IR T4IE rw rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. Semiconductor Group 9-15 10Jul97@15:19h The General Purpose Timer Units / C161 9.2 Timer Block GPT2 From a programmer's point of view, the GPT2 block is represented by a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded. Ports & Direction Control Alternate Functions Data Registers Control Registers Interrupt Control ODP3 DP3 P3 CAPIN/P3.2 ODP3 DP3 P3 T5CON T6CON E T5 T6 CAPREL T5CON T6CON T5IC T6IC CRIC Port 3 Open Drain Control Register Port 3 Direction Control Register Port 3 Data Register GPT2 Timer 5 Control Register GPT2 Timer 6 Control Register T5 T6 CAPREL T5IC T6IC CRIC GPT2 Timer 5 Register GPT2 Timer 6 Register GPT2 Capture/Reload Register GPT2 Timer 5 Interrupt Control Register Control Registers GPT2 Timer 6 Interrupt Control Register GPT2 CAPREL Interrupt Control Register Figure 9-11 SFRs and Port Pins Associated with Timer Block GPT2 Note: GPT2 is only provided on the C161O. Timer block GPT2 supports high precision event control with a maximum resolution of 250 ns (@ 16 MHz CPU clock). It includes the two timers T5 and T6, and the 16-bit capture/reload register CAPREL. Timer T6 is referred to as the core timer, and T5 is referred to as the auxiliary timer of GPT2. The count direction (Up / Down) may be programmed via software. An overflow/underflow of T6 is indicated by the output toggle bit T6OTL. In addition, T6 may be reloaded with the contents of CAPREL. The toggle bit supports the concatenation of T6 with auxiliary timer T5. Triggered by an external signal, the contents of T5 can be captured into register CAPREL, and T5 may optionally be cleared. Both timer T6 and T5 can count up or down, and the current timer value can be read or modified by the CPU in the non-bitaddressable SFRs T5 and T6. Semiconductor Group 9-16 10Jul97@15:19h The General Purpose Timer Units / C161 Figure 9-12 GPT2 Block Diagram Semiconductor Group 9-17 10Jul97@15:19h The General Purpose Timer Units / C161 GPT2 Core Timer T6 The operation of the core timer T6 is controlled by its bitaddressable control register T6CON. T6CON (FF48H / A4H) 15 T6SR rw 14 13 12 11 10 T6 OTL rw 9 8 - SFR 7 6 5 4 T6M rw Reset Value: 0000H 3 2 1 T6I rw 0 T6UD T6R rw rw Bit T6I T6M Function Timer 6 Input Selection Depends on the Operating Mode, see below. Timer 6 Mode Control (Basic Operating Mode) 000: Timer Mode Note: The other combinations of T6M are reserved and lead to undefined behaviour if selected. Timer 6 Run Bit T6R = `0': Timer / Counter 6 stops T6R = `1': Timer / Counter 6 runs Timer 6 Up / Down Control Timer 6 Output Toggle Latch Toggles on each overflow / underflow of T6. Can be set or reset by software. Timer 6 Reload Mode Enable T6SR = `0': Reload from register CAPREL Disabled T6SR = `1': Reload from register CAPREL Enabled T6R T6UD T6OTL T6SR Timer 6 Run Bit The timer can be started or stopped by software through bit T6R (Timer T6 Run Bit). If T6R=`0', the timer stops. Setting T6R to `1' will start the timer. Count Direction Control The count direction of the core timer can be controlled via software by setting or clearing bit T6UD. The count direction can be changed regardless of whether the timer is running or not. Timer 6 Output Toggle Latch An overflow or underflow of timer T6 will clock the toggle bit T6OTL in control register T6CON. T6OTL can also be set or reset by software. T6OTL can be used in conjunction with the timer over/ underflows as an input for the counter function of the auxiliary timer T5. Semiconductor Group 9-18 10Jul97@15:19h The General Purpose Timer Units / C161 Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bit field T6M in register T6CON to `000 B'. In this mode, T6 is clocked with the internal system clock divided by a programmable prescaler, which is selected by bit field T6I. The input frequency fT6 for timer T6 and its resolution rT6 are scaled linearly with lower clock frequencies fCPU, as can be seen from the following formula: fT6 = fCPU 4 * 2 T6EUD T6OUT = = P5.10 P3.1 x=6 Figure 9-13 Block Diagram of Core Timer T6 in Timer Mode The timer input frequencies, resolution and periods which result from the selected prescaler option when using a 16 MHz CPU clock are listed in the table below. Note that some numbers may be rounded to 3 significant digits. GPT2 Timer Input Frequencies, Resolution and Periods fCPU = 16 MHz Prescaler factor Input Frequency Resolution Period Timer Input Selection T5I / T6I 000B 4 4 MHz 250ns 16 ms 001B 8 2 MHz 500 ns 33 ms 010B 16 1 MHz 1 s 011B 32 500 kHz 2 s 100B 64 250 kHz 4 s 101B 128 125 kHz 8 s 110B 256 62.5 kHz 16 s 111B 512 31.25 kHz 32 s 2.1 s 65.5 ms 131 ms 262 ms 524 ms 1.05 s Semiconductor Group 9-19 10Jul97@15:19h The General Purpose Timer Units / C161 GPT2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer mode with the same options for the timer frequencies as the core timer T6. In addition the auxiliary timer can be concatenated with the core timer. Note: The auxiliary timer has no output toggle latch. The individual configuration for timer T5 is determined by its bitaddressable control register T5CON. Note that functions which are present in both timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers. T5CON (FF46H / A3H) 15 14 13 CI rw 12 11 10 9 8 T5 T5SC CLR rw rw SFR 7 6 5 4 T5M rw Reset Value: 0000H 3 2 1 T5I rw 0 T5UD T5R rw rw Bit T5I T5M Function Timer 5 Input Selection Depends on the Operating Mode, see below. Timer 5 Mode Control (Basic Operating Mode) 00: Timer Mode Note: The other combinations of T5M are reserved and lead to undefined behaviour if selected. Timer 5 Run Bit T5R = `0': Timer / Counter 5 stops T5R = `1': Timer / Counter 5 runs Timer 5 Up / Down Control Register CAPREL Input Selection 00: Capture disabled 01: Positive transition (rising edge) on CAPIN 10: Negative transition (falling edge) on CAPIN 11: Any transition (rising or falling edge) on CAPIN Timer 5 Clear Bit T5CLR = `0': Timer 5 not cleared on a capture T5CLR = `1': Timer 5 is cleared on a capture Timer 5 Capture Mode Enable T5SC = `0': Capture into register CAPREL Disabled T5SC = `1': Capture into register CAPREL Enabled T5R T5UD CI T5CLR T5SC Semiconductor Group 9-20 10Jul97@15:19h The General Purpose Timer Units / C161 Count Direction Control for Auxiliary Timer The count direction of the auxiliary timer can be controlled in the same way as for the core timer T6. The description applies accordingly. Timer T5 in Timer Mode When the auxiliary timer T5 is programmed to timer mode its operation is the same as described for the core timer T6. The descriptions, figures and tables apply accordingly with one exception: * There is no output toggle latch for T5. Timer Concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer. Depending on which transition of T6OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a 33-bit timer / counter. * 32-bit Timer/Counter: If both a positive and a negative transition of T6OTL is used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T6. Thus, the two timers form a 32-bit timer. * 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T6. This configuration forms a 33-bit timer (16-bit core timer+T6OTL+16-bit auxiliary timer). The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. Semiconductor Group 9-21 10Jul97@15:19h The General Purpose Timer Units / C161 T6OUT *) = P3.1 x =5 y = 6 Note: Line only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 9-14 Concatenation of Core Timer T6 and Auxiliary Timer T5 Semiconductor Group 9-22 10Jul97@15:19h The General Purpose Timer Units / C161 GPT2 Capture/Reload Register CAPREL in Capture Mode This 16-bit register can be used as a capture register for the auxiliary timer T5. This mode is selected by setting bit T5SC=`1' in control register T5CON. The source for a capture trigger is the external input pin CAPIN, which is an alternate input function of port pin P3.2. Either a positive, a negative, or both a positive and a negative transition at this pin can be selected to trigger the capture function. The active edge is controlled by bit field CI in register T5CON. The same coding is used as in the two least significant bits of bit field T5I (see table in counter mode section). The maximum input frequency for the capture trigger signal at CAPIN is fCPU/4 (2 MHz @ fCPU= 16 MHz). To ensure that a transition of the capture trigger signal is correctly recognized, its level should be held for at least 4 fCPU cycles before it changes. When a selected transition at the external input pin CAPIN is detected, the contents of the auxiliary timer T5 are latched into register CAPREL, and interrupt request flag CRIR is set. With the same event, timer T5 can be cleared to 0000H. This option is controlled by bit T5CLR in register T5CON. If T5CLR=`0', the contents of timer T5 are not affected by a capture. If T5CLR=`1', timer T5 is cleared after the current timer value has been latched into register CAPREL. Note: Bit T5SC only controls whether a capture is performed or not. If T5SC=`0', the input pin CAPIN can still be used to clear timer T5 or as an external interrupt input. This interrupt is controlled by the CAPREL interrupt control register CRIC. Figure 9-15 GPT2 Register CAPREL in Capture Mode Semiconductor Group 9-23 10Jul97@15:19h The General Purpose Timer Units / C161 GPT2 Capture/Reload Register CAPREL in Reload Mode This 16-bit register can be used as a reload register for the core timer T6. This mode is selected by setting bit T6SR=`1' in register T6CON. The event causing a reload in this mode is an overflow or underflow of the core timer T6. When timer T6 overflows from FFFFH to 0000H (when counting up) or when it underflows from 0000H to FFFFH (when counting down), the value stored in register CAPREL is loaded into timer T6. This will not set the interrupt request flag CRIR associated with the CAPREL register. However, interrupt request flag T6IR will be set indicating the overflow/underflow of T6. Figure 9-16 GPT2 Register CAPREL in Reload Mode Semiconductor Group 9-24 10Jul97@15:19h The General Purpose Timer Units / C161 GPT2 Capture/Reload Register CAPREL in Capture-And-Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR, the two functions can be enabled simultaneously by setting both bits. This feature can be used to generate an output frequency that is a multiple of the input frequency. Figure 9-17 GPT2 Register CAPREL in Capture-And-Reload Mode This combined mode can be used to detect consecutive external events which may occur aperiodically, but where a finer resolution, that means, more 'ticks' within the time between two external events is required. For this purpose, the time between the external events is measured using timer T5 and the CAPREL register. Timer T5 runs in timer mode counting up with a frequency of eg. fCPU/32. The external events are applied to pin CAPIN. When an external event occurs, the timer T5 contents are latched into register CAPREL, and timer T5 is cleared (T5CLR=`1'). Thus, register CAPREL always contains the correct time between two events, measured in timer T5 increments. Timer T6, which runs in timer mode counting down with a frequency of eg. fCPU/4, uses the value in register CAPREL Semiconductor Group 9-25 10Jul97@15:19h The General Purpose Timer Units / C161 to perform a reload on underflow. This means, the value in register CAPREL represents the time between two underflows of timer T6, now measured in timer T6 increments. Since timer T6 runs 8 times faster than timer T5, it will underflow 8 times within the time between two external events. Thus, the underflow signal of timer T6 generates 8 'ticks'. Upon each underflow, the interrupt request flag T6IR will be set and bit T6OTL will be toggled. T6OTL will have 8 times more transitions than the signal which is applied to pin CAPIN. Interrupt Control for GPT2 Timers and CAPREL When a timer overflows from FFFFH to 0000H (when counting up), or when it underflows from 0000H to FFFFH (when counting down), its interrupt request flag (T5IR or T6IR) in register TxIC will be set. Whenever a transition according to the selection in bit field CI is detected at pin CAPIN, interrupt request flag CRIR in register CRIC is set. Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector (T5INT, T6INT or CRINT) or trigger a PEC service, if the respective interrupt enable bit (T5IE or T6IE in register TxIC, CRIE in register CRIC) is set. There is an interrupt control register for each of the two timers and for the CAPREL register. T5IC (FF66H / B3H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 T5IR T5IE rw rw GLVL rw T6IC (FF68H / B4H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 T6IR T6IE rw rw GLVL rw CRIC (FF6AH / B5H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 CRIR CRIE rw rw GLVL rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. Semiconductor Group 9-26 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 10 The Asynchronous/Synchr. Serial Interface The Asynchronous/Synchronous Serial Interface ASC0 provides serial communication between the C161 and other microcontrollers, microprocessors or external peripherals. The ASC0 supports full-duplex asynchronous communication up to 500 KBaud and half-duplex synchronous communication up to 2 MBaud (@ 16 MHz CPU clock). In synchronous mode, data are transmitted or received synchronous to a shift clock which is generated by the C161. In asynchronous mode, 8- or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection is provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism to distinguish address from data bytes is included. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC0 with a separate serial clock signal. Ports & Direction Control Alternate Functions Data Registers Control Registers Interrupt Control ODP3 DP3 P3 RXD0 / P3.11 TXD0 / P3.10 E S0BG S0TBUF S0RBUF S0CON S0TIC S0RIC S0EIC S0TBIC E ODP3 DP3 S0BG S0TBUF S0TIC S0TBIC Port 3 Open Drain Control Register Port 3 Direction Control Register ASC0 Baud Rate Generator/Reload Register ASC0 Transmit Buffer Register ASC0 Transmit Interrupt Control Register ASC0 Transmit Buffer Interrupt Control Reg. P3 S0CON S0RBUF S0RIC S0EIC Port 3 Data Register ASC0 Control Register ASC0 Receive Buffer Register (read only) ASC0 Receive Interrupt Control Register ASC0 Error Interrupt Control Register Figure 10-1 SFRs and Port Pins associated with ASC0 The operating mode of the serial channel ASC0 is controlled by its bitaddressable control register S0CON. This register contains control bits for mode and error check selection, and status flags for error identification. Semiconductor Group 10-1 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 S0CON (FFB0H / D8H) 15 14 13 12 11 10 9 8 S0 S0 S0R S0LB BRS ODD rw rw rw rw SFR 7 6 5 4 S0 S0 S0OE S0FE S0PE OEN FEN rw rw rw rw rw S0 S0 PEN REN rw rw Reset Value: 0000H 3 S0 STP rw 2 1 S0M rw 0 Bit S0M Function ASC0 Mode Control 000: 8-bit data 001: 8-bit data 010: Reserved. Do not use this combination! 011: 7-bit data + parity 100: 9-bit data 101: 8-bit data + wake up bit 110: Reserved. Do not use this combination! 111: 8-bit data + parity Number of Stop Bits Selection 0: One stop bit 1: Two stop bits synchronous operation async. operation async. operation async. operation async. operation async. operation async. operation S0STP S0REN Receiver Enable Bit 0: Receiver disabled 1: Receiver enabled (Reset by hardware after reception of byte in synchronous mode) Parity Check Enable Bit 0: Ignore parity 1: Check parity Framing Check Enable Bit 0: Ignore framing errors 1: Check framing errors Overrun Check Enable Bit 0: Ignore overrun errors 1: Check overrun errors Parity Error Flag Set by hardware on a parity error (S0PEN='1'). Must be reset by software. Framing Error Flag Set by hardware on a framing error (S0FEN='1'). Must be reset by software. Overrun Error Flag Set by hardware on an overrun error (S0OEN='1'). Must be reset by software. Parity Selection Bit 0: Even parity (parity bit set on odd number of `1's in data) 1: Odd parity (parity bit set on even number of `1's in data) async. operation S0PEN S0FEN async. operation S0OEN S0PE S0FE S0OE S0ODD Semiconductor Group 10-2 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 Bit S0BRS Function Baudrate Selection Bit 0: Divide clock by reload-value + constant (depending on mode) 1: Additionally reduce serial clock to 2/3rd LoopBack Mode Enable Bit 0: Standard transmit/receive mode 1: Loopback mode enabled Baudrate Generator Run Bit 0: Baudrate generator disabled (ASC0 inactive) 1: Baudrate generator enabled S0LB S0R A transmission is started by writing to the Transmit Buffer register S0TBUF (via an instruction or a PEC data transfer). Only the number of data bits which is determined by the selected operating mode will actually be transmitted, ie. bits written to positions 9 through 15 of register S0TBUF are always insignificant. After a transmission has been completed, the transmit buffer register is cleared to 0000H. Data transmission is double-buffered, so a new character may be written to the transmit buffer register, before the transmission of the previous character is complete. This allows the transmission of characters back-to-back without gaps. Data reception is enabled by the Receiver Enable Bit S0REN. After reception of a character has been completed, the received data and, if provided by the selected operating mode, the received parity bit can be read from the (read-only) Receive Buffer register S0RBUF. Bits in the upper half of S0RBUF which are not valid in the selected operating mode will be read as zeros. Data reception is double-buffered, so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register. In all modes, receive buffer overrun error detection can be selected through bit S0OEN. When enabled, the overrun error status flag S0OE and the error interrupt request flag S0EIR will be set when the receive buffer register has not been read by the time reception of a second character is complete. The previously received character in the receive buffer is overwritten. The Loop-Back option (selected by bit S0LB) allows the data currently being transmitted to be received simultaneously in the receive buffer. This may be used to test serial communication routines at an early stage without having to provide an external network. In loop-back mode the alternate input/output functions of the Port 3 pins are not necessary. Note: Serial data transmission or reception is only possible when the Baud Rate Generator Run Bit S0R is set to `1'. Otherwise the serial interface is idle. Do not program the mode control field S0M in register S0CON to one of the reserved combinations to avoid unpredictable behaviour of the serial interface. Semiconductor Group 10-3 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 10.1 Asynchronous Operation Asynchronous mode supports full-duplex communication, where both transmitter and receiver use the same data frame format and the same baud rate. Data is transmitted on pin TXD0/P3.10 and received on pin RXD0/P3.11. These signals are alternate functions of Port 3 pins. Figure 10-2 Asynchronous Mode of Serial Channel ASC0 Semiconductor Group 10-4 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 Asynchronous Data Frames 8-bit data frames either consist of 8 data bits D7...D0 (S0M='001B'), or of 7 data bits D6...D0 plus an automatically generated parity bit (S0M='011B'). Parity may be odd or even, depending on bit S0ODD in register S0CON. An even parity bit will be set, if the modulo-2-sum of the 7 data bits is `1'. An odd parity bit will be cleared in this case. Parity checking is enabled via bit S0PEN (always OFF in 8-bit data mode). The parity error flag S0PE will be set along with the error interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit S0RBUF.7. Start D0 Bit (LSB) D1 D2 D3 D4 D5 D6 (1st) D7 / Stop Parity Bit 2nd Stop Bit Figure 10-3 Asynchronous 8-bit Data Frames 9-bit data frames either consist of 9 data bits D8...D0 (S0M='100B'), of 8 data bits D7...D0 plus an automatically generated parity bit (S0M='111B') or of 8 data bits D7...D0 plus wake-up bit (S0M='101B'). Parity may be odd or even, depending on bit S0ODD in register S0CON. An even parity bit will be set, if the modulo-2-sum of the 8 data bits is `1'. An odd parity bit will be cleared in this case. Parity checking is enabled via bit S0PEN (always OFF in 9-bit data and wake-up mode). The parity error flag S0PE will be set along with the error interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit S0RBUF.8. In wake-up mode received frames are only transferred to the receive buffer register, if the 9th bit (the wake-up bit) is `1'. If this bit is `0', no receive interrupt request will be activated and no data will be transferred. This feature may be used to control communication in multi-processor system: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the additional 9th bit is a '1' for an address byte and a '0' for a data byte, so no slave will be interrupted by a data 'byte'. An address 'byte' will interrupt all slaves (operating in 8-bit data + wakeup bit mode), so each slave can examine the 8 LSBs of the received character (the address). The addressed slave will switch to 9-bit data mode (eg. by clearing bit S0M.0), which enables it to also receive the data bytes that will be coming (having the wake-up bit cleared). The slaves that were not being addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes. Semiconductor Group 10-5 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 Start D0 Bit (LSB) D1 D2 D3 D4 D5 D6 D7 9th Bit (1st) Stop Bit 2nd Stop Bit * Data Bit D8 * Parity * Wake-up Bit Figure 10-4 Asynchronous 9-bit Data Frames Asynchronous transmission begins at the next overflow of the divide-by-16 counter (see figure above), provided that S0R is set and data has been loaded into S0TBUF. The transmitted data frame consists of three basic elements: * the start bit * the data field (8 or 9 bits, LSB first, including a parity bit, if selected) * the delimiter (1 or 2 stop bits) Data transmission is double buffered. When the transmitter is idle, the transmit data loaded into S0TBUF is immediately moved to the transmit shift register thus freeing S0TBUF for the next data to be sent. This is indicated by the transmit buffer interrupt request flag S0TBIR being set. S0TBUF may now be loaded with the next data, while transmission of the previous one is still going on. The transmit interrupt request flag S0TIR will be set before the last bit of a frame is transmitted, ie. before the first or the second stop bit is shifted out of the transmit shift register. The transmitter output pin TXD0/P3.10 must be configured for alternate data output, ie. P3.10='1' and DP3.10='1'. Semiconductor Group 10-6 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 Asynchronous reception is initiated by a falling edge (1-to-0 transition) on pin RXD0, provided that bits S0R and S0REN are set. The receive data input pin RXD0 is sampled at 16 times the rate of the selected baud rate. A majority decision of the 7th, 8th and 9th sample determines the effective bit value. This avoids erroneous results that may be caused by noise. If the detected value is not a '0' when the start bit is sampled, the receive circuit is reset and waits for the next 1-to-0 transition at pin RXD0. If the start bit proves valid, the receive circuit continues sampling and shifts the incoming data frame into the receive shift register. When the last stop bit has been received, the content of the receive shift register is transferred to the receive data buffer register S0RBUF. Simultaneously, the receive interrupt request flag S0RIR is set after the 9th sample in the last stop bit time slot (as programmed), regardless whether valid stop bits have been received or not. The receive circuit then waits for the next start bit (1-to-0 transition) at the receive data input pin. The receiver input pin RXD0/P3.11 must be configured for input, ie. DP3.11='0'. Asynchronous reception is stopped by clearing bit S0REN. A currently received frame is completed including the generation of the receive interrupt request and an error interrupt request, if appropriate. Start bits that follow this frame will not be recognized. Note: In wake-up mode received frames are only transferred to the receive buffer register, if the 9th bit (the wake-up bit) is `1'. If this bit is `0', no receive interrupt request will be activated and no data will be transferred. Semiconductor Group 10-7 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 10.2 Synchronous Operation Synchronous mode supports half-duplex communication, basically for simple IO expansion via shift registers. Data is transmitted and received via pin RXD0/P3.11, while pin TXD0/P3.10 outputs the shift clock. These signals are alternate functions of Port 3 pins. Synchronous mode is selected with S0M='000B'. 8 data bits are transmitted or received synchronous to a shift clock generated by the internal baud rate generator. The shift clock is only active as long as data bits are transmitted or received. Figure 10-5 Synchronous Mode of Serial Channel ASC0 Semiconductor Group 10-8 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 Synchronous transmission begins within 4 state times after data has been loaded into S0TBUF, provided that S0R is set and S0REN='0' (half-duplex, no reception). Data transmission is double buffered. When the transmitter is idle, the transmit data loaded into S0TBUF is immediately moved to the transmit shift register thus freeing S0TBUF for the next data to be sent. This is indicated by the transmit buffer interrupt request flag S0TBIR being set. S0TBUF may now be loaded with the next data, while transmission of the previous one is still going on. The data bits are transmitted synchronous with the shift clock. After the bit time for the 8th data bit, both pins TXD0 and RXD0 will go high, the transmit interrupt request flag S0TIR is set, and serial data transmission stops. Pin TXD0/P3.10 must be configured for alternate data output, ie. P3.10='1' and DP3.10='1', in order to provide the shift clock. Pin RXD0/P3.11 must also be configured for output (P3.11='1' and DP3.11='1') during transmission. Synchronous reception is initiated by setting bit S0REN='1'. If bit S0R=1, the data applied at pin RXD0 are clocked into the receive shift register synchronous to the clock which is output at pin TXD0. After the 8th bit has been shifted in, the content of the receive shift register is transferred to the receive data buffer S0RBUF, the receive interrupt request flag S0RIR is set, the receiver enable bit S0REN is reset, and serial data reception stops. Pin TXD0/P3.10 must be configured for alternate data output, ie. P3.10='1' and DP3.10='1', in order to provide the shift clock. Pin RXD0/P3.11 must be configured as alternate data input (DP3.11='0'). Synchronous reception is stopped by clearing bit S0REN. A currently received byte is completed including the generation of the receive interrupt request and an error interrupt request, if appropriate. Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission. If a previously received byte has not been read out of the receive buffer register at the time the reception of the next byte is complete, both the error interrupt request flag S0EIR and the overrun error status flag S0OE will be set, provided the overrun check has been enabled by bit S0OEN. Semiconductor Group 10-9 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 10.3 Hardware Error Detection Capabilities To improve the safety of serial data exchange, the serial channel ASC0 provides an error interrupt request flag, which indicates the presence of an error, and three (selectable) error status flags in register S0CON, which indicate which error has been detected during reception. Upon completion of a reception, the error interrupt request flag S0EIR will be set simultaneously with the receive interrupt request flag S0RIR, if one or more of the following conditions are met: * If the framing error detection enable bit S0FEN is set and any of the expected stop bits is not high, the framing error flag S0FE is set, indicating that the error interrupt request is due to a framing error (Asynchronous mode only). If the parity error detection enable bit S0PEN is set in the modes where a parity bit is received, and the parity check on the received data bits proves false, the parity error flag S0PE is set, indicating that the error interrupt request is due to a parity error (Asynchronous mode only). If the overrun error detection enable bit S0OEN is set and the last character received was not read out of the receive buffer by software or PEC transfer at the time the reception of a new frame is complete, the overrun error flag S0OE is set indicating that the error interrupt request is due to an overrun error (Asynchronous and synchronous mode). * * 10.4 ASC0 Baud Rate Generation The serial channel ASC0 has its own dedicated 13-bit baud rate generator with 13-bit reload capability, allowing baud rate generation independent of the GPT timers. The baud rate generator is clocked with the CPU clock divided by 2 (10 MHz @ 20 MHz CPU clock). The timer is counting downwards and can be started or stopped through the Baud Rate Generator Run Bit S0R in register S0CON. Each underflow of the timer provides one clock pulse to the serial channel. The timer is reloaded with the value stored in its 13-bit reload register each time it underflows. The resulting clock is again divided according to the operating mode and controlled by the Baudrate Selection Bit S0BRS. If S0BRS='1', the clock signal is additionally divided to 2/3rd of its frequency (see formulas and table). So the baud rate of ASC0 is determined by the CPU clock, the reload value, the value of S0BRS and the operating mode (asynchronous or synchronous). Register S0BG is the dual-function Baud Rate Generator/Reload register. Reading S0BG returns the content of the timer (bits 15...13 return zero), while writing to S0BG always updates the reload register (bits 15...13 are insiginificant). An auto-reload of the timer with the content of the reload register is performed each time S0BG is written to. However, if S0R='0' at the time the write operation to S0BG is performed, the timer will not be reloaded until the first instruction cycle after S0R='1'. Semiconductor Group 10-10 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 Asynchronous Mode Baud Rates For asynchronous operation, the baud rate generator provides a clock with 16 times the rate of the established baud rate. Every received bit is sampled at the 7th, 8th and 9th cycle of this clock. The baud rate for asynchronous operation of serial channel ASC0 and the required reload value for a given baudrate can be determined by the following formulas: fCPU BAsync = 16 * (2 + 00CFH / 00D0H +0.6 % / -0.1 % Note: The deviation errors given in the table above are rounded. Using a baudrate crystal will provide correct baudrates without deviation errors. Synchronous Mode Baud Rates For synchronous operation, the baud rate generator provides a clock with 4 times the rate of the established baud rate. The baud rate for synchronous operation of serial channel ASC0 can be determined by the following formula: BSync = fCPU 4 * (2 + Semiconductor Group 10-11 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 10.5 ASC0 Interrupt Control Four bit addressable interrupt control registers are provided for serial channel ASC0. Register S0TIC controls the transmit interrupt, S0TBIC controls the transmit buffer interrupt, S0RIC controls the receive interrupt and S0EIC controls the error interrupt of serial channel ASC0. Each interrupt source also has its own dedicated interrupt vector. S0TINT is the transmit interrupt vector, S0TBINT is the transmit interrupt vector, S0RINT is the receive interrupt vector, and S0EINT is the error interrupt vector. The cause of an error interrupt request (framing, parity, overrun error) can be identified by the error status flags in control register S0CON. Note: In contrary to the error interrupt request flag S0EIR, the error status flags S0FE/S0PE/S0OE are not reset automatically upon entry into the error interrupt service routine, but must be cleared by software. S0TIC (FF6CH / B6H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 S0TIR S0TIE rw rw GLVL rw S0RIC (FF6EH / B7H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 S0RIR S0RIE rw rw GLVL rw S0EIC (FF70H / B8H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 S0EIR S0EIE rw rw GLVL rw S0TBIC (F19CH / CEH) 15 14 13 12 11 10 9 ESFR 8 7 6 5 4 ILVL rw S0 S0 TBIR TBIE Reset Value: - - 00H 3 2 1 0 GLVL rw - - - - - - - - rw rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. Semiconductor Group 10-12 The Asynchronous/Synchr. 10Jul97@15:19h Serial Interface / C161 Using the ASC0 Interrupts For normal operation (ie. besides the error interrupt) the ASC0 provides three interrupt requests to control data exchange via this serial channel: * S0TBIR * S0TIR * S0RIR is activated when data is moved from S0TBUF to the transmit shift register. is activated before the last bit of an asynchronous frame is transmitted, or after the last bit of a synchronous frame has been transmitted. is activated when the received frame is moved to S0RBUF. While the task of the receive interrupt handler is quite clear, the transmitter is serviced by two interrupt handlers. This provides advantages for the servicing software. For single transfers is is sufficient to use the transmitter interrupt (S0TIR), which indicates that the previously loaded data has been transmitted, except for the last bit of an asynchronous frame. For multiple back-to-back transfers it is necessary to load the following piece of data at last until the time the last bit of the previous frame has been transmitted. In asynchronous mode this leaves just one bit-time for the handler to respond to the transmitter interrupt request, in synchronous mode it is impossible at all. Using the transmit buffer interrupt (S0TBIR) to reload transmit data gives the time to transmit a complete frame for the service routine, as S0TBUF may be reloaded while the previous data is still being transmitted. Figure 10-6 ASC0 Interrupt Generation As shown in the figure above, S0TBIR is an early trigger for the reload routine, while S0TIR indicates the completed transmission. Software using handshake therefore should rely on S0TIR at the end of a data block to make sure that all data has really been transmitted. Semiconductor Group 10-13 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 11 The High-Speed Synchronous Serial Interface The High-Speed Synchronous Serial Interface SSC provides flexible high-speed serial communication between the C161 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication up to 4 MBaud (@ 16 MHz CPU clock). The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. The high-speed synchronous serial interface can be configured in a very flexible way, so it can be used with other synchronous serial interfaces (eg. the ASC0 in synchronous mode), serve for master/slave or multimaster interconnections or operate compatible with the popular SPI interface. So it can be used to communicate with shift registers (IO expansion), peripherals (eg. EEPROMs etc.) or other controllers (networking). The SSC supports half-duplex and full-duplex communication. Data is transmitted or received on pins MTSR/P3.9 (Master Transmit / Slave Receive) and MRST/P3.8 (Master Receive / Slave Transmit). The clock signal is output or input on pin SCLK/P3.13. These pins are alternate functions of Port 3 pins. Ports & Direction Control Alternate Functions Data Registers Control Registers Interrupt Control ODP3 DP3 P3 SCLK / P3.13 MTSR / P3.9 MRST / P3.8 E SSCBR SSCTB SSCRB E E E SSCCON SSCTIC SSCRIC SSCEIC ODP3 DP3 SSCBR SSCTB SSCTIC Port 3 Open Drain Control Register Port 3 Direction Control Register SSC Baud Rate Generator/Reload Register SSC Transmit Buffer Register (write only) SSC Transmit Interrupt Control Register P3 SSCCON SSCRB SSCRIC SSCEIC Port 3 Data Register SSC Control Register SSC Receive Buffer Register (read only) SSC Receive Interrupt Control Register SSC Error Interrupt Control Register Figure 11-1 SFRs and Port Pins associated with the SSC Semiconductor Group 11-1 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 Figure 11-2 Synchronous Serial Channel SSC Block Diagram The operating mode of the serial channel SSC is controlled by its bit-addressable control register SSCCON. This register serves for two purposes: * during programming (SSC disabled by SSCEN='0') it provides access to a set of control bits, * during operation (SSC enabled by SSCEN='1') it provides access to a set of status flags. Register SSCCON is shown below in each of the two modes. Semiconductor Group 11-2 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 SSCCON (FFB2H / D9H) 15 14 13 12 11 10 9 8 SSC SSC EN=0 MS rw rw SSC SSC AREN BEN rw rw SFR 7 6 SSC PO rw 5 SSC PH rw 4 SSC HB rw SSC SSC SSC PEN REN TEN rw rw rw Reset Value: 0000H 3 2 1 0 SSCBM rw Bit SSCBM Function (Programming Mode, SSCEN = `0') SSC Data Width Selection 0: Reserved. Do not use this combination. 1...15 : Transfer Data Width is 2...16 bit ( SSCHB SSCPH SSCPO SSCTEN SSCREN SSCPEN SSCBEN SSCAREN SSCMS SSCEN Semiconductor Group 11-3 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 SSCCON (FFB2H / D9H) 15 14 13 12 11 10 9 8 SSC SSC EN=1 MS rw rw SSC SSC BSY BE rw rw SFR 7 6 5 4 SSC SSC SSC PE RE TE rw rw rw Reset Value: 0000H 3 2 1 0 SSCBC r Bit SSCBC SSCTE SSCRE SSCPE SSCBE Function (Operating Mode, SSCEN = `1') SSC Bit Count Field Shift counter is updated with every shifted bit. Do not write to!!! SSC Transmit Error Flag 1: Transfer starts with the slave's transmit buffer not being updated SSC Receive Error Flag 1: Reception completed before the receive buffer was read SSC Phase Error Flag 1: Received data changes around sampling clock edge SSC Baudrate Error Flag 1: More than factor 2 or 0.5 between Slave's actual and expected baudrate SSC Busy Flag Set while a transfer is in progress. Do not write to!!! SSC Master Select Bit 0: Slave Mode. Operate on shift clock received via SCLK. 1: Master Mode. Generate shift clock and output it via SCLK. SSC Enable Bit = `1' Transmission and reception enabled. Access to status flags and M/S control. SSCBSY SSCMS SSCEN Note: * The target of an access to SSCCON (control bits or flags) is determined by the state of SSCEN prior to the access, ie. writing C057H to SSCCON in programming mode (SSCEN='0') will initialize the SSC (SSCEN was `0') and then turn it on (SSCEN='1'). * When writing to SSCCON, make sure that reserved locations receive zeros. The shift register of the SSC is connected to both the transmit pin and the receive pin via the pin control logic (see block diagram). Transmission and reception of serial data is synchronized and takes place at the same time, ie. the same number of transmitted bits is also received. Transmit data is written into the Transmit Buffer SSCTB. It is moved to the shift register as soon as this is empty. An SSC-master (SSCMS='1') immediately begins transmitting, while an SSC-slave (SSCMS='0') will wait for an active shift clock. When the transfer starts, the busy flag SSCBSY is set and a transmit interrupt request (SSCTIR) will be generated to indicate that SSCTB may be reloaded again. When the programmed number of bits (2...16) has been transferred, the contents of the shift register are moved to the Receive Buffer SSCRB and a receive interrupt request (SSCRIR) will be generated. If no further transfer is to take place (SSCTB is empty), SSCBSY will be cleared at the same time. Software should not modify SSCBSY, as this flag is hardware controlled. Note: Only one SSC (etc.) can be master at a given time. Semiconductor Group 11-4 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 The transfer of serial data bits can be programmed in many respects: * the data width can be chosen from 2 bits to 16 bits * transfer may start with the LSB or the MSB * the shift clock may be idle low or idle high * data bits may be shifted with the leading or trailing edge of the clock signal * the baudrate may be set from 122 Bd up to 4 MBd (@ 16 MHz CPU clock) * the shift clock can be generated (master) or received (slave) This allows the adaptation of the SSC to a wide range of applications, where serial data transfer is required. The Data Width Selection supports the transfer of frames of any length, from 2-bit "characters" up to 16-bit "characters". Starting with the LSB (SSCHB='0') allows communication eg. with ASC0 devices in synchronous mode (C166 family) or 8051 like serial interfaces. Starting with the MSB (SSCHB='1') allows operation compatible with the SPI interface. Regardless which data width is selected and whether the MSB or the LSB is transmitted first, the transfer data is always right aligned in registers SSCTB and SSCRB, with the LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the internal shift register logic. The unselected bits of SSCTB are ignored, the unselected bits of SSCRB will be not valid and should be ignored by the receiver service routine. The Clock Control allows the adaptation of transmit and receive behaviour of the SSC to a variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out transmit data, while the other clock edge is used to latch in receive data. Bit SSCPH selects the leading edge or the trailing edge for each function. Bit SSCPO selects the level of the clock line in the idle state. So for an idlehigh clock the leading edge is a falling one, a 1-to-0 transition. The figure below is a summary. Figure 11-3 Serial Clock Phase and Polarity Options Semiconductor Group 11-5 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 11.1 Full-Duplex Operation The different devices are connected through three lines. The definition of these lines is always determined by the master: The line connected to the master's data output pin MTSR is the transmit line, the receive line is connected to its data input line MRST, and the clock line is connected to pin SCLK. Only the device selected for master operation generates and outputs the serial clock on pin SCLK. All slaves receive this clock, so their pin SCLK must be switched to input mode (DP3.13='0'). The output of the master's shift register is connected to the external transmit line, which in turn is connected to the slaves' shift register input. The output of the slaves' shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave. The external connections are hard-wired, the function and direction of these pins is determined by the master or slave operation of the individual device. Note: The shift direction shown in the figure applies for MSB-first operation as well as for LSB-first operation. When initializing the devices in this configuration, select one device for master operation (SSCMS='1'), all others must be programmed for slave operation (SSCMS='0'). Initialization includes the operating mode of the device's SSC and also the function of the respective port lines (see "Port Control"). Figure 11-4 SSC Full Duplex Configuration Semiconductor Group 11-6 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration. During a transfer each slave shifts out data from its shift register. There are two ways to avoid collisions on the receive line due to different slave data: Only one slave drives the line, ie. enables the driver of its MRST pin. All the other slaves have to program there MRST pins to input. So only one slave can put its data onto the master's receive line. Only receiving of data from the master is possible. The master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. The selected slave then switches its MRST line to output, until it gets a deselection signal or command. The slaves use open drain output on MRST. This forms a Wired-AND connection. The receive line needs an external pullup in this case. Corruption of the data on the receive line sent by the selected slave is avoided, when all slaves which are not selected for transmission to the master only send ones (`1'). Since this high level is not actively driven onto the line, but only held through the pullup device, the selected slave can pull this line actively to a low level when transmitting a zero bit. The master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. After performing all necessary initializations of the SSC, the serial interfaces can be enabled. For a master device, the alternate clock line will now go to its programmed polarity. The alternate data line will go to either '0' or '1', until the first transfer will start. After a transfer the alternate data line will always remain at the logic level of the last transmitted data bit. When the serial interfaces are enabled, the master device can initiate the first data transfer by writing the transmit data into register SSCTB. This value is copied into the shift register (which is assumed to be empty at this time), and the selected first bit of the transmit data will be placed onto the MTSR line on the next clock from the baudrate generator (transmission only starts, if SSCEN='1'). Depending on the selected clock phase, also a clock pulse will be generated on the SCLK line. With the opposite clock edge the master at the same time latches and shifts in the data detected at its input line MRST. This "exchanges" the transmit data with the receive data. Since the clock line is connected to all slaves, their shift registers will be shifted synchronously with the master's shift register, shifting out the data contained in the registers, and shifting in the data detected at the input line. After the preprogrammed number of clock pulses (via the data width selection) the data transmitted by the master is contained in all slaves' shift registers, while the master's shift register holds the data of the selected slave. In the master and all slaves the content of the shift register is copied into the receive buffer SSCRB and the receive interrupt flag SSCRIR is set. A slave device will immediately output the selected first bit (MSB or LSB of the transfer data) at pin MRST, when the content of the transmit buffer is copied into the slave's shift register. It will not wait for the next clock from the baudrate generator, as the master does. The reason for this is that, depending on the selected clock phase, the first clock edge generated by the master may be already used to clock in the first data bit. So the slave's first data bit must already be valid at this time. Semiconductor Group 11-7 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 Note: On the SSC always a transmission and a reception takes place at the same time, regardless whether valid data has been transmitted or received. This is different eg. from asynchronous reception on ASC0. The initialization of the SCLK pin on the master requires some attention in order to avoid undesired clock transitions, which may disturb the other receivers. The state of the internal alternate output lines is '1' as long as the SSC is disabled. This alternate output signal is ANDed with the respective port line output latch. Enabling the SSC with an idle-low clock (SSCPO='0') will drive the alternate data output and (via the AND) the port pin SCLK immediately low. To avoid this, use the following sequence: * select the clock idle level (SSCPO='x') * load the port output latch with the desired clock idle level (P3.13='x') * switch the pin to output (DP3.13='1') * enable the SSC (SSCEN='1') * if SSCPO='0': enable alternate data output (P3.13='1') The same mechanism as for selecting a slave for transmission (separate select lines or special commands) may also be used to move the role of the master to another device in the network. In this case the previous master and the future master (previous slave) will have to toggle their operating mode (SSCMS) and the direction of their port pins (see description above). 11.2 Half Duplex Operation In a half duplex configuration only one data line is necessary for both receiving and transmitting of data. The data exchange line is connected to both pins MTSR and MRST of each device, the clock line is connected to the SCLK pin. The master device controls the data transfer by generating the shift clock, while the slave devices receive it. Due to the fact that all transmit and receive pins are connected to the one data exchange line, serial data may be moved between arbitrary stations. Similar to full duplex mode there are two ways to avoid collisions on the data exchange line: * only the transmitting device may enable its transmit pin driver * the non-transmitting devices use open drain output and only send ones. Since the data inputs and outputs are connected together, a transmitting device will clock in its own data at the input pin (MRST for a master device, MTSR for a slave). By these means any corruptions on the common data exchange line are detected, where the received data is not equal to the transmitted data. Semiconductor Group 11-8 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 Figure 11-5 SSC Half Duplex Configuration Continuous Transfers When the transmit interrupt request flag is set, it indicates that the transmit buffer SSCTB is empty and ready to be loaded with the next transmit data. If SSCTB has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the next transmission will start without any additional delay. On the data line there is no gap between the two successive frames. Eg. two byte transfers would look the same as one word transfer. This feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer. It is just a matter of software, how long a total data frame length can be. This option can also be used eg. to interface to byte-wide and word-wide devices on the same serial bus. Note: Of course, this can only happen in multiples of the selected basic data width, since it would require disabling/enabling of the SSC to reprogram the basic data width on-the-fly. Semiconductor Group 11-9 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 Port Control The SSC uses three pins of Port 3 to communicate with the external world. Pin P3.13/SCLK serves as the clock line, while pins P3.8/MRST (Master Receive / Slave Transmit) and P3.9/MTSR (Master Transmit / Slave Receive) serve as the serial data input/output lines. The operation of these pins depends on the selected operating mode (master or slave). In order to enable the alternate output functions of these pins instead of the general purpose IO operation, the respective port latches have to be set to '1', since the port latch outputs and the alternate output lines are ANDed. When an alternate data output line is not used (function disabled), it is held at a high level, allowing IO operations via the port latch. The direction of the port lines depends on the operating mode. The SSC will automatically use the correct alternate input or output line of the ports when switching modes. The direction of the pins, however, must be programmed by the user, as shown in the tables. Using the open drain output feature helps to avoid bus contention problems and reduces the need for hardwired hand-shaking or slave select lines. In this case it is not always necessary to switch the direction of a port pin. The table below summarizes the required values for the different modes and pins. Pin Master Mode Function P3.13 / SCLK Serial Clock Output P3.9 / MTSR P3.8 / MRST Serial Data Output Serial Data Input Port Latch Direction P3.13='1' P3.9='1' P3.8='x' Slave Mode Function Port Latch Direction P3.13='x' P3.9='x' P3.8='1' DP3.13='0' DP3.9='0' DP3.8='1' DP3.13='1' Serial Clock Input DP3.9='1' DP3.8='0' Serial Data Input Serial Data Output Note: In the table above, an 'x' means that the actual value is irrelevant in the respective mode, however, it is recommended to set these bits to '1', so they are already in the correct state when switching between master and slave mode. 11.3 Baud Rate Generation The serial channel SSC has its own dedicated 16-bit baud rate generator with 16-bit reload capability, allowing baud rate generation independent from the timers. The baud rate generator is clocked with the CPU clock divided by 2 (8 MHz @ 16 MHz CPU clock). The timer is counting downwards and can be started or stopped through the global enable bit SSCEN in register SSCCON. Register SSCBR is the dual-function Baud Rate Generator/Reload register. Reading SSCBR, while the SSC is enabled, returns the content of the timer. Reading SSCBR, while the SSC is disabled, returns the programmed reload value. In this mode the desired reload value can be written to SSCBR. Note: Never write to SSCBR, while the SSC is enabled. Semiconductor Group 11-10 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 The formulas below calculate either the resulting baud rate for a given reload value, or the required reload value for a given baudrate: fCPU BSSC = 2 * ( Baud Rate Reserved. Use a reload value > 0. 4 2.67 2 1.6 1.0 100 10 1.0 122.1 MBaud MBaud MBaud MBaud MBaud KBaud KBaud KBaud Baud Bit Time --250 375 500 625 1 10 100 1 8.2 --ns ns ns ns s s s ms ms Reload Value 0000H 0001H 0002H 0003H 0004H 0007H 004FH 031FH 1F3FH FFFFH Note: The content of SSCBR must be > 0. Semiconductor Group 11-11 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 11.4 Error Detection Mechanisms The SSC is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes, while Transmit Error and Baudrate Error only apply to slave mode. When an error is detected, the respective error flag is set. When the corresponding Error Enable Bit is set, also an error interrupt request will be generated by setting SSCEIR (see figure below). The error interrupt handler may then check the error flags to determine the cause of the error interrupt. The error flags are not reset automatically (like SSCEIR), but rather must be cleared by software after servicing. This allows servicing of some error conditions via interrupt, while the others may be polled by software. Note: The error interrupt handler must clear the associated (enabled) errorflag(s) to prevent repeated interrupt requests. A Receive Error (Master or Slave mode) is detected, when a new data frame is completely received, but the previous data was not read out of the receive buffer register SSCRB. This condition sets the error flag SSCRE and, when enabled via SSCREN, the error interrupt request flag SSCEIR. The old data in the receive buffer SSCRB will be overwritten with the new value and is unretrievably lost. A Phase Error (Master or Slave mode) is detected, when the incoming data at pin MRST (master mode) or MTSR (slave mode), sampled with the same frequency as the CPU clock, changes between one sample before and two samples after the latching edge of the clock signal (see "Clock Control"). This condition sets the error flag SSCPE and, when enabled via SSCPEN, the error interrupt request flag SSCEIR. A Baud Rate Error (Slave mode) is detected, when the incoming clock signal deviates from the programmed baud rate by more than 100%, ie. it either is more than double or less than half the expected baud rate. This condition sets the error flag SSCBE and, when enabled via SSCBEN, the error interrupt request flag SSCEIR. Using this error detection capability requires that the slave's baud rate generator is programmed to the same baud rate as the master device. This feature detects false additional, or missing pulses on the clock line (within a certain frame). Note: If this error condition occurs and bit SSCAREN='1', an automatic reset of the SSC will be performed in case of this error. This is done to reinitialize the SSC, if too few or too many clock pulses have been detected. Semiconductor Group 11-12 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 A Transmit Error (Slave mode) is detected, when a transfer was initiated by the master (shift clock gets active), but the transmit buffer SSCTB of the slave was not updated since the last transfer. This condition sets the error flag SSCTE and, when enabled via SSCTEN, the error interrupt request flag SSCEIR. If a transfer starts while the transmit buffer is not updated, the slave will shift out the 'old' contents of the shift register, which normally is the data received during the last transfer. This may lead to the corruption of the data on the transmit/receive line in half-duplex mode (open drain configuration), if this slave is not selected for transmission. This mode requires that slaves not selected for transmission only shift out ones, ie. their transmit buffers must be loaded with 'FFFF H' prior to any transfer. Note: A slave with push/pull output drivers, which is not selected for transmission, will normally have its output drivers switched. However, in order to avoid possible conflicts or misinterpretations, it is recommended to always load the slave's transmit buffer prior to any transfer. Figure 11-6 SSC Error Interrupt Control Semiconductor Group 11-13 The High-Speed 10Jul97@15:19h Synchronous Serial Interface / C161 11.5 SSC Interrupt Control Three bit addressable interrupt control registers are provided for serial channel SSC. Register SSCTIC controls the transmit interrupt, SSCRIC controls the receive interrupt and SSCEIC controls the error interrupt of serial channel SSC. Each interrupt source also has its own dedicated interrupt vector. SCTINT is the transmit interrupt vector, SCRINT is the receive interrupt vector, and SCEINT is the error interrupt vector. The cause of an error interrupt request (receive, phase, baudrate, transmit error) can be identified by the error status flags in control register SSCCON. Note: In contrary to the error interrupt request flag SSCEIR, the error status flags SSCxE are not reset automatically upon entry into the error interrupt service routine, but must be cleared by software. SSCTIC (FF72H / B9H) 15 14 13 12 11 10 9 8 SFR 7 SSC TIR 6 SSC TIE rw 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 GLVL rw - - - - - - - - rw SSCRIC (FF74H / BAH) 15 14 13 12 11 10 9 8 SFR 7 SSC RIR 6 SSC RIE rw 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 GLVL rw - - - - - - - - rw SSCEIC (FF76H / BBH) 15 14 13 12 11 10 9 8 SFR 7 SSC EIR 6 SSC EIE rw 5 4 ILVL rw Reset Value: - - 00H 3 2 1 0 GLVL rw - - - - - - - - rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. Semiconductor Group 11-14 10Jul97@15:19h The Watchdog Timer (WDT) / C161 12 The Watchdog Timer (WDT) To allow recovery from software or hardware failure, the C161 provides a Watchdog Timer. If the software fails to service this timer before an overflow occurs, an internal reset sequence will be initiated. This internal reset will also pull the RSTOUT pin low, which also resets the peripheral hardware, which might be the cause for the malfunction. When the watchdog timer is enabled and the software has been designed to service it regularly before it overflows, the watchdog timer will supervise the program execution, as it only will overflow if the program does not progress properly. The watchdog timer will also time out, if a software error was due to hardware related failures. This prevents the controller from malfunctioning for longer than a user-specified time. The watchdog timer provides two registers: a read-only timer register that contains the current count, and a control register for initialization. Reset Indication Pin Data Registers Control Registers RSTOUT WDT WDTCON Figure 12-1 SFRs and Port Pins associated with the Watchdog Timer The watchdog timer is a 16-bit up counter which can be clocked with the CPU clock (fCPU) either divided by 2 or divided by 128. This 16-bit timer is realized as two concatenated 8-bit timers (see figure below). The upper 8 bits of the watchdog timer can be preset to a user-programmable value via a watchdog service access in order to vary the watchdog expire time. The lower 8 bits are reset on each service access. Figure 12-2 Watchdog Timer Block Diagram Semiconductor Group 12-1 10Jul97@15:19h The Watchdog Timer (WDT) / C161 Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT, which is a non-bitaddressable read-only register. The operation of the Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register WDTCON. This register specifies the reload value for the high byte of the timer, selects the input clock prescaling factor and provides a flag that indicates a watchdog timer overflow. WDTCON (FFAEH / D7H) 15 14 13 12 11 10 9 8 SFR 7 6 5 4 - Reset Value: 000XH 3 2 1 0 WDT WDT R IN r rw WDTREL rw Bit WDTIN Function Watchdog Timer Input Frequency Selection `0': Input frequency is fCPU / 2 `1': Input frequency is fCPU / 128 Watchdog Timer Reset Indication Flag Set by the watchdog timer on an overflow. Cleared by a hardware reset or by the SRVWDT instruction. Watchdog Timer Reload Value (for the high byte) WDTR WDTREL Note: The reset value will be 0002 H, if the reset was triggered by the watchdog timer (overflow). It will be 0000H otherwise. After any software reset, external hardware reset (see note), or watchdog timer reset, the watchdog timer is enabled and starts counting up from 0000 H with the frequency fCPU/2. The input frequency may be switched to fCPU/128 by setting bit WDTIN. The watchdog timer can be disabled via the instruction DISWDT (Disable Watchdog Timer). Instruction DISWDT is a protected 32-bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT (End of Initialization) or the SRVWDT (Service Watchdog Timer) instruction. Either one of these instructions disables the execution of DISWDT. When the watchdog timer is not disabled via instruction DISWDT, it will continue counting up, even during Idle Mode. If it is not serviced via the instruction SRVWDT by the time the count reaches FFFFH the watchdog timer will overflow and cause an internal reset. This reset will pull the external reset indication pin RSTOUT low. It differs from a software or external hardware reset in that bit WDTR (Watchdog Timer Reset Indication Flag) of register WDTCON will be set. A hardware reset or the SRVWDT instruction will clear this bit. Bit WDTR can be examined by software in order to determine the cause of the reset. A watchdog reset will also complete a running external bus cycle before starting the internal reset sequence if this bus cycle does not use READY or samples READY active (low) after the programmed waitstates. Otherwise the external bus cycle will be aborted. Note: After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled. Semiconductor Group 12-2 10Jul97@15:19h The Watchdog Timer (WDT) / C161 To prevent the watchdog timer from overflowing, it must be serviced periodically by the user software. The watchdog timer is serviced with the instruction SRVWDT, which is a protected 32-bit instruction. Servicing the watchdog timer clears the low byte and reloads the high byte of the watchdog time register WDT with the preset value in bit field WDTREL, which is the high byte of register WDTCON. Servicing the watchdog timer will also reset bit WDTR. After being serviced the watchdog timer continues counting up from the value ( The time period for an overflow of the watchdog timer is programmable in two ways: * the input frequency to the watchdog timer can be selected via bit WDTIN in register WDTCON to be either fCPU/2 or fCPU/128. * the reload value WDTREL for the high byte of WDT can be programmed in register WDTCON. The period PWDT between servicing the watchdog timer and the next overflow can therefore be determined by the following formula: PWDT = 2(1 + The table below marks the possible ranges for the watchdog time which can be achieved using a CPU clock of 20 MHz. Some numbers are rounded to 3 significant digits. Reload value in WDTREL FFH 00H Prescaler for fCPU 2 (WDTIN = `0') 25.6 s 6.55 ms 128 (WDTIN = `1') 1.6 ms 419 ms Note: For safety reasons, the user is advised to rewrite WDTCON each time before the watchdog timer is serviced. Semiconductor Group 12-3 10Jul97@15:19h The Bootstrap Loader / C161 13 The Bootstrap Loader The built-in bootstrap loader of the C161 provides a mechanism to load the startup program, which is executed after reset, via the serial interface. In this case no external (ROM) memory or an internal ROM is required for the initialization code starting at location 00'0000H. Note: The built-in bootstrap loader is not available in the C161V. The bootstrap loader moves code/data into the internal RAM, but it is also possible to transfer data via the serial interface into an external RAM using a second level loader routine. ROM memory (internal or external) is not necessary. However, it may be used to provide lookup tables or may provide "core-code", ie. a set of general purpose subroutines, eg. for IO operations, number crunching, system initialization, etc. BSL initialization time, > 2 s @ fCPU = 20 MHz. Zero byte (1 start bit, eight `0' data bits, 1 stop bit), sent by host. 3) Identification byte, sent by C161. 4) 32 bytes of code / data, sent by host. 5) Caution: TxD0 is only driven a certain time after reception of the zero byte (2.5 s @ fCPU = 20 MHz). 6) Internal Boot ROM. 1) 2) Figure 13-1 Bootstrap Loader Sequence The Bootstrap Loader may be used to load the complete application software into ROMless systems, it may load temporary software into complete systems for testing or calibration, it may also be used to load a programming routine for Flash devices. The BSL mechanism may be used for standard system startup as well as only for special occasions like system maintenance (firmware update) or end-of-line programming or testing. Semiconductor Group 13-1 10Jul97@15:19h The Bootstrap Loader / C161 Entering the Bootstrap Loader The C161 enters BSL mode, if pin P0L.4 is sampled low at the end of a hardware reset. In this case the built-in bootstrap loader is activated independent of the selected bus mode. The bootstrap loader code is stored in a special Boot-ROM, no part of the standard mask ROM or Flash memory area is required for this. After entering BSL mode and the respective initialization the C161 scans the RXD0 line to receive a zero byte, ie. one start bit, eight `0' data bits and one stop bit. From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock, initializes the serial interface ASC0 accordingly and switches pin TxD0 to output. Using this baudrate, an identification byte is returned to the host that provides the loaded data. This identification byte identifies the device to be bootet. The following codes are defined: 8xC166: 55H C165: B5H C167: C5H (previous versions returned A5H). When the C161 has entered BSL mode, the following configuration is automatically set (values that deviate from the normal reset values, are marked): Watchdog Timer: Context Pointer CP: Stack Pointer SP: Register S0CON: Register S0BG: Disabled FA00H FA40H 8011H acc. to `00' byte Register SYSCON: Register STKUN: Register STKOV: Register BUSCON0: P3.10 / TXD0: DP3.10: 0E00H FA40H FA0CH 0<->C acc. to startup config. `1' `1' Other than after a normal reset the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin TXD0 is configured as output, so the C161 can return the identification byte. Note: Even if the internal ROM is enabled, no code can be executed out of it. The hardware that activates the BSL during reset may be a simple pull-down resistor on P0L.4 for systems that use this feature upon every hardware reset. You may want to use a switchable solution (via jumper or an external signal) for systems that only temporarily use the bootstrap loader. Figure 13-2 Hardware Provisions to Activate the BSL Semiconductor Group 13-2 10Jul97@15:19h The Bootstrap Loader / C161 After sending the identification byte the ASC0 receiver is enabled and is ready to receive the initial 32 bytes from the host. A half duplex connection is therefore sufficient to feed the BSL. Memory Configuration after Reset The configuration (ie. the accessibility) of the C161's memory areas after reset in Bootstrap-Loader mode differs from the standard case. Pin EA is not evaluated when BSL mode is selected, and accesses to the internal ROM area are partly redirected, while the C161 is in BSL mode (see table below). All code fetches are made from the special Boot-ROM, while data accesses read from the internal user ROM. Data accesses will return undefined values on ROMless devices. Note: The code in the Boot-ROM is not an invariant feature of the C161. User software should not try to execute code from the internal ROM area while the BSL mode is still active, as these fetches will be redirected to the Boot-ROM. The Boot-ROM will also "move" to segment 1, when the internal ROM area is mapped to segment 1. 16 MBytes 255 16 MBytes 255 16 MBytes 255 Depends on reset config. 1 (EA, P0) int. RAM 0 user ROM access to external bus 1 disabled int. RAM 0 user ROM Boot-ROM Boot-ROM access to external bus 1 enabled int. RAM 0 user ROM access to int. ROM enabled access to int. ROM enabled Depends on reset config. BSL mode active EA pin Code fetch from internal ROM area Data fetch from internal ROM area Yes (P0L.4='0') high Boot-ROM access User ROM access Yes (P0L.4='0') low Boot-ROM access User ROM access No (P0L.4='1') acc. to application User ROM access User ROM access Semiconductor Group 13-3 10Jul97@15:19h The Bootstrap Loader / C161 Loading the Startup Code After sending the identification byte the BSL enters a loop to receive 32 bytes via ASC0. These bytes are stored sequentially into locations 00'FA40H through 00'FA5FH of the internal RAM. So up to 16 instructions may be placed into the RAM area. To execute the loaded code the BSL then jumps to location 00'FA40H, ie. the first loaded instruction. The bootstrap loading sequence is now terminated, the C161 remains in BSL mode, however. Most probably the initially loaded routine will load additional code or data, as an average application is likely to require substantially more than 16 instructions. This second receive loop may directly use the pre-initialized interface ASC0 to receive data and store it to arbitrary user-defined locations. This second level of loaded code may be the final application code. It may also be another, more sophisticated, loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data. It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory. This process may go through several iterations or may directly execute the final application. In all cases the C161 will still run in BSL mode, ie. with the watchdog timer disabled and limited access to the internal ROM area. All code fetches from the internal ROM area (00'0000H...00'7FFFH or 01'0000H...01'7FFFH, if mapped to segment 1) are redirected to the special Boot-ROM. Data fetches access will access the internal ROM of the C161, if any is available, but will return undefined data on ROMless devices. Exiting Bootstrap Loader Mode In order to execute a program in normal mode, the BSL mode must be terminated first. The C161 exits BSL mode upon a software reset (ignores the level on P0L.4) or a hardware reset (P0L.4 must be high then!). After a reset the C161 will start executing from location 00'0000H of the internal ROM or the external memory, as programmed via pin EA. Choosing the Baudrate for the BSL The calculation of the serial baudrate for ASC0 from the length of the first zero byte that is received, allows the operation of the bootstrap loader of the C161 with a wide range of baudrates. However, the upper and lower limits have to be kept, in order to insure proper data transfer. BC161 = -----------------------------------------32 ( S0BRL + 1 ) f CPU The C161 uses timer T6 to measure the length of the initial zero byte. The quantization uncertainty of this measurement implies the first deviation from the real baudrate, the next deviation is implied by the computation of the S0BRL reload value from the timer contents. The formula below shows the association: T6 - 36 S0BRL = -----------------72 , 9 f CPU T6 = -- --------------4 B Host Semiconductor Group 13-4 10Jul97@15:19h The Bootstrap Loader / C161 For a correct data transfer from the host to the C161 the maximum deviation between the internal initialized baudrate for ASC0 and the real baudrate of the host should be below 2.5%. The deviation (FB, in percent) between host baudrate and C161 baudrate can be calculated via the formula below: FB B Contr - B Host = --------------------------------------- 100 % , B Contr F B 2,5 % Note: Function (FB) does not consider the tolerances of oscillators and other devices supporting the serial communication. This baudrate deviation is a nonlinear function depending on the CPU clock and the baudrate of the host. The maxima of the function (F B) increase with the host baudrate due to the smaller baudrate prescaler factors and the implied higher quantization error (see figure below). Figure 13-3 Baudrate deviation between host and C161 The minimum baudrate (BLow in the figure above) is determined by the maximum count capacity of timer T6, when measuring the zero byte, ie. it depends on the CPU clock. Using the maximum T6 count 216 in the formula the minimum baudrate for fCPU=20 MHz is 687 Baud. The lowest standard baudrate in this case would be 1200 Baud. Baudrates below BLow would cause T6 to overflow. In this case ASC0 cannot be initialized properly. The maximum baudrate (BHigh in the figure above) is the highest baudrate where the deviation still does not exceed the limit, ie. all baudrates between BLow and BHigh are below the deviation limit. The maximum standard baudrate that fulfills this requirement is 19200 Baud. Higher baudrates, however, may be used as long as the actual deviation does not exceed the limit. A certain baudrate (marked I) in the figure) may eg. violate the deviation limit, while an even higher baudrate (marked II) in the figure) stays very well below it. This depends on the host interface. Semiconductor Group 13-5 10Jul97@15:19h System Reset / C161 14 System Reset The internal system reset function provides initialization of the C161 into a defined default state and is invoked either by asserting a hardware reset signal on pin RSTIN (Hardware Reset Input), upon the execution of the SRST instruction (Software Reset) or by an overflow of the watchdog timer. Whenever one of these conditions occurs, the microcontroller is reset into its predefined default state through an internal reset procedure. When a reset is initiated, pending internal hold states are cancelled and the current internal access cycle (if any) is completed. An external bus cycle is aborted, except for a watchdog reset (see description). After that the bus pin drivers and the IO pin drivers are switched off (tristate). RSTOUT is activated depending on the reset source. The internal reset procedure requires 516 CPU clock cycles (32.25 s @ 16 MHz CPU clock) in order to perform a complete reset sequence. This 516 cycle reset sequence is started upon a watchdog timer overflow, a SRST instruction or when the reset input signal RSTIN is latched low (hardware reset). The internal reset condition is active at least for the duration of the reset sequence and then until the RSTIN input is inactive. When this internal reset condition is removed (reset sequence complete and RSTIN inactive), the reset configuration is latched from PORT0, and pins ALE, RD and WR are driven to their inactive levels. Note: Bit ADP which selects the Adapt mode is latched with the rising edge of RSTIN. After the internal reset condition is removed, the microcontroller will start program execution from memory location 00'0000H in code segment zero. This start location will typically hold a branch instruction to the start of a software initialization routine for the application specific configuration of peripherals and CPU Special Function Registers. C161 Figure 14-1 External Reset Circuitry Semiconductor Group 14-1 10Jul97@15:19h System Reset / C161 Hardware Reset A hardware reset is triggered when the reset input signal RSTIN is latched low. To ensure the recognition of the RSTIN signal (latching), it must be held low for at least 2 CPU clock cycles. Also shorter RSTIN pulses may trigger a hardware reset, if they coincide with the latch's sample point. However, it is recommended to keep RSTIN low for ca. 1 ms. After the reset sequence has been completed, the RSTIN input is sampled. When the reset input signal is active at that time the internal reset condition is prolonged until RSTIN gets inactive. During a hardware reset the PORT0 inputs for the reset configuration need some time to settle on the required levels, especially if the hardware reset aborts a read operation form an external peripheral. During this settling time the configuration may intermittently be wrong. The input RSTIN provides an internal pullup device equalling a resistor of 50 K to 150 K (the minimum reset time must be determined by the lowest value). Simply connecting an external capacitor is sufficient for an automatic power-on reset (see b) in figure above). RSTIN may also be connected to the output of other logic gates (see a) in figure above). Note: A power-on reset requires an active time of two reset sequences (1036 CPU clock cycles) after a stable clock signal is available (about 10...50 ms to allow the on-chip oscillator to stabilize). Software Reset The reset sequence can be triggered at any time via the protected instruction SRST (Software Reset). This instruction can be executed deliberately within a program, eg. to leave bootstrap loader mode, or upon a hardware trap that reveals a system failure. Note: A software reset disregards the configuration of P0L.5...P0L.0. Watchdog Timer Reset When the watchdog timer is not disabled during the initialization or serviced regularly during program execution is will overflow and trigger the reset sequence. Other than hardware and software reset the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY at all, or if READY is sampled active (low) after the programmed waitstates. When READY is sampled inactive (high) after the programmed waitstates the running external bus cycle is aborted. Then the internal reset sequence is started. Note: A watchdog reset disregards the configuration of P0L.5...P0L.0. The watchdog reset cannot occur while the C161 is in bootstrap loader mode! Semiconductor Group 14-2 10Jul97@15:19h System Reset / C161 The C161's Pins after Reset After the reset sequence the different groups of pins of the C161 are activated in different ways depending on their function. Bus and control signals are activated immediately after the reset sequence according to the configuration latched from PORT0, so either external accesses can takes place or the external control signals are inactive. The general purpose IO pins remain in input mode (high impedance) until reprogrammed via software (see figure below). The RSTOUT pin remains active (low) until the end of the initialization routine (see description). When the internal reset condition is prolongued by RSTIN, the activation of the output signals is delayed until the end of the internal reset condition. 1) Current bus cycle is completed or aborted. 2) Switches asynchronously with RSTIN, synchronously upon software or watchdog reset. 3) The reset condition ends here. The C161 starts program execution. 4) Activation of the IO pins is controlled by software. 5) Execution of the EINIT instruction. 6) The shaded area designates the internal reset sequence, which starts after synchronization of RSTIN. Figure 14-2 Reset Input and Output Signals Semiconductor Group 14-3 10Jul97@15:19h System Reset / C161 Reset Output Pin The RSTOUT pin is dedicated to generate a reset signal for the system components besides the controller itself. RSTOUT will be driven active (low) at the begin of any reset sequence (triggered by hardware, the SRST instruction or a watchdog timer overflow). RSTOUT stays active (low) beyond the end of the internal reset sequence until the protected EINIT (End of Initialization) instruction is executed (see figure above). This allows the complete configuration of the controller including its on-chip peripheral units before releasing the reset signal for the external peripherals of the system. Note: RSTOUT will float as long as pins P0L.0 and P0L.1 select emulation mode or adapt mode. Watchdog Timer Operation after Reset The watchdog timer starts running after the internal reset has completed. It will be clocked with the internal system clock divided by 2 (10 MHz @ fCPU=20 MHz), and its default reload value is 00H, so a watchdog timer overflow will occur 131072 CPU clock cycles (6.55 ms @ fCPU=20 MHz) after completion of the internal reset, unless it is disabled, serviced or reprogrammed meanwhile. When the system reset was caused by a watchdog timer overflow, the WDTR (Watchdog Timer Reset Indication) flag in register WDTCON will be set to '1'. This indicates the cause of the internal reset to the software initialization routine. WDTR is reset to '0' by an external hardware reset or by servicing the watchdog timer. After the internal reset has completed, the operation of the watchdog timer can be disabled by the DISWDT (Disable Watchdog Timer) instruction. This instruction has been implemented as a protected instruction. For further security, its execution is only enabled in the time period after a reset until either the SRVWDT (Service Watchdog Timer) or the EINIT instruction has been executed. Thereafter the DISWDT instruction will have no effect. Reset Values for the C161 Registers During the reset sequence the registers of the C161 are preset with a default value. Most SFRs, including system registers and peripheral control and data registers, are cleared to zero, so all peripherals and the interrupt system are off or idle after reset. A few exceptions to this rule provide a first pre-initialization, which is either fixed or controlled by input pins. DPP1: DPP2: DPP3: CP: STKUN: STKOV: SP: WDTCON: S0RBUF: SSCRB: SYSCON: BUSCON0: RP0H: ONES: 0001H (points to data page 1) 0002H (points to data page 2) 0003H (points to data page 3) FC00H FC00H FA00H FC00H 0002H, if reset was triggered by a watchdog timer overflow, 0000 H otherwise XXH (undefined) XXXXH (undefined) 0XX0H (set according to reset configuration) 0XX0H (set according to reset configuration) XXH (reset levels of P0H) FFFFH (fixed value) Semiconductor Group 14-4 10Jul97@15:19h System Reset / C161 The Internal RAM after Reset The contents of the internal RAM are not affected by a system reset. However, after a power-on reset, the contents of the internal RAM are undefined. This implies that the GPRs (R15...R0) and the PEC source and destination pointers (SRCP7...SRCP0, DSTP7...DSTP0) which are mapped into the internal RAM are also unchanged after a warm reset, software reset or watchdog reset, but are undefined after a power-on reset. Ports and External Bus Configuration during Reset During the internal reset sequence all of the C161's port pins are configured as inputs by clearing the associated direction registers, and their pin drivers are switched to the high impedance state. This ensures that the C161 and external devices will not try to drive the same pin to different levels. Pin ALE is held low through an internal pulldown, and pins RD and WR are held high through internal pullups. Also the pins selected for CS output will be pulled high. The registers SYSCON and BUSCON0 are initialized according to the configuration selected via PORT0. When an external start is selected (pin EA='0'): * the Bus Type field (BTYP) in register BUSCON0 is initialized according to P0L.7 and P0L.6 * bit BUSACT0 in register BUSCON0 is set to `1' * bit ALECTL0 in register BUSCON0 is set to `1' * bit ROMEN in register SYSCON will be cleared to `0' * bit BYTDIS in register SYSCON is set according to the data bus width When an internal start is selected (pin EA='1'): * register BUSCON0 is cleared to 0000H * bit ROMEN in register SYSCON will be set to `1' * bit BYTDIS in register SYSCON is cleared, ie. BHE is enabled The other bits of register BUSCON0, and the other BUSCON registers are cleared. This default initialization selects the slowest possible external accesses using the configured bus type. The Ready function is disabled at the end of the internal system reset. When the internal reset has completed, the configuration of PORT0, PORT1, Port 4, Port 6 and of the BHE signal (High Byte Enable, alternate function of P3.12) depends on the bus type which was selected during reset. When any of the external bus modes was selected during reset, PORT0 (and PORT1) will operate in the selected bus mode. Port 4 will output the selected number of segment address lines (all zero after reset) and Port 6 will drive the selected number of CS lines (CS0 will be `0', while the other active CS lines will be `1'). When no memory accesses above 64 K are to be performed, segmentation may be disabled. When the on-chip bootstrap loader was activated during reset, pin TxD0 (alternate function of P3.10) will be switched to output mode after the reception of the zero byte. All other pins remain in the high-impedance state until they are changed by software or peripheral operation. Semiconductor Group 14-5 10Jul97@15:19h System Reset / C161 Application-Specific Initialization Routine After the internal reset condition is removed the C161 fetches the first instruction from location 00'0000H, which is the first vector in the trap/interrupt vector table, the reset vector. 4 words (locations 00'0000H through 00'0007H) are provided in this table to start the initialization after reset. As a rule, this location holds a branch instruction to the actual initialization routine that may be located anywhere in the address space. Note: When the Bootstrap Loader Mode was activated during a hardware reset the C161 does not fetch instructions from location 00'0000 H but rather expects data via serial interface ASC0. If single chip mode is selected during reset, the first instruction is fetched from the internal ROM. Otherwise it is fetched from external memory. When internal ROM access is enabled after reset in single chip mode (bit ROMEN='1' in register SYSCON), the software initialization routine may enable and configure the external bus interface before the execution of the EINIT instruction. When external access is enabled after reset, it may be desirable to reconfigure the external bus characteristics, because the SYSCON register is initialized during reset to the slowest possible memory configuration. To decrease the number of instructions required to initialize the C161, each peripheral is programmed to a default configuration upon reset, but is disabled from operation. These default configurations can be found in the descriptions of the individual peripherals. During the software design phase, portions of the internal memory space must be assigned to register banks and system stack. When initializing the stack pointer (SP) and the context pointer (CP), it must be ensured that these registers are initialized before any GPR or stack operation is performed. This includes interrupt processing, which is disabled upon completion of the internal reset, and should remain disabled until the SP is initialized. Note: Traps (incl. NMI) may occur, even though the interrupt system is still disabled. In addition, the stack overflow (STKOV) and the stack underflow (STKUN) registers should be initialized. After reset, the CP, SP, and STKUN registers all contain the same reset value 00'FC00H, while the STKOV register contains 00'FA00H. With the default reset initialization, 256 words of system stack are available, where the system stack selected by the SP grows downwards from 00'FBFEH, while the register bank selected by the CP grows upwards from 00'FC00H. Based on the application, the user may wish to initialize portions of the internal memory before normal program operation. Once the register bank has been selected by programming the CP register, the desired portions of the internal memory can easily be initialized via indirect addressing. At the end of the initialization, the interrupt system may be globally enabled by setting bit IEN in register PSW. Care must be taken not to enable the interrupt system before the initialization is complete. The software initialization routine should be terminated with the EINIT instruction. This instruction has been implemented as a protected instruction. Execution of the EINIT instruction disables the action of the DISWDT instruction, disables write accesses to register SYSCON (see note) and causes the RSTOUT pin to go high. This signal can be used to indicate the end of the initialization routine and the proper operation of the microcontroller to external hardware. Note: All configurations regarding register SYSCON (enable CLKOUT, stacksize, etc.) must be selected before the execution of EINIT. Semiconductor Group 14-6 10Jul97@15:19h System Reset / C161 System Startup Configuration Although most of the programmable features of the C161 are either selected during the initialization phase or repeatedly during program execution, there are some features that must be selected earlier, because they are used for the first access of the program execution (eg. internal or external start selected via EA). These selections are made during reset via the pins of PORT0, which are read at the end of the internal reset sequence. During reset internal pullup devices are active on the PORT0 lines, so their input level is high, if the respective pin is left open, or is low, if the respective pin is connected to an external pulldown device. With the coding of the selections, as shown below, in many cases the default option, ie. high level, can be used. The value on the upper byte of PORT0 (P0H) is latched into register RP0H upon reset, the value on the lower byte (P0L) directly influences the BUSCON0 register (bus mode) or the internal control logic of the C161. Figure 14-3 PORT0 Configuration during Reset The pins that control the operation of the internal control logic and the reserved pins are evaluated only during a hardware triggered reset sequence. The pins that influence the configuration of the C161 are evaluated during any reset sequence, ie. also during software and watchdog timer triggered resets. The configuration via P0H is latched in register RP0H for subsequent evaluation by software. Register RP0H is described in chapter "The External Bus Interface". Note: The reserved pins (marked "R") must remain high during reset in order to ensure proper operation of the C161. The load on those pins must be small enough for the internal pullup device to keep their level high, or external pullup devices must ensure the high level. Semiconductor Group 14-7 10Jul97@15:19h System Reset / C161 The following describes the different selections that are offered for reset configuration. The default modes refer to pins at high level, ie. without external pulldown devices connected. Please also consider the note (above) on reserved pins. Emulation Mode Pin P0L.0 (EMU) selects the Emulation Mode, when low during reset. This mode allows the access to integrated XBUS peripherals via the external bus interface pins in application specific versions of the C161. In addition also the RSTOUT pin floats to tristate rather than be driven low. When the emulation mode has been latched the CLKOUT output is automatically enabled. This mode is used for special emulator purposes and is of no use in basic C161 devices, so in this case P0L.0 should be held high. Default: Emulation Mode is off. Note: In emulation mode the direct drive clock option is selected with P0.15 (P0H.7) = '1'. Adapt Mode Pin P0L.1 (ADP) selects the Adapt Mode, when low during reset. In this mode the C161 goes into a passive state, which is similar to its state during reset. The pins of the C161 float to tristate or are deactivated via internal pullup/pulldown devices, as described for the reset state. In addition also the RSTOUT pin floats to tristate rather than be driven low, and the on-chip oscillator is switched off. This mode allows switching a C161 that is mounted to a board virtually off, so an emulator may control the board's circuitry, even though the original C161 remains in its place. The original C161 also may resume to control the board after a reset sequence with P0L.1 high. Default: Adapt Mode is off. Note: When XTAL1 is fed by an external clock generator (while XTAL2 is left open), this clock signal may also be used to drive the emulator device. However, if a crystal is used, the emulator device's oscillator can use this crystal only, if at least XTAL2 of the original device is disconnected from the circuitry (the output XTAL2 will still be active in Adapt Mode). Bootstrap Loader Mode Pin P0L.4 (BSL) activates the on-chip bootstrap loader, when low during reset. The bootstrap loader allows moving the start code into the internal RAM of the C161 via the serial interface ASC0. The C161 will remain in bootstrap loader mode until a hardware reset with P0L.4 high or a software reset. Default: The C161 starts fetching code from location 00'0000H, the bootstrap loader is off. Note: The built-in bootstrap loader is not available in the C161V. Semiconductor Group 14-8 10Jul97@15:19h System Reset / C161 External Bus Type Pins P0L.7 and P0L.6 (BUSTYP) select the external bus type during reset, if an external start is selected via pin EA. This allows the configuration of the external bus interface of the C161 even for the first code fetch after reset. The two bits are copied into bit field BTYP of register BUSCON0. P0L.7 controls the data bus width, while P0L.6 controls the address output (multiplexed or demultiplexed). This bit field may be changed via software after reset, if required. BTYP Encoding 00 01 10 11 External Data Bus Width 8-bit Data 8-bit Data 16-bit Data 16-bit Data External Address Bus Mode Demultiplexed Addresses Multiplexed Addresses Demultiplexed Addresses Multiplexed Addresses PORT0 and PORT1 are automatically switched to the selected bus mode. In multiplexed bus modes PORT0 drives both the 16-bit intra-segment address and the output data, while PORT1 remains in high impedance state as long as no demultiplexed bus is selected via one of the BUSCON registers. In demultiplexed bus modes PORT1 drives the 16-bit intra-segment address, while PORT0 or P0L (according to the selected data bus width) drives the output data. For a 16-bit data bus BHE is automatically enabled, for an 8-bit data bus BHE is disabled via bit BYTDIS in register SYSCON. Default: 16-bit data bus with multiplexed addresses. Note: If an internal start is selected via pin EA, these two pins are disregarded and bit field BTYP of register BUSCON0 is cleared. Demultiplexed bus modes are not supported on the C161V (shaded rows in above table). Write Configuration Pin P0H.0 (WRC) selects the initial operation of the control pins WR and BHE during reset. When high, this pin selects the standard function, ie. WR control and BHE. When low, it selects the alternate configuration, ie. WRH and WRL. Thus even the first access after a reset can go to a memory controlled via WRH and WRL. This bit is latched in register RP0H and its inverted value is copied into bit WRCFG in register SYSCON. Default: Standard function (WR control and BHE). Semiconductor Group 14-9 10Jul97@15:19h System Reset / C161 Chip Select Lines Pins P0H.2 and P0H.1 (CSSEL) define the number of active chip select signals during reset. This allows the selection which pins of Port 6 drive external CS signals and which are used for general purpose IO. The two bits are latched in register RP0H. Default: All 4 chip select lines active (CS3...CS0). CSSEL 11 10 01 00 Chip Select Lines Four: None Two: Three: CS1...CS0 CS2...CS0 CS3...CS0 Note Default without pull-downs Port 6 pins free for IO C161K / C161O C161O C161O Note: The selected number of CS signals cannot be changed via software after reset. The maximum number of selectable CS lines depends on the device. Segment Address Lines Pins P0H.4 and P0H.3 (SALSEL) define the number of active segment address lines during reset. This allows the selection which pins of Port 4 drive address lines and which are used for general purpose IO. The two bits are latched in register RP0H. Depending on the system architecture the required address space is chosen and accessible right from the start, so the initialization routine can directly access all locations without prior programming. The required pins of Port 4 are automatically switched to address output mode. SALSEL 11 10 01 00 Segment Address Lines Two: Six: None Four: A19...A16 A17...A16 A21...A16 Directly accessible Address Space 256 4 64 1 KByte (Default without pull-downs) MByte (Maximum) KByte (Minimum) MByte Even if not all segment address lines are enabled on Port 4, the C161 internally uses its complete 24-bit addressing mechanism. This allows the restriction of the width of the effective address bus, while still deriving CS signals from the complete addresses. Default: 2-bit segment address (A17...A16) allowing access to 256 KByte. Note: The selected number of segment address lines cannot be changed via software after reset. Semiconductor Group 14-10 10Jul97@15:19h System Reset / C161 Clock Generation Control Pins P0H.7, P0H.6 and P0H.5 (CLKCFG) select the clock generation mode during reset. The oscillator clock either directly feeds the CPU and peripherals (direct drive) or is divided by 2 (prescaler operation). These bits are latched in register RP0H. C161 Clock Generation Modes Reset Configuration P0.15-13 (P0H.7-5) 1 0 1) CPU Frequency External Clock Input Range 2 to 32 MHz 1 to 16 MHz Notes X X X X fXTAL / 2 fXTAL * 1 Prescaler operation. Default configuration after reset. Direct drive 1) Direct drive: the maximum frequency depends on the duty cycle of the external clock signal. In emulation mode pin P0.15 (P0H.7) is inverted, ie. the configuration '1XX' would select direct drive in emulation mode. Default: Prescaler is active (2:1). Note: Watch the different requirements for frequency and duty cycle of the oscillator input clock for the possible selections. Semiconductor Group 14-11 10Jul97@15:19h Power Reduction Modes / C161 15 Power Reduction Modes Two different power reduction modes with different levels of power reduction have been implemented in the C161, which may be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. In Power Down mode both the CPU and the peripherals are stopped. Power Down mode can only be terminated by a hardware reset. Note: All external bus actions are completed before Idle or Power Down mode is entered. However, Idle or Power Down mode is not entered if READY is enabled, but has not been activated (driven low) during the last bus access. 15.1 Idle Mode The power consumption of the C161 microcontroller can be decreased by entering Idle mode. In this mode all peripherals, including the watchdog timer, continue to operate normally, only the CPU operation is halted. Idle mode is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has been completed. To prevent unintentional entry into Idle mode, the IDLE instruction has been implemented as a protected 32-bit instruction. Idle mode is terminated by interrupt requests from any enabled interrupt source whose individual Interrupt Enable flag was set before the Idle mode was entered, regardless of bit IEN. For a request selected for CPU interrupt service the associated interrupt service routine is entered if the priority level of the requesting source is higher than the current CPU priority and the interrupt system is globally enabled. After the RETI (Return from Interrupt) instruction of the interrupt service routine is executed the CPU continues executing the program with the instruction following the IDLE instruction. Otherwise, if the interrupt request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU immediately resumes normal program execution with the instruction following the IDLE instruction. For a request which was programmed for PEC service a PEC data transfer is performed if the priority level of this request is higher than the current CPU priority and the interrupt system is globally enabled. After the PEC data transfer has been completed the CPU remains in Idle mode. Otherwise, if the PEC request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU does not remain in Idle mode but continues program execution with the instruction following the IDLE instruction. Semiconductor Group 15-1 10Jul97@15:19h Power Reduction Modes / C161 Figure 15-1 Transitions between Idle mode and active mode Idle mode can also be terminated by a Non-Maskable Interrupt, ie. a high to low transition on the NMI pin. After Idle mode has been terminated by an interrupt or NMI request, the interrupt system performs a round of prioritization to determine the highest priority request. In the case of an NMI request, the NMI trap will always be entered. Any interrupt request whose individual Interrupt Enable flag was set before Idle mode was entered will terminate Idle mode regardless of the current CPU priority. The CPU will not go back into Idle mode when a CPU interrupt request is detected, even when the interrupt was not serviced because of a higher CPU priority or a globally disabled interrupt system (IEN='0'). The CPU will only go back into Idle mode when the interrupt system is globally enabled (IEN='1') and a PEC service on a priority level higher than the current CPU level is requested and executed. Note: An interrupt request which is individually enabled and assigned to priority level 0 will terminate Idle mode. The associated interrupt vector will not be accessed, however. The watchdog timer may be used to monitor the Idle mode: an internal reset will be generated if no interrupt or NMI request occurs before the watchdog timer overflows. To prevent the watchdog timer from overflowing during Idle mode it must be programmed to a reasonable time interval before Idle mode is entered. Semiconductor Group 15-2 10Jul97@15:19h Power Reduction Modes / C161 15.2 Power Down Mode To further reduce the power consumption the microcontroller can be switched to Power Down mode. Clocking of all internal blocks is stopped, the contents of the internal RAM, however, are preserved through the voltage supplied via the VCC pins. The watchdog timer is stopped in Power Down mode. This mode can only be terminated by an external hardware reset, ie. by asserting a low level on the RSTIN pin. This reset will initialize all SFRs and ports to their default state, but will not change the contents of the internal RAM. There are two levels of protection against unintentionally entering Power Down mode. First, the PWRDN (Power Down) instruction which is used to enter this mode has been implemented as a protected 32-bit instruction. Second, this instruction is effective only if the NMI (Non Maskable Interrupt) pin is externally pulled low while the PWRDN instruction is executed. The microcontroller will enter Power Down mode after the PWRDN instruction has completed. This feature can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent. The microcontroller will enter the NMI trap routine which can save the internal state into RAM. After the internal state has been saved, the trap routine may set a flag or write a certain bit pattern into specific RAM locations, and then execute the PWRDN instruction. If the NMI pin is still low at this time, Power Down mode will be entered, otherwise program execution continues. During power down the voltage at the VCC pins can be lowered to 2.5 V while the contents of the internal RAM will still be preserved. The initialization routine (executed upon reset) can check the identification flag or bit pattern within RAM to determine whether the controller was initially switched on, or whether it was properly restarted from Power Down mode. Semiconductor Group 15-3 10Jul97@15:19h Power Reduction Modes / C161 15.3 Status of Output Pins during Idle and Power Down Mode During Idle mode the CPU clocks are turned off, while all peripherals continue their operation in the normal way. Therefore all ports pins, which are configured as general purpose output pins, output the last data value which was written to their port output latches. If the alternate output function of a port pin is used by a peripheral, the state of the pin is determined by the operation of the peripheral. Port pins which are used for bus control functions go into that state which represents the inactive state of the respective function (eg. WR), or to a defined state which is based on the last bus access (eg. BHE). Port pins which are used as external address/data bus hold the address/data which was output during the last external memory access before entry into Idle mode under the following conditions: P0H outputs the high byte of the last address if a multiplexed bus mode with 8-bit data bus is used, otherwise P0H is floating. P0L is always floating in Idle mode. PORT1 outputs the lower 16 bits of the last address if a demultiplexed bus mode is used, otherwise the output pins of PORT1 represent the port latch data. Port 4 outputs the segment address for the last access on those pins that were selected during reset, otherwise the output pins of Port 4 represent the port latch data. During Power Down mode the oscillator and the clocks to the CPU and to the peripherals are turned off. Like in Idle mode, all port pins which are configured as general purpose output pins output the last data value which was written to their port output latches. When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks were switched off. Semiconductor Group 15-4 10Jul97@15:19h Power Reduction Modes / C161 The table below summarizes the state of all C161 output pins during Idle and Power Down mode. C161 Idle Mode Output Pin(s) No external bus ALE RD, WR RSTOUT P0L P0H PORT1 Port 4 BHE CSx Other Port Output Pins Note: 1) Power Down Mode External bus enabled Low High 1) No external bus Low High 1) External bus enabled Low High 1) Low High 1) Port Latch Data Port Latch Data Port Latch Data Port Latch Data Port Latch Data Port Latch Data Floating A15...A8 2) / Float Last Address 3) / Port Latch Data Port Latch Data/ Last segment Last value Last value 4) Port Latch Data Port Latch Data Port Latch Data Port Latch Data Port Latch Data Port Latch Data Floating A15...A8 2) / Float Last Address 3) / Port Latch Data Port Latch Data/ Last segment Last value Last value 4) Port Latch Data / Port Latch Data / Port Latch Data / Port Latch Data / Alternate Function Alternate Function Alternate Function Alternate Function : High if EINIT was executed before entering Idle or Power Down mode, Low otherwise. For multiplexed buses with 8-bit data bus. For demultiplexed buses. 2): 3): 4) : The CS signal that corresponds to the last address remains active (low), all other enabled CS signals remain inactive (high). By accessing an on-chip X-Periperal prior to entering a power save mode all external CS signals can be deactivated. Semiconductor Group 15-5 10Jul97@15:19h System Programming / C161 16 System Programming To aid in software development, a number of features has been incorporated into the instruction set of the C161, including constructs for modularity, loops, and context switching. In many cases commonly used instruction sequences have been simplified while providing greater flexibility. The following programming features help to fully utilize this instruction set. Instructions Provided as Subsets of Instructions In many cases, instructions found in other microcontrollers are provided as subsets of more powerful instructions in the C161. This allows the same functionality to be provided while decreasing the hardware required and decreasing decode complexity. In order to aid assembly programming, these instructions, familiar from other microcontrollers, can be built in macros, thus providing the same names. Directly Substitutable Instructions are instructions known from other microcontrollers that can be replaced by the following instructions of the C161: Substituted Instruction CLR CPLB DEC INC SWAPB Rn Bit Rn Rn Rn C161 Instruction AND BMOVN SUB ADD ROR Rn, #0H Bit, Bit Rn, #1H Rn, #1H Rn, #8H Function Clear register Complement bit Decrement register Increment register Swap bytes within word Modification of System Flags is performed using bit set or bit clear instructions (BSET, BCLR). All bit and word instructions can access the PSW register, so no instructions like CLEAR CARRY or ENABLE INTERRUPTS are required. External Memory Data Access does not require special instructions to load data pointers or explicitly load and store external data. The C161 provides a Von-Neumann memory architecture and its on-chip hardware automatically detects accesses to internal RAM, GPRs, and SFRs. Multiplication and Division Multiplication and division of words and double words is provided through multiple cycle instructions implementing a Booth algorithm. Each instruction implicitly uses the 32-bit register MD (MDL = lower 16 bits, MDH = upper 16 bits). The MDRIU flag (Multiply or Divide Register In Use) in register MDC is set whenever either half of this register is written to or when a multiply/divide instruction is started. It is cleared whenever the MDL register is read. Because an interrupt can be acknowledged before the contents of register MD are saved, this flag is required to alert interrupt routines, which require the use of the multiply/divide hardware, so they can preserve register MD. This register, however, only needs to be saved when an interrupt routine requires use of the MD register and a previous task has not saved the current result. This flag is easily tested by the Jump-on-Bit instructions. Semiconductor Group 16-1 10Jul97@15:19h System Programming / C161 Multiplication or division is simply performed by specifying the correct (signed or unsigned) version of the multiply or divide instruction. The result is then stored in register MD. The overflow flag (V) is set if the result from a multiply or divide instruction is greater than 16 bits. This flag can be used to determine whether both word halfs must be transferred from register MD. The high portion of register MD (MDH) must be moved into the register file or memory first, in order to ensure that the MDRIU flag reflects the correct state. The following instruction sequence performs an unsigned 16 by 16-bit multiplication: ... SAVE: JNB MDRIU, START ;Test if MD was in use. SCXT MDC, #0010H ;Save and clear control register, leaving MDRIU set ;(only required for interrupted multiply/divide instructions) BSET SAVED ;Indicate the save operation PUSH MDH ;Save previous MD contents... PUSH MDL ;...on system stack START: MULU R1, R2 ;Multiply 16*16 unsigned, Sets MDRIU JMPR cc_NV, COPYL ;Test for only 16-bit result MOV R3, MDH ;Move high portion of MD COPYL: MOV R4, MDL ;Move low portion of MD, Clears MDRIU RESTORE: JNB SAVED, DONE ;Test if MD registers were saved POP MDL ;Restore registers POP MDH POP MDC BCLR SAVED ;Multiplication is completed, program continues DONE: ... The above save sequence and the restore sequence after COPYL are only required if the current routine could have interrupted a previous routine which contained a MUL or DIV instruction. Register MDC is also saved because it is possible that a previous routine's Multiply or Divide instruction was interrupted while in progress. In this case the information about how to restart the instruction is contained in this register. Register MDC must be cleared to be correctly initialized for a subsequent multiplication or division. The old MDC contents must be popped from the stack before the RETI instruction is executed. For a division the user must first move the dividend into the MD register. If a 16/16-bit division is specified, only the low portion of register MD must be loaded. The result is also stored into register MD. The low portion (MDL) contains the integer result of the division, while the high portion (MDH) contains the remainder. Semiconductor Group 16-2 10Jul97@15:19h System Programming / C161 The following instruction sequence performs a 32 by 16-bit division: MOV MOV DIV JMPR MOV MOV MDH, R1 MDL, R2 R3 cc_V, ERROR R3, MDH R4, MDL ;Move dividend to MD register. Sets MDRIU ;Move low portion to MD ;Divide 32/16 signed, R3 holds the divisor ;Test for divide overflow ;Move remainder to R3 ;Move integer result to R4. Clears MDRIU Whenever a multiply or divide instruction is interrupted while in progress, the address of the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the interrupting routine is set. When the interrupt routine is exited with the RETI instruction, this bit is implicitly tested before the old PSW is popped from the stack. If MULIP='1' the multiply/divide instruction is re-read from the location popped from the stack (return address) and will be completed after the RETI instruction has been executed. Note: The MULIP flag is part of the context of the interrupted task. When the interrupting routine does not return to the interrupted task (eg. scheduler switches to another task) the MULIP flag must be set or cleared according to the context of the task that is switched to. BCD Calculations No direct support for BCD calculations is provided in the C161. BCD calculations are performed by converting BCD data to binary data, performing the desired calculations using standard data types, and converting the result back to BCD data. Due to the enhanced performance of division instructions binary data is quickly converted to BCD data through division by 10 D. Conversion from BCD data to binary data is enhanced by multiple bit shift instructions. This provides similar performance compared to instructions directly supporting BCD data types, while no additional hardware is required. Semiconductor Group 16-3 10Jul97@15:19h System Programming / C161 16.1 Stack Operations The C161 supports two types of stacks. The system stack is used implicitly by the controller and is located in the internal RAM. The user stack provides stack access to the user in either the internal or external memory. Both stack types grow from high memory addresses to low memory addresses. Internal System Stack A system stack is provided to store return vectors, segment pointers, and processor status for procedures and interrupt routines. A system register, SP, points to the top of the stack. This pointer is decremented when data is pushed onto the stack, and incremented when data is popped. The internal system stack can also be used to temporarily store data or pass it between subroutines or tasks. Instructions are provided to push or pop registers on/from the system stack. However, in most cases the register banking scheme provides the best performance for passing data between multiple tasks. Note: The system stack allows the storage of words only. Bytes must either be converted to words or the respective other byte must be disregarded. Register SP can only be loaded with even byte addresses (The LSB of SP is always '0'). Detection of stack overflow/underflow is supported by two registers, STKOV (Stack Overflow Pointer) and STKUN (Stack Underflow Pointer). Specific system traps (Stack Overflow trap, Stack Underflow trap) will be entered whenever the SP reaches either boundary specified in these registers. The contents of the stack pointer are compared to the contents of the overflow register, whenever the SP is DECREMENTED either by a CALL, PUSH or SUB instruction. An overflow trap will be entered, when the SP value is less than the value in the stack overflow register. The contents of the stack pointer are compared to the contents of the underflow register, whenever the SP is INCREMENTED either by a RET, POP or ADD instruction. An underflow trap will be entered, when the SP value is greater than the value in the stack underflow register. Note: When a value is MOVED into the stack pointer, NO check against the overflow/underflow registers is performed. In many cases the user will place a software reset instruction (SRST) into the stack underflow and overflow trap service routines. This is an easy approach, which does not require special programming. However, this approach assumes that the defined internal stack is sufficient for the current software and that exceeding its upper or lower boundary represents a fatal error. It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack. Only the portion of the system stack currently being used is placed into the internal memory, thus allowing a greater portion of the internal RAM to be used for program, data or register banking. This approach assumes no error but requires a set of control routines (see below). Semiconductor Group 16-4 10Jul97@15:19h System Programming / C161 Circular (virtual) Stack This basic technique allows pushing until the overflow boundary of the internal stack is reached. At this point a portion of the stacked data must be saved into external memory to create space for further stack pushes. This is called "stack flushing". When executing a number of return or pop instructions, the upper boundary (since the stack empties upward to higher memory locations) is reached. The entries that have been previously saved in external memory must now be restored. This is called "stack filling". Because procedure call instructions do not continue to nest infinitely and call and return instructions alternate, flushing and filling normally occurs very infrequently. If this is not true for a given program environment, this technique should not be used because of the overhead of flushing and filling. The basic mechanism is the transformation of the addresses of a virtual stack area, controlled via registers SP, STKOV and STKUN, to a defined physical stack area within the internal RAM via hardware. This virtual stack area covers all possible locations that SP can point to, ie. 00'F000H through 00'FFFEH. STKOV and STKUN accept the same 4 KByte address range. The size of the physical stack area within the internal RAM that effectively is used for standard stack operations is defined via bitfield STKSZ in register SYSCON (see below). The virtual stack addresses are transformed to physical stack addresses by concatenating the significant bits of the stack pointer register SP (see table) with the complementary most significant bits of the upper limit of the physical stack area (00'FBFEH). This transformation is done via hardware (see figure below). The reset values (STKOV=FA00H, STKUN=FC00H, SP=FC00H, STKSZ=000B) map the virtual stack area directly to the physical stack area and allow using the internal system stack without any changes, provided that the 256 word area is not exceeded. Semiconductor Group 16-5 10Jul97@15:19h System Programming / C161 FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 FB80H 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 Phys.A. FB80H 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 FA00H 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 F800H 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 After PUSH FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 Phys.A. FB7EH 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0 64 words Figure 16-1 Physical Stack Address Generation After PUSH FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 FBFEH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 F7FEH 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 256 words Stack Size The following example demonstrates the circular stack mechanism which is also an effect of this virtual stack mapping: First, register R1 is pushed onto the lowest physical stack location according to the selected maximum stack size. With the following instruction, register R2 will be pushed onto the highest physical stack location although the SP is decremented by 2 as for the previous push operation. MOV SP, #0F802H ... PUSH R1 PUSH R2 ; Set SP before last entry of physical stack of 256 words ; (SP) = F802H: Physical stack address = FA02H ; (SP) = F800H: Physical stack address = FA00H ; (SP) = F7FEH: Physical stack address = FBFEH The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning. When flushing and filling the internal stack, this circular stack mechanism only requires to move that portion of stack data which is really to be re-used (ie. the upper part of the defined stack area) instead of the whole stack area. Stack data that remain in the lower part of the internal stack need not be moved by the distance of the space being flushed or filled, as the stack pointer automatically wraps around to the beginning of the freed part of the stack area. Note: This circular stack technique is applicable for stack sizes of 32 to 512 words (STKSZ = `000 B' to `100B'), it does not work with option STKSZ = `111 B', which uses the complete internal RAM for system stack. In the latter case the address transformation mechanism is deactivated. Semiconductor Group 16-6 10Jul97@15:19h System Programming / C161 When a boundary is reached, the stack underflow or overflow trap is entered, where the user moves a predetermined portion of the internal stack to or from the external stack. The amount of data transferred is determined by the average stack space required by routines and the frequency of calls, traps, interrupts and returns. In most cases this will be approximately one quarter to one tenth the size of the internal stack. Once the transfer is complete, the boundary pointers are updated to reflect the newly allocated space on the internal stack. Thus, the user is free to write code without concern for the internal stack limits. Only the execution time required by the trap routines affects user programs. The following procedure initializes the controller for usage of the circular stack mechanism: * Specify the size of the physical system stack area within the internal RAM (bitfield STKSZ in register SYSCON). * Define two pointers, which specify the upper and lower boundary of the external stack. These values are then tested in the stack underflow and overflow trap routines when moving data. * Set the stack overflow pointer (STKOV) to the limit of the defined internal stack area plus six words (for the reserved space to store two interrupt entries). The internal stack will now fill until the overflow pointer is reached. After entry into the overflow trap procedure, the top of the stack will be copied to the external memory. The internal pointers will then be modified to reflect the newly allocated space. After exiting from the trap procedure, the internal stack will wrap around to the top of the internal stack, and continue to grow until the new value of the stack overflow pointer is reached. When the underflow pointer is reached while the stack is meptied the bottom of stack is reloaded from the external memory and the internal pointers are adjusted accordingly. Linear Stack The C161 also offers a linear stack option (STKSZ = `111B'), where the system stack may use the complete internal RAM area. This provides a large system stack without requiring procedures to handle data transfers for a circular stack. However, this method also leaves less RAM space for variables or code. The RAM area that may effectively be consumed by the system stack is defined via the STKUN and STKOV pointers. The underflow and overflow traps in this case serve for fatal error detection only. For the linear stack option all modifiable bits of register SP are used to access the physical stack. Although the stack pointer may cover addresses from 00'F000H up to 00'FFFEH the (physical) system stack must be located within the internal RAM and therefore may only use the address range 00'F600H to 00'FDFEH. It is the user's responsibility to restrict the system stack to the internal RAM range. Note: Avoid stack accesses below the IRAM area (ESFR space and reserved area) and within address range 00'FE00H and 00'FFFEH (SFR space). Otherwise unpredictable results will occur. Semiconductor Group 16-7 10Jul97@15:19h System Programming / C161 User Stacks User stacks provide the ability to create task specific data stacks and to off-load data from the system stack. The user may push both bytes and words onto a user stack, but is responsible for using the appropriate instructions when popping data from the specific user stack. No hardware detection of overflow or underflow of a user stack is provided. The following addressing modes allow implementation of user stacks: [- Rw], Rb or [- Rw], Rw: Pre-decrement Indirect Addressing. Used to push one byte or word onto a user stack. This mode is only available for MOV instructions and can specify any GPR as the user stack pointer. Rb, [Rw+] or Rw, [Rw+]: Post-increment Index Register Indirect Addressing. Used to pop one byte or word from a user stack. This mode is available to most instructions, but only GPRs R0-R3 can be specified as the user stack pointer. Rb, [Rw+] or Rw, [Rw+]: Post-increment Indirect Addressing. Used to pop one byte or word from a user stack. This mode is only available for MOV instructions and can specify any GPR as the user stack pointer. 16.2 Register Banking Register banking provides the user with an extremely fast method to switch user context. A single machine cycle instruction saves the old bank and enters a new register bank. Each register bank may assign up to 16 registers. Each register bank should be allocated during coding based on the needs of each task. Once the internal memory has been partitioned into a register bank space, internal stack space and a global internal memory area, each bank pointer is then assigned. Thus, upon entry into a new task, the appropriate bank pointer is used as the operand for the SCXT (switch context) instruction. Upon exit from a task a simple POP instruction to the context pointer (CP) restores the previous task's register bank. 16.3 Procedure Call Entry and Exit To support modular programming a procedure mechanism is provided to allow coding of frequently used portions of code into subroutines. The CALL and RET instructions store and restore the value of the instruction pointer (IP) on the system stack before and after a subroutine is executed. Procedures may be called conditionally with instructions CALLA or CALLI, or be called unconditionally using instructions CALLR or CALLS. Note: Any data pushed onto the system stack during execution of the subroutine must be popped before the RET instruction is executed. Semiconductor Group 16-8 10Jul97@15:19h System Programming / C161 Passing Parameters on the System Stack Parameters may be passed via the system stack through PUSH instructions before the subroutine is called, and POP instructions during execution of the subroutine. Base plus offset indirect addressing also permits access to parameters without popping these parameters from the stack during execution of the subroutine. Indirect addressing provides a mechanism of accessing data referenced by data pointers, which are passed to the subroutine. In addition, two instructions have been implemented to allow one parameter to be passed on the system stack without additional software overhead. The PCALL (push and call) instruction first pushes the 'reg' operand and the IP contents onto the system stack and then passes control to the subroutine specified by the 'caddr' operand. When exiting from the subroutine, the RETP (return and pop) instruction first pops the IP and then the 'reg' operand from the system stack and returns to the calling program. Cross Segment Subroutine Calls Calls to subroutines in different segments require the use of the CALLS (call inter-segment subroutine) instruction. This instruction preserves both the CSP (code segment pointer) and IP on the system stack. Upon return from the subroutine, a RETS (return from inter-segment subroutine) instruction must be used to restore both the CSP and IP. This ensures that the next instruction after the CALLS instruction is fetched from the correct segment. Note: It is possible to use CALLS within the same segment, but still two words of the stack are used to store both the IP and CSP. Providing Local Registers for Subroutines For subroutines which require local storage, the following methods are provided: Alternate Bank of Registers: Upon entry into a subroutine, it is possible to specify a new set of local registers by executing the SCXT (switch context) instruction. This mechanism does not provide a method to recursively call a subroutine. Saving and Restoring of Registers: To provide local registers, the contents of the registers which are required for use by the subroutine can be pushed onto the stack and the previous values be popped before returning to the calling routine. This is the most common technique used today and it does provide a mechanism to support recursive procedures. This method, however, requires two machine cycles per register stored on the system stack (one cycle to PUSH the register, and one to POP the register). Use of the System Stack for Local Registers: It is possible to use the SP and CP to set up local subroutine register frames. This enables subroutines to dynamically allocate local variables as needed within two machine cycles. A local frame is allocated by simply subtracting the number of required local registers from the SP, and then moving the value of the new SP to the CP. Semiconductor Group 16-9 10Jul97@15:19h System Programming / C161 This operation is supported through the SCXT (switch context) instruction with the addressing mode 'reg, mem'. Using this instruction saves the old contents of the CP on the system stack and moves the value of the SP into CP (see example below). Each local register is then accessed as if it was a normal register. Upon exit from the subroutine, first the old CP must be restored by popping it from the stack and then the number of used local registers must be added to the SP to restore the allocated local space back to the system stack. Note: The system stack is growing downwards, while the register bank is growing upwards. Old SP R4 R3 R2 R1 R0 Old CP Contents Old Stack Area Newly Allocated Register Bank New CP New SP New Stack Area Figure 16-2 Local Registers The software to provide the local register bank for the example above is very compact: After entering the subroutine: SUB SCXT SP, #10D CP, SP ; Free 5 words in the current system stack ; Set the new register bank pointer Before exiting the subroutine: POP ADD CP SP, #10D ; Restore the old register bank ; Release the 5 word of the current system stack Semiconductor Group 16-10 10Jul97@15:19h System Programming / C161 16.4 Table Searching A number of features have been included to decrease the execution time required to search tables. First, branch delays are eliminated by the branch target cache after the first iteration of the loop. Second, in non-sequentially searched tables, the enhanced performance of the ALU allows more complicated hash algorithms to be processed to obtain better table distribution. For sequentially searched tables, the auto-increment indirect addressing mode and the E (end of table) flag stored in the PSW decrease the number of overhead instructions executed in the loop. The two examples below illustrate searching ordered tables and non-ordered tables, respectively: LOOP: MOV R0, #BASE ;Move table base into R0 CMP R1, [R0+] ;Compare target to table entry JMPR cc_SGT, LOOP ;Test whether target has not been found Note: The last entry in the table must be greater than the largest possible target. LOOP: MOV R0, #BASE ;Move table base into R0 CMP R1, [R0+] ;Compare target to table entry JMPR cc_NET, LOOP ;Test whether target is not found AND the end of table... ;...has not been reached. Note: The last entry in the table must be equal to the lowest signed integer (8000H). 16.5 Peripheral Control and Interface All communication between peripherals and the CPU is performed either by PEC transfers to and from internal memory, or by explicitly addressing the SFRs associated with the specific peripherals. After resetting the C161 all peripherals (except the watchdog timer) are disabled and initialized to default values. A desired configuration of a specific peripheral is programmed using MOV instructions of either constants or memory values to specific SFRs. Specific control flags may also be altered via bit instructions. Once in operation, the peripheral operates autonomously until an end condition is reached at which time it requests a PEC transfer or requests CPU servicing through an interrupt routine. Information may also be polled from peripherals through read accesses to SFRs or bit operations including branch tests on specific control bits in SFRs. To ensure proper allocation of peripherals among multiple tasks, a portion of the internal memory has been made bit addressable to allow user semaphores. Instructions have also been provided to lock out tasks via software by setting or clearing user specific bits and conditionally branching based on these specific bits. It is recommended that bit fields in control SFRs are updated using the BFLDH and BFLDL instructions or a MOV instruction to avoid undesired intermediate modes of operation which can occur, when BCLR/BSET or AND/OR instruction sequences are used. Semiconductor Group 16-11 10Jul97@15:19h System Programming / C161 16.6 Floating Point Support All floating point operations are performed using software. Standard multiple precision instructions are used to perform calculations on data types that exceed the size of the ALU. Multiple bit rotate and logic instructions allow easy masking and extracting of portions of floating point numbers. To decrease the time required to perform floating point operations, two hardware features have been implemented in the CPU core. First, the PRIOR instruction aids in normalizing floating point numbers by indicating the position of the first set bit in a GPR. This result can the be used to rotate the floating point result accordingly. The second feature aids in properly rounding the result of normalized floating point numbers through the overflow (V) flag in the PSW. This flag is set when a one is shifted out of the carry bit during shift right operations. The overflow flag and the carry flag are then used to round the floating point result based on the desired rounding algorithm. 16.7 Trap/Interrupt Entry and Exit Interrupt routines are entered when a requesting interrupt has a priority higher than the current CPU priority level. Traps are entered regardless of the current CPU priority. When either a trap or interrupt routine is entered, the state of the machine is preserved on the system stack and a branch to the appropriate trap/interrupt vector is made. All trap and interrupt routines require the use of the RETI (return from interrupt) instruction to exit from the called routine. This instruction restores the system state from the system stack and then branches back to the location where the trap or interrupt occurred. 16.8 Unseparable Instruction Sequences The instructions of the C161 are very efficient (most instructions execute in one machine cycle) and even the multiplication and division are interruptable in order to minimize the response latency to interrupt requests (internal and external). In many microcontroller applications this is vital. Some special occasions, however, require certain code sequences (eg. semaphore handling) to be uninterruptable to function properly. This can be provided by inhibiting interrupts during the respective code sequence by disabling and enabling them before and after the sequence. The necessary overhead may be reduced by means of the ATOMIC instruction which allows locking 1...4 instructions to an unseparable code sequence, during which the interrupt system (standard interrupts and PEC requests) and Class A Traps (NMI, stack overflow/underflow) are disabled. A Class B Trap (illegal opcode, illegal bus access, etc.), however, will interrupt the atomic sequence, since it indicates a severe hardware problem. The interrupt inhibit caused by an ATOMIC instruction gets active immediately, ie. no other instruction will enter the pipeline except the one that follows the ATOMIC instruction, and no interrupt request will be serviced in between. All instructions requiring multiple cycles or hold states are regarded as one instruction in this sense (eg. MUL is one instruction). Any instruction type can be used within an unseparable code sequence. EXAMPLE: ATOMIC MOV MOV MUL MOV #3 R0, #1234H R1, #5678H R0, R1 R2, MDL ; The following 3 instructions are locked (No NOP required) ; Instruction 1 (no other instr. enters the pipeline!) ; Instruction 2 ; Instruction 3: MUL regarded as one instruction ; This instruction is out of the scope ; of the ATOMIC instruction sequence Semiconductor Group 16-12 10Jul97@15:19h System Programming / C161 16.9 Overriding the DPP Addressing Mechanism The standard mechanism to access data locations uses one of the four data page pointers (DPPx), which selects a 16 KByte data page, and a 14-bit offset within this data page. The four DPPs allow immediate access to up to 64 KByte of data. In applications with big data arrays, especially in HLL applications using large memory models, this may require frequent reloading of the DPPs, even for single accesses. The EXTP (extend page) instruction allows switching to an arbitrary data page for 1...4 instructions without having to change the current DPPs. EXAMPLE: EXTP R15, #1 MOV R0, [R14] MOV R1, [R13] ; The override page number is stored in R15 ; The (14-bit) page offset is stored in R14 ; This instruction uses the standard DPP scheme! The EXTS (extend segment) instruction allows switching to a 64 KByte segment oriented data access scheme for 1...4 instructions without having to change the current DPPs. In this case all 16 bits of the operand address are used as segment offset, with the segment taken from the EXTS instruction. This greatly simplifies address calculation with continuous data like huge arrays in "C". EXAMPLE: EXTS #15, #1 MOV R0, [R14] MOV R1, [R13] ; The override seg. is #15 (0F'0000H...0F'FFFFH) ; The (16-bit) segment offset is stored in R14 ; This instruction uses the standard DPP scheme! Note: Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC. Short Addressing in the Extended SFR (ESFR) Space The short addressing modes of the C161 (REG or BITOFF) implicitly access the SFR space. The additional ESFR space would have to be accessed via long addressing modes (MEM or [Rw]). The EXTR (extend register) instruction redirects accesses in short addressing modes to the ESFR space for 1...4 instructions, so the additional registers can be accessed this way, too. The EXTPR and EXTSR instructions combine the DPP override mechanism with the redirection to the ESFR space using a single instruction. Note: Instructions EXTR, EXTPR and EXTSR inhibit interrupts the same way as ATOMIC. The switching to the ESFR area and data page overriding is checked by the development tools or handled automatically. Nested Locked Sequences Each of the described extension instruction and the ATOMIC instruction starts an internal "extension counter" counting the effected instructions. When another extension or ATOMIC instruction is contained in the current locked sequence this counter is restarted with the value of the new instruction. This allows the construction of locked sequences longer than 4 instructions. Note: * Interrupt latencies may be increased when using locked code sequences. * PEC requests are not serviced during idle mode, if the IDLE instruction is part of a locked sequence. Semiconductor Group 16-13 10Jul97@15:19h System Programming / C161 16.10 Handling the Internal ROM The Mask-ROM or Flash versions of the C161 may provide and control a 32 KByte internal ROM area that may store code as well as data. Access to this internal ROM area is controlled during the reset configuration and via software. The ROM area may be mapped to segment 0, to segment 1 or may be disabled at all. Note: The internal ROM area always occupies an address area of 32 KByte, even if the implemented mask ROM or Flash memory is smaller than that (eg. 8 KByte). Of course the total implemented memory may exceed 32 KBytes. ROM Configuration during Reset The control input pin EA (External Access) enables the user to define the address area from which the first instructions after reset are fetched. When EA is low (`0') during reset, the internal ROM area is disabled and the first instructions are fetched from external memory. When EA is high (`1') during reset, the internal ROM area is globally enabled and the first instructions are fetched from the internal ROM. Note: Be sure not to select internal ROM access after reset on ROMless devices. Mapping the Internal ROM Area After reset the internal ROM area is mapped into segment 0, the "system segment" (00'0000H...00'7FFFH) as a default. This is necessary to allow the first instructions to be fetched from locations 00'0000H ff. The ROM area may be mapped to segment 1 (01'0000 H...01'7FFFH) by setting bit ROMS1 in register SYSCON. The internal ROM may now be accessed through the lower half of segment 1, while accesses to segment 0 will now be made to external memory. This adds flexibility to the system software. The interrupt/trap vector table, which uses locations 00'0000 H through 00'01FFH, is now part of the external memory and may therefore be modified, ie. the system software may now change interrupt/trap handlers according to the current condition of the system. The internal ROM can still be used for fixed software routines like IO drivers, math libraries, application specific invariant routines, tables, etc. This combines the advantage of an integrated non-volatile memory with the advantage of a flexible, adaptable software system. Enabling and Disabling the Internal ROM Area After Reset If the internal ROM does not contain an appropriate startup code, the system may be booted from external memory, while the internal ROM is enabled afterwards to provide access to library routines, tables, etc. If the internal ROM only contains the startup code and/or test software, the system may be booted from internal ROM, which may then be disabled, after the software has switched to executing from (eg.) external memory, in order to free the address space occupied by the internal ROM area, which is now unnecessary. Semiconductor Group 16-14 10Jul97@15:19h System Programming / C161 16.11 Pits, Traps and Mines Although handling the internal ROM provides powerful means to enhance the overall performance and flexibility of a system, extreme care must be taken in order to avoid a system crash. Instruction memory is the most crucial resource for the C161 and it must be made sure that it never runs out of it. The following precautions help to take advantage of the methods mentioned above without jeopardizing system security. Internal ROM access after reset: When the first instructions are to be fetched from internal ROM (EA=`1'), the device must contain ROM memory, and the ROM must contain a valid reset vector and valid code at its destination. Mapping the internal ROM to segment 1: Due to instruction pipelining, any new ROM mapping will at the earliest become valid for the second instruction after the instruction which has changed the ROM mapping. To enable accesses to the ROM after mapping a branch to the newly selected ROM area (JMPS) and reloading of all data page pointers is required. This also applies to re-mapping the internal ROM to segment 0. Enabling the internal ROM after reset: When enabling the internal ROM after having booted the system from external memory, note that the C161 will then access the internal ROM using the current segment offset, rather than accessing external memory. Disabling the internal ROM after reset: When disabling the internal ROM after having booted the system from there, note that the C161 will not access external memory before a jump to segment 0 (in this case) is executed. General Rules When mapping the ROM no instruction or data accesses should be made to the internal ROM, otherwise unpredictable results may occur. To avoid these problems, the instructions that configure the internal ROM should be executed from external memory or from the internal RAM. Whenever the internal ROM is disabled, enabled or remapped the DPPs must be explicitly (re)loaded to enable correct data accesses to the internal ROM and/or external memory. Semiconductor Group 16-15 10Jul97@15:19h The Register Set / C161 17 The Register Set This section summarizes all registers, which are implemented in the C161 and explains the description format which is used in the chapters describing the function and layout of the SFRs. For easy reference the registers are ordered according to two different keys (except for GPRs): * Ordered by address, to check which register a given address references, * Ordered by register name, to find the location of a specific register. Register Description Format In the respective chapters the function and the layout of the SFRs is described in a specific format which provides a number of details about the described special function register. The example below shows how to interpret these details. A word register looks like this: REG_NAME (A16H / A8H) 15 res. 14 res. 13 res. 12 res. 11 res. 10 write only w 9 hw bit rw E/SFR 8 read only r 7 std bit rw 6 hw bit rw 5 4 bitfield rw Reset Value: * * * *H 3 2 1 bitfield rw 0 Bit Function bit(field)name Explanation of bit(field)name Description of the functions controlled by this bit(field). A byte register looks like this: REG_NAME (A16H / A8H) 15 14 13 12 11 10 9 E/SFR 8 7 std bit 6 hw bit rw 5 4 Reset Value: - - * *H 3 2 1 0 bitfield rw bitfield rw - - - - - - - - rw Elements: REG_NAME Name of this register A16 / A8 Long 16-bit address / Short 8-bit address SFR/ESFR/XRegRegister space (SFR, ESFR or External/XBUS Register) (* *) * * Register contents after reset 0/1: defined value, 'X': undefined, 'U': unchanged (undefined ('X') after power up) Bits that are set/cleared by hardware are marked with a shaded access box hwbit Semiconductor Group 17-1 10Jul97@15:19h The Register Set / C161 17.1 CPU General Purpose Registers (GPRs) The GPRs form the register bank that the CPU works with. This register bank may be located anywhere within the internal RAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks can only reside within the internal RAM. All GPRs are bit-addressable. Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Physical 8-Bit Address Address (CP) + 0 (CP) + 2 (CP) + 4 (CP) + 6 (CP) + 8 (CP) + 10 (CP) + 12 (CP) + 14 (CP) + 16 (CP) + 18 (CP) + 20 (CP) + 22 (CP) + 24 (CP) + 26 (CP) + 28 (CP) + 30 F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH Description CPU General Purpose (Word) Register R0 CPU General Purpose (Word) Register R1 CPU General Purpose (Word) Register R2 CPU General Purpose (Word) Register R3 CPU General Purpose (Word) Register R4 CPU General Purpose (Word) Register R5 CPU General Purpose (Word) Register R6 CPU General Purpose (Word) Register R7 CPU General Purpose (Word) Register R8 CPU General Purpose (Word) Register R9 CPU General Purpose (Word) Register R10 CPU General Purpose (Word) Register R11 CPU General Purpose (Word) Register R12 CPU General Purpose (Word) Register R13 CPU General Purpose (Word) Register R14 CPU General Purpose (Word) Register R15 Reset Value UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH UUUUH Semiconductor Group 17-2 10Jul97@15:19h The Register Set / C161 The first 8 GPRs (R7...R0) may also be accessed bytewise. Other than with SFRs, writing to a GPR byte does not affect the other byte of the respective GPR. The respective halves of the byte-accessible registers receive special names: Name RL0 RH0 RL1 RH1 RL2 RH2 RL3 RH3 RL4 RH4 RL5 RH5 RL6 RH6 RL7 RH7 Physical 8-Bit Address Address (CP) + 0 (CP) + 1 (CP) + 2 (CP) + 3 (CP) + 4 (CP) + 5 (CP) + 6 (CP) + 7 (CP) + 8 (CP) + 9 (CP) + 10 (CP) + 11 (CP) + 12 (CP) + 13 (CP) + 14 (CP) + 14 F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH Description CPU General Purpose (Byte) Register RL0 CPU General Purpose (Byte) Register RH0 CPU General Purpose (Byte) Register RL1 CPU General Purpose (Byte) Register RH1 CPU General Purpose (Byte) Register RL2 CPU General Purpose (Byte) Register RH2 CPU General Purpose (Byte) Register RL3 CPU General Purpose (Byte) Register RH3 CPU General Purpose (Byte) Register RL4 CPU General Purpose (Byte) Register RH4 CPU General Purpose (Byte) Register RL5 CPU General Purpose (Byte) Register RH5 CPU General Purpose (Byte) Register RL6 CPU General Purpose (Byte) Register RH6 CPU General Purpose (Byte) Register RL7 CPU General Purpose (Byte) Register RH7 Reset Value UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH UUH Semiconductor Group 17-3 10Jul97@15:19h The Register Set / C161 17.2 Special Function Registers ordered by Name The following table lists all SFRs which are implemented in the C161 in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Registers within on-chip X-Peripherals (SSP) are marked with the letter "X" in column "Physical Address". Registers which are unique to specific C161 derivatives are shaded. Name ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 Physical 8-Bit Address Address FE18H FE1AH FE1CH FE1EH 0CH 0DH 0EH 0FH 86H 8AH 8BH 8CH 8DH 25H C5H C6H C7H C8H C9H CAH CBH 08H B5H 04H Description Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register External Interrupt 1 Control Register External Interrupt 2 Control Register External Interrupt 3 Control Register External Interrupt 4 Control Register External Interrupt 5 Control Register External Interrupt 6 Control Register External Interrupt 7 Control Register CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (8 bits, not directly writeable) P0L Direction Control Register P0H Direction Control Register P1L Direction Control Register P1H Direction Control Register Port 2 Direction Control Register Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H FC00H 0000H 0000H 00H 00H 00H 00H 0000H BUSCON0 b FF0CH BUSCON1 b FF14H BUSCON2 b FF16H BUSCON3 b FF18H BUSCON4 b FF1AH CAPREL CC9IC CC10IC CC11IC CC12IC CC13IC CC14IC CC15IC CP CRIC CSP DP0L DP0H DP1L DP1H DP2 FE4AH b FF8AH b FF8CH b FF8EH b FF90H b FF92H b FF94H b FF96H FE10H b FF6AH FE08H b F100H E 80H b F102H E 81H b F104H E 82H b F106H E 83H b FFC2H E1H Semiconductor Group 17-4 10Jul97@15:19h The Register Set / C161 Name DP3 DP4 DP6 DPP0 DPP1 DPP2 DPP3 EXICON MDC MDH MDL ODP2 ODP3 ODP6 ONES P0L P0H P1L P1H P2 P3 P4 P5 P6 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PSW Physical 8-Bit Address Address b FFC6H b FFCAH b FFCEH FE00H FE02H FE04H FE06H b FF0EH FE0CH FE0EH E3H E5H E7H 00H 01H 02H 03H 87H 06H 07H Description Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) CPU Data Page Pointer 3 Register (10 bits) External Interrupt Control Register CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Register (Lower half of PORT0) Port 0 High Register (Upper half of PORT0) Port 1 Low Register (Lower half of PORT1) Port 1 High Register (Upper half of PORT1) Port 2 Register Port 3 Register Port 4 Register (8 bits) Port 5 Register (read only) Port 6 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register CPU Program Status Word Reset Value 0000H 00H 00H 0000H 0001H 0002H 0003H 0000H 0000H 0000H 0000H 0000H 0000H 00H FFFF H 00H 00H 00H 00H 0000H 0000H 00H XXXXH 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H b F1C0H E E0H b F1C2H E E1H b F1C6H E E3H b F1CEH E E7H b FF1EH b FF00H b FF02H b FF04H b FF06H b FFC0H b FFC4H b FFC8H b FFA2H b FFCCH FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH FECEH b FF10H 8FH 80H 81H 82H 83H E0H E2H E4H D1H E6H 60H 61H 62H 63H 64H 65H 66H 67H 88H Semiconductor Group 17-5 10Jul97@15:19h The Register Set / C161 Name RP0H S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR SSCCON SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON T2 T2CON T2IC T3 T3CON T3IC T4 T4CON Physical 8-Bit Address Address b F108H E 84H FEB4H b FFB0H b FF70H FEB2H b FF6EH 5AH D8H B8H 59H B7H Description System Startup Configuration Register (Rd. only) Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer (read only) SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register Reset Value XXH 0000H 0000H 0000H XXXXH 0000H 0000H 0000H 0000H FC00H 0000H 0000H 0000H XXXXH 0000H 0000H 0000H FA00H FC00H 0XX0H1) 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H b F19CH E CEH FEB0H b FF6CH FE12H b FFB2H b FF76H b FF74H b FF72H FE14H FE16H b FF12H FE40H b FF40H b FF60H FE42H b FF42H b FF62H FE44H b FF44H 58H B6H 09H D9H BBH BAH B9H 0AH 0BH 89H 20H A0H B0H 21H A1H B1H 22H A2H F0B4H E 5AH F0B2H E 59H F0B0H E 58H Semiconductor Group 17-6 10Jul97@15:19h The Register Set / C161 Name T4IC T5 T5CON T5IC T6 T6CON T6IC TFR WDT ZEROS Physical 8-Bit Address Address b FF64H FE46H b FF46H b FF66H FE48H b FF48H b FF68H b FFACH FEAEH b FF1CH B2H 23H A3H B3H 24H A4H B4H D6H 57H D7H 8EH Description GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register Constant Value 0's Register (read only) Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 000XH2) 0000H WDTCON b FFAEH Note: The shaded registers are only available in the C161O, not in the C161V and the C161K. 1) 2) The system configuration is selected during reset. Bit WDTR indicates a watchdog timer triggered reset. Semiconductor Group 17-7 10Jul97@15:19h The Register Set / C161 17.3 Registers ordered by Address The following table lists all SFRs which are implemented in the C161 ordered by their physical address. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Registers within on-chip X-Peripherals (SSP) are marked with the letter "X" in column "Physical Address". Registers which are unique to specific C161 derivatives are shaded. Name SSCTB SSCRB SSCBR DP0L DP0H DP1L DP1H RP0H S0TBIC EXICON ODP2 ODP3 ODP6 DPP0 DPP1 DPP2 DPP3 CSP MDH MDL CP SP STKOV STKUN ADDRSEL1 Physical 8-Bit Address Address F0B0H E 58H F0B2H E 59H F0B4H E 5AH b F100H E 80H b F102H E 81H b F104H E 82H b F106H E 83H b F108H E 84H b F19CH E CEH b F1C0H E E0H b F1C2H E E1H b F1C6H E E3H b F1CEH E E7H FE00H FE02H FE04H FE06H FE08H FE0CH FE0EH FE10H FE12H FE14H FE16H FE18H 00H 01H 02H 03H 04H 06H 07H 08H 09H 0AH 0BH 0CH Description SSC Transmit Buffer (write only) SSC Receive Buffer (read only) SSC Baudrate Register P0L Direction Control Register P0H Direction Control Register P1L Direction Control Register P1H Direction Control Register System Startup Configuration Register (Rd. only) Serial Channel 0 Transmit Buffer Interrupt Control Register External Interrupt Control Register Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) CPU Data Page Pointer 3 Register (10 bits) CPU Code Segment Pointer Register (8 bits, not directly writeable) CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word CPU Context Pointer Register CPU System Stack Pointer Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register Address Select Register 1 Reset Value 0000H XXXXH 0000H 00H 00H 00H 00H XXH 0000H 0000H 0000H 0000H 00H 0000H 0001H 0002H 0003H 0000H 0000H 0000H FC00H FC00H FA00H FC00H 0000H Semiconductor Group 17-8 10Jul97@15:19h The Register Set / C161 Name ADDRSEL2 ADDRSEL3 ADDRSEL4 T2 T3 T4 T5 T6 CAPREL WDT S0TBUF S0RBUF S0BG PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 P0L P0H P1L P1H MDC PSW SYSCON Physical 8-Bit Address Address FE1AH FE1CH FE1EH FE40H FE42H FE44H FE46H FE48H FE4AH FEAEH FEB0H FEB2H FEB4H FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH FECEH b FF00H b FF02H b FF04H b FF06H b FF0EH b FF10H b FF12H 0DH 0EH 0FH 20H 21H 22H 23H 24H 25H 57H 58H 59H 5AH 60H 61H 62H 63H 64H 65H 66H 67H 80H 81H 82H 83H 86H 87H 88H 89H 8AH 8BH Description Address Select Register 2 Address Select Register 3 Address Select Register 4 GPT1 Timer 2 Register GPT1 Timer 3 Register GPT1 Timer 4 Register GPT2 Timer 5 Register GPT2 Timer 6 Register GPT2 Capture/Reload Register Watchdog Timer Register (read only) Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Baud Rate Generator Reload Register PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Port 0 Low Register (Lower half of PORT0) Port 0 High Register (Upper half of PORT0) Port 1 Low Register (Lower half of PORT1) Port 1 High Register (Upper half of PORT1) Bus Configuration Register 0 CPU Multiply Divide Control Register CPU Program Status Word CPU System Configuration Register Bus Configuration Register 1 Bus Configuration Register 2 Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H XXXXH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 0000H 0XX0H1) 0000H 0000H BUSCON0 b FF0CH BUSCON1 b FF14H BUSCON2 b FF16H Semiconductor Group 17-9 10Jul97@15:19h The Register Set / C161 Name Physical 8-Bit Address Address 8CH 8DH 8EH 8FH A0H A1H A2H A3H A4H B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH C5H C6H C7H C8H C9H CAH CBH D1H D6H D7H Description Bus Configuration Register 3 Bus Configuration Register 4 Constant Value 0's Register (read only) Constant Value 1's Register (read only) GPT1 Timer 2 Control Register GPT1 Timer 3 Control Register GPT1 Timer 4 Control Register GPT2 Timer 5 Control Register GPT2 Timer 6 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Interrupt Control Register GPT2 CAPREL Interrupt Control Register Serial Channel 0 Transmit Interrupt Control Register Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Error Interrupt Control Register SSC Transmit Interrupt Control Register SSC Receive Interrupt Control Register SSC Error Interrupt Control Register External Interrupt 1 Control Register External Interrupt 2 Control Register External Interrupt 3 Control Register External Interrupt 4 Control Register External Interrupt 5 Control Register External Interrupt 6 Control Register External Interrupt 7 Control Register Port 5 Register (read only) Trap Flag Register Watchdog Timer Control Register Reset Value 0000H 0000H 0000H FFFF H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H XXXXH 0000H 000XH2) BUSCON3 b FF18H BUSCON4 b FF1AH ZEROS ONES T2CON T3CON T4CON T5CON T6CON T2IC T3IC T4IC T5IC T6IC CRIC S0TIC S0RIC S0EIC SSCTIC SSCRIC SSCEIC CC9IC CC10IC CC11IC CC12IC CC13IC CC14IC CC15IC P5 TFR b FF1CH b FF1EH b FF40H b FF42H b FF44H b FF46H b FF48H b FF60H b FF62H b FF64H b FF66H b FF68H b FF6AH b FF6CH b FF6EH b FF70H b FF72H b FF74H b FF76H b FF8AH b FF8CH b FF8EH b FF90H b FF92H b FF94H b FF96H b FFA2H b FFACH WDTCON b FFAEH Semiconductor Group 17-10 10Jul97@15:19h The Register Set / C161 Name S0CON SSCCON P2 DP2 P3 DP3 P4 DP4 P6 DP6 Physical 8-Bit Address Address b FFB0H b FFB2H b FFC0H b FFC2H b FFC4H b FFC6H b FFC8H b FFCAH b FFCCH b FFCEH D8H D9H E0H E1H E2H E3H E4H E5H E6H E7H Description Serial Channel 0 Control Register SSC Control Register Port 2 Register Port 2 Direction Control Register Port 3 Register Port 3 Direction Control Register Port 4 Register (8 bits) Port 4 Direction Control Register Port 6 Register (8 bits) Port 6 Direction Control Register Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 00H 00H 00H 00H Note: The shaded registers are only available in the C161O, not in the C161V and the C161K. 1) 2) The system configuration is selected during reset. Bit WDTR indicates a watchdog timer triggered reset. Semiconductor Group 17-11 10Jul97@15:19h The Register Set / C161 17.4 Special Notes PEC Pointer Registers The source and destination pointers for the peripheral event controller are mapped to a special area within the internal RAM. Pointers that are not occupied by the PEC may therefore be used like normal RAM. During Power Down mode or any warm reset the PEC pointers are preserved. The PEC and its registers are described in chapter "Interrupt and Trap Functions". GPR Access in the ESFR Area The locations 00'F000H...00'F01EH within the ESFR area are reserved and allow to access the current register bank via short register addressing modes. The GPRs are mirrored to the ESFR area which allows access to the current register bank even after switching register spaces (see example below). MOV EXTR MOV R5, DP3 #1 R5, ODP3 ;GPR access via SFR area ;GPR access via ESFR area Writing Bytes to SFRs All special function registers may be accessed wordwise or bytewise (some of them even bitwise). Reading bytes from word SFRs is a non-critical operation. However, when writing bytes to word SFRs the complementary byte of the respective SFR is cleared with the write operation. Semiconductor Group 17-12 10Jul97@15:19h Instruction Set Summary / C161 18 Instruction Set Summary This chapter briefly summarizes the C161's instructions ordered by instruction classes. This provides a basic understanding of the C161's instruction set, the power and versatility of the instructions and their general usage. A detailed description of each single instruction, including its operand data type, condition flag settings, addressing modes, length (number of bytes) and object code format is provided in the "Instruction Set Manual" for the C16x Family. This manual also provides tables ordering the instructions according to various criteria, to allow quick references. Summary of Instruction Classes Grouping the various instruction into classes aids in identifying similar instructions (eg. SHR, ROR) and variations of certain instructions (eg. ADD, ADDB). This provides an easy access to the possibilities and the power of the instructions of the C161. Note: The used mnemonics refer to the detailled description. Arithmetic Instructions * * * * * * * * * Addition of two words or bytes: Addition with Carry of two words or bytes: Subtraction of two words or bytes: Subtraction with Carry of two words or bytes: 16*16 bit signed or unsigned multiplication: 16/16 bit signed or unsigned division: 32/16 bit signed or unsigned division: 1's complement of a word or byte: 2's complement (negation) of a word or byte: ADD ADDC SUB SUBC MUL DIV DIVL CPL NEG ADDB ADDCB SUBB SUBCB MULU DIVU DIVLU CPLB NEGB Logical Instructions * * * Bitwise ANDing of two words or bytes: Bitwise ORing of two words or bytes: Bitwise XORing of two words or bytes: AND OR XOR ANDB ORB XORB Compare and Loop Control Instructions * * * Comparison of two words or bytes: Comparison of two words with post-increment by either 1 or 2: Comparison of two words with post-decrement by either 1 or 2: CMP CMPI1 CMPD1 CMPB CMPI2 CMPD2 Semiconductor Group 18-1 10Jul97@15:19h Instruction Set Summary / C161 Boolean Bit Manipulation Instructions * * * * * * * * * Manipulation of a maskable bit field in either the high or the low byte of a word: Setting a single bit (to `1'): Clearing a single bit (to `0'): Movement of a single bit: Movement of a negated bit: ANDing of two bits: ORing of two bits: XORing of two bits: Comparison of two bits: BFLDH BSET BCLR BMOV BMOVN BAND BOR BXOR BCMP BFLDL Shift and Rotate Instructions * * * * * Shifting right of a word: Shifting left of a word: Rotating right of a word: Rotating left of a word: Arithmetic shifting right of a word (sign bit shifting): SHR SHL ROR ROL ASHR Prioritize Instruction * Determination of the number of shift cycles required to normalize a word operand (floating point support): PRIOR Data Movement Instructions * * Standard data movement of a word or byte: MOV MOVB Data movement of a byte to a word location with either sign or zero byte extension: MOVBS MOVBZ Note: The data movement instructions can be used with a big number of different addressing modes including indirect addressing and automatic pointer in-/decrementing. System Stack Instructions * * * Pushing of a word onto the system stack: Popping of a word from the system stack: Saving of a word on the system stack, and then updating the old word with a new value (provided for register bank switching): PUSH POP SCXT Semiconductor Group 18-2 10Jul97@15:19h Instruction Set Summary / C161 Jump Instructions * Conditional jumping to an either absolutely, indirectly, or relatively addressed target instruction within the current code segment: Unconditional jumping to an absolutely addressed target instruction within any code segment: Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit: Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit with a post-inversion of the tested bit in case of jump taken (semaphore support): JMPA JMPS JMPI JMPR * * JB JNB * JBC JNBS Call Instructions * Conditional calling of an either absolutely or indirectly addressed subroutine within the current code segment: Unconditional calling of a relatively addressed subroutine within the current code segment: Unconditional calling of an absolutely addressed subroutine within any code segment: Unconditional calling of an absolutely addressed subroutine within the current code segment plus an additional pushing of a selectable register onto the system stack: Unconditional branching to the interrupt or trap vector jump table in code segment 0: CALLA CALLR CALLS CALLI * * * PCALL TRAP * Return Instructions * * * Returning from a subroutine within the current code segment: Returning from a subroutine within any code segment: Returning from a subroutine within the current code segment plus an additional popping of a selectable register from the system stack: Returning from an interrupt service routine: RET RETS * RETP RETI Semiconductor Group 18-3 10Jul97@15:19h Instruction Set Summary / C161 System Control Instructions * * * * * * Resetting the C161 via software: Entering the Idle mode: Entering the Power Down mode: Servicing the Watchdog Timer: Disabling the Watchdog Timer: Signifying the end of the initialization routine (pulls pin RSTOUT high, and disables the effect of any later execution of a DISWDT instruction): SRST IDLE PWRDN SRVWDT DISWDT EINIT Miscellaneous * * * * Null operation which requires 2 bytes of storage and the minimum time for execution: Definition of an unseparable instruction sequence: Switch `reg', `bitoff' and `bitaddr' addressing modes to the Extended SFR space: Override the DPP addressing scheme using a specific data page instead of the DPPs, and optionally switch to ESFR space: Override the DPP addressing scheme using a specific segment instead of the DPPs, and optionally switch to ESFR space: NOP ATOMIC EXTR EXTP EXTPR * EXTS EXTSR Note: The ATOMIC and EXT* instructions provide support for uninterruptable code sequences eg. for semaphore operations. They also support data addressing beyond the limits of the current DPPs (except ATOMIC), which is advantageous for bigger memory models in high level languages. Refer to chapter "System Programming" for examples. Protected Instructions Some instructions of the C161 which are critical for the functionality of the controller are implemented as so-called Protected Instructions. These protected instructions use the maximum instruction format of 32 bits for decoding, while the regular instructions only use a part of it (eg. the lower 8 bits) with the other bits providing additional information like involved registers. Decoding all 32 bits of a protected doubleword instruction increases the security in cases of data distortion during instruction fetching. Critical operations like a software reset are therefore only executed if the complete instruction is decoded without an error. This enhances the safety and reliability of a microcontroller system. Semiconductor Group 18-4 10Jul97@15:19h Device Specification / C161 19 Device Specification The device specification describes the electrical parameters of the device. It lists DC characteristics like input, output or supply voltages or currents, and AC characteristics like timing characteristics and requirements. Other than the architecture, the instruction set or the basic functions of the C161 core and its peripherals, these DC and AC characteristics are subject to changes due to device improvements or specific derivatives of the standard device. Therefore these characteristics are not contained in this manual, but rather provided in a separate Data Sheet, which can be updated more frequently. Please refer to the current version of the Data Sheet for all electrical parameters. Note: In any case the specific characteristics of a device should be verified, before a new design is started. This ensures that the used information is up to date. The figures below show the pin diagrams of the C161. They show the location of the different supply and IO pins. A detailed description of all the pins is also found in the respective Data Sheet. Semiconductor Group 19-1 10Jul97@15:19h Device Specification / C161 Figure 19-1 Pin Description of the C161V, P-MQFP-80 Package Semiconductor Group 19-2 10Jul97@15:19h Device Specification / C161 Figure 19-2 Pin Description of the C161K, P-MQFP-80 Package Semiconductor Group 19-3 10Jul97@15:19h Device Specification / C161 Figure 19-3 Pin Configuration of the C161O, P-MQFP-80 Package Semiconductor Group 19-4 10Jul97@15:19h Keyword Index / C161 20 Keyword Index This section lists a number of keywords which refer to specific details of the C161 in terms of its architecture, its functional units or functions. This helps to quickly find the answer to specific questions about the C161. A Acronyms 1-6 Adapt Mode 14-8 Address Arbitration 8-21 Area Definition 8-20 Boundaries 3-10 Segment 8-8, 14-10 ADDRSELx 8-19, 8-21 ALE length 8-11 ALU 24 Arbitration Address 8-21 ASC0 Error Detection 10-10 Interrupts 10-12 ASC0, Asynchronous Serial Interface 10-1 C Capture Mode (GPT) 9-14, 9-23 CCxIC 5-22 Chip Select 8-8, 14-10 Clock Generator 2-9, 14-11 modes 2-9, 14-11 Concatenation of Timers 9-11, 9-21 Configuration Address 8-8, 14-10 Bus Mode 8-2, 14-9 Chip Select 8-8, 14-10 PLL 2-9, 14-11 Reset 14-5 Write Control 14-9 Context Switching 5-15 Count direction 9-4, 9-18 Counter 9-7, 9-10 CP 32 CPU 2-2, 11 CRIC 9-26 Cross Reference 1-5 CSP 28 B Baudrate ASC0 10-10 Bootstrap Loader 13-4 SSC 11-10 BHE 8-7 Bit addressable memory 3-4 Handling 19 Manipulation Instructions 18-2 protected 2-15, 19 Bootstrap Loader 13-1, 14-8 Boundaries 3-10 Bus Demultiplexed 8-4 Idle State 8-23 Mode Configuration 8-2, 14-9 Multiplexed 8-3 BUSCONx 8-17, 8-21 Semiconductor Group 20-1 10Jul97@15:19h Keyword Index / C161 D Data Page 30, 16-13 boundaries 3-10 Delay Read/Write 8-14 Demultiplexed Bus 8-4 Development Support 1-5 Direct Drive 2-10 Direction count 9-4, 9-18 Disable Interrupt 5-13 Segmentation 23 Division 37, 16-1 DP0L, DP0H 6-4 DP1L, DP1H 6-7 DP2 6-10 DP3 6-13 DP4 6-18 DP6 6-23 DPP 30, 16-13 G GPR 3-6, 32, 17-2 GPT 2-14 GPT1 9-1 GPT2 9-16 H Half Duplex 11-8 Hardware Reset 14-1 Traps 5-23 I Idle State (Bus) 8-23 Idle Mode 15-1 Instruction 16-1, 18-1 Bit Manipulation 18-2 Branch 14 Pipeline 13 protected 18-4 Timing 20 unseparable 16-12 Interface External Bus 8-1 serial async. 10-1 serial sync. 11-1 Internal RAM 3-4 Interrupt Enable/Disable 5-13 External 5-20 Priority 5-6 Processing 5-1, 5-5 Response Times 5-16 Sources 5-3 System 2-6, 5-2 Vectors 5-3 IP 27 E Emulation Mode 14-8 Enable Interrupt 5-13 Segmentation 23 Error Detection ASC0 10-10 SSC 11-12 ESFR 2-8 EXICON 5-21 External Bus Characteristics 8-10 to 8-14 Bus Idle State 8-23 Bus Modes 8-2 to 8-7 Interrupts 5-20 External Bus 2-8 F Flags 24 to 26 Full Duplex 11-6 Semiconductor Group 20-2 10Jul97@15:19h Keyword Index / C161 M MDC 38 MDH 37 MDL 37 Memory 2-7 bit-addressable 3-4 External 3-9 RAM/SFR 3-4 ROM 3-3, 16-14 Memory Cycle Time 8-12 Multiplexed Bus 8-3 Multiplication 37, 16-1 P P0L, P0H 6-4 P1L, P1H 6-7 P2 6-10 P3 6-13 P4 6-18 P5 6-21 P6 6-23 PEC 2-7, 3-7, 5-10 Response Times 5-18 PECCx 5-10 Peripheral 2-11 Pins 7-1, 19-2 in Idle and Power Down mode 15-5 Pipeline 13 Effects 16 PLL 14-11 Port 2-12 Power Down Mode 15-3 Prescaler 2-10 Protected Bits 2-15, 19 instruction 18-4 PSW 24, 5-8 O ODP2 6-10 ODP3 6-13 ODP6 6-23 ONES 39 Open Drain Mode 6-2 Oscillator circuit 2-9 R RAM internal 3-4 Read/Write Delay 8-14 Register 17-1, 17-4, 17-8 Reset 9-8, 14-1 Configuration 14-5 Output 14-4 Values 14-4 ROM 16-14 RP0H 8-22 Semiconductor Group 20-3 10Jul97@15:19h Keyword Index / C161 S S0BG 10-10 S0CON 10-2 S0EIC, S0RIC, S0TIC, S0TBIC 10-12 S0RBUF 10-7, 10-9 S0TBUF 10-6, 10-9 Segment Address 8-8, 14-10 boundaries 3-10 Segmentation 28 Enable/Disable 23 Serial Interface 2-13, 10-1 Asynchronous 10-4 Synchronous 10-8, 11-1 SFR 2-8, 3-8, 17-4, 17-8 Single Chip Mode 8-2 Software Reset 14-1 Traps 5-23 Source Interrupt 5-3 SP 34 SSC 11-1 Baudrate generation 11-10 Error Detection 11-12 Full Duplex 11-6 Half Duplex 11-8 SSCBR 11-10 SSCCON 11-2 SSCEIC, SSCRIC, SSCTIC 11-14 SSCRB, SSCTB 11-7 Stack 3-5, 34, 16-4 Startup Configuration 14-5 STKOV 35 STKUN 36 Subroutine 16-9 Synchronous Serial Interface 11-1 SYSCON 21, 22, 8-16 T T2CON 9-8 T2IC, T3IC, T4IC 9-15 T3CON 9-3 T4CON 9-8 T5CON 9-20 T5IC, T6IC 9-26 T6CON 9-18 TFR 5-24 Timer 2-14, 9-1, 9-16 Auxiliary Timer 9-8, 9-20 Concatenation 9-11, 9-21 Core Timer 9-3, 9-18 Tools 1-5 Traps 5-4, 5-23 Tri-State Time 8-13 U Unseparable instructions 16-12 W Waitstate Memory Cycle 8-12 Tri-State 8-13 Watchdog 2-14, 12-1, 14-4 WDT 12-1 WDTCON 12-2 X XBUS 2-9, 8-24 Z ZEROS 39 Semiconductor Group 20-4 |
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