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Macroblock Features 16 constant-current output channels 12-bit grayscale PWM control Preliminary Datasheet MBI5031 Small Outline Package 16-Channel PWM-Embedded LED Driver Backward compatible with MBI5026 in package Scrambled-PWM technology to improve refresh rate Open-Circuit Detection to detect individual LED errors 8-bit programmable output current gain Constant output current range: 5 ~ 45mA at 3.3V supply voltage 5 ~ 60mA at 5.0V supply voltage Output current accuracy: between channels: <3% (max.), and between ICs: <6% (max.) Staggered output delay Maximum data clock frequency: 25MHz Schmitt trigger input 3.0V-5.5V supply voltage GF: SOP24-300-1.00 Product Description MBI5031 is designed for LED video applications using internal Pulse Width Modulation (PWM) control with 12-bit gray scales. MBI5031 features a 16-bit shift register which converts serial input data into each 12-bit pixel gray scale of output port. At MBI5031 output port, sixteen regulated current ports are designed to provide uniform and constant current sinks for driving LEDs with a wide range of Vf variations. The output current can be preset through an external resistor. Moreover, the preset current of MBI5031 can be further programmed up or down to 128 gain steps for LED global brightness adjustment. With Scrambled-PWM (S-PWMTM) technology, MBI5031 enhances Pulse Width Modulation by scrambling the "on" time into several "on" periods. The enhancement equivalently increases the visual refresh rate. When building a 12-bit gray scale video, S-PWMTM reduces the flickers and improves the fidelity. MBI5031 offloads the signal timing generation of the host controller which just needs to feed data into drivers. MBI5031 drives the corresponding LEDs to the brightness specified by image data. With MBI5031, all output channels can be built with 12-bit color depths (4,096 gray scales). Macroblock, Inc. 2006 Floor 6-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30077, ROC. TEL: +886-3-579-0068, FAX: +886-3-579-7534 E-mail: info@mblock.com.tw -1March 2006, V1.00 MBI5031 Block Diagram 16-channel PWM-Embedded LED Driver OUT0 OUT1 OUT14 OUT15 R-EXT IO Regulator and DAC 16-bit error status VDD Comparators Comparators Comparators Comparators GCLK 12-bit Counter 16 SYNC Gray Scale Pixel Gray Scale Pixel Control Configuration Register 16 Gray Scale Pixel 16 16 Gray Scale Pixel LE GND 16 Buffers 16 16 SDI DCLK 16-bit Shift Register (FIFO) SDO Figure 1 -2- March 2006, V1.00 MBI5031 Terminal Description Pin Name GND SDI DCLK LE Function 16-channel PWM-Embedded LED Driver Pin Configuration GND SDI DCLK LE OUT0 OUT1 OUT2 OUT3 OUT 4 OUT 5 OUT6 OUT7 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD R-EXT SDO GCLK OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 Ground terminal for control logic and current sink Serial-data input to the shift register Clock input terminal used to shift data on rising edge and carries command information when LE is asserted. Data strobe terminal and controlling command with DCLK OUT0 ~ OUT15 Constant current output terminals GCLK Gray scale clock terminal Clock input for gray scale. The gray scale display is counted by gray scale clock comparing with input data. Serial-data output to the receiver-end SDI of next driver IC Input terminal used to connect an external resistor for setting up output current for all output channels 3.3V/5V supply voltage terminal SDO R-EXT VDD Maximum Ratings Characteristic Supply Voltage Input Pin Voltage (SDI) Output Current Sustaining Voltage at OUT Port Data Clock Frequency* Gray Scale Clock Frequency GND Terminal Current Power Dissipation (On PCB, Ta=25C) Thermal Resistance (On PCB, Ta=25C) Operating Temperature Storage Temperature * Supply Voltage is 5V. GF Type GF Type Symbol VDD VIN IOUT VDS FDCLK FGCLK IGND PD Rth(j-a) Topr Tstg Rating 7 -0.4 ~ VDD + 0.4 +60 17 +25 +8 +1000 2.39 52.37 -40 ~ +85 -55 ~ +150 Unit V V mA V MHz MHz mA W C/W C C -3- March 2006, V1.00 MBI5031 16-channel PWM-Embedded LED Driver Equivalent Circuits of Inputs and Outputs GCLK, DCLK, SDI terminal VDD LE terminal VDD IN IN SDO terminal VDD OUT -4- March 2006, V1.00 MBI5031 Electrical Characteristics (VDD= 5.0V) Characteristics Supply Voltage Sustaining Voltage at OUT Ports Symbol VDD VDS IOUT Output Current IOH IOL Input Voltage "H" level "L" level VIH VIL IOH VOL VOH dIOUT %/dVDS %/dVDD VDS,TH RIN(down) IDD(off) 1 Supply Current "On" "Off" IDD(off) 2 IDD(off) 3 IDD(on) 1 IDD(on) 2 Rext= Open, Rext= 920, Rext= 460, Rext= 920, Rext= 460, OUT0 ~ OUT15 16-channel PWM-Embedded LED Driver Condition Min. 4.5 5 0.7*VDD GND 4.6 Rext= 920 LE OUT0 ~ OUT15 OUT0 ~ OUT15 OUT0 ~ OUT15 OUT0 ~ OUT15 OUT0 ~ OUT15 Typ. 5.0 0.1 1.0 0.15 430 3.5 7.1 7.5 11.0 11.5 Max. 5.5 17.0 60 -1.0 1.0 VDD 0.3*VDD 0.5 0.4 3 0.20 700 5.3 10.7 11.3 16.5 17.3 Unit V V mA mA mA V V A V V % %/V %/V V K Refer to "Test Circuit for Electrical Characteristics" SDO SDO Ta = -40~85C Ta = -40~85C VDS= 17.0V IOL= +1.0mA IOH= -1.0mA IOUT= 10.5mA VDS= 1.0V Output Leakage Current Output Voltage Current Skew Output Current vs. Output Voltage Regulation Output Current vs. Supply Voltage Regulation LED Open Detection Threshold Pull-down Resistor SDO VDS within 1.0V and 3.0V, Rext=460@21mA VDD within 4.5V and 5.5V, Rext=460@21mA - 200 = Off = Off = Off = On = On - mA -5- March 2006, V1.00 MBI5031 Characteristics Supply Voltage Sustaining Voltage at OUT Ports Symbol VDD VDS 16-channel PWM-Embedded LED Driver Condition OUT0 ~ OUT15 Electrical Characteristics (VDD= 3.3V) Min. 3.0 Typ. 3.3 Max. 3.6 Unit V 5 0.7*VDD GND 2.9 Rext= 920 - 0.1 1.0 0.15 430 2.2 4.4 6.3 6.7 7.1 17.0 45 -1.0 1.0 VDD 0.3*VDD 0.5 0.4 3 0.20 700 3.3 6.6 9.5 10.1 10.7 V mA mA mA V V A V V % %/V %/V V K IOUT Output Current IOH IOL Input Voltage "H" level "L" level VIH VIL IOH VOL VOH dIOUT %/dVDS %/dVDD VDS,TH RIN(down) IDD(off) 1 Supply Current "On" "Off" IDD(off) 2 IDD(off) 3 IDD(on) 1 IDD(on) 2 Refer to "Test Circuit for Electrical Characteristics" SDO SDO Ta = -40~85C Ta = -40~85C VDS= 17.0V IOL= +1.0mA IOH= -1.0mA IOUT= 10.5mA VDS= 1.0V Output Leakage Current Output Voltage SDO Current Skew Output Current vs. Output Voltage Regulation Output Current vs. Supply Voltage Regulation LED Open Detection Threshold Pull-down Resistor VDS within 1.0V and 3.0V, Rext=460@21mA VDD within 3.0V and 3.6V, Rext=460@21mA LE Rext= Open, Rext= 920, Rext= 460, Rext= 920, Rext= 460, OUT0 ~ OUT15 OUT0 ~ OUT15 OUT0 ~ OUT15 OUT0 ~ OUT15 OUT0 ~ OUT15 200 = Off = Off = Off = On = On - mA Test Circuit for Electrical Characteristics IDD VDD IOUT VIH,VIL V DD SDI DCLK LE G CLK R - EXT G ND Logic input waveform VIH=VDD V IL=GND SDO O UT0 Function Generator . . . VDS IOL I OH O UT15 R ext Figure 2 -6- March 2006, V1.00 MBI5031 Switching Characteristics (VDD= 5.0V) Characteristics Symbol 16-channel PWM-Embedded LED Driver Condition Min. Typ. Max. Unit SDI - DCLK Setup Time LE - DCLK LE - DCLK Hold Time DCLK - SDI DCLK - LE DCLK - SDO tSU0 tSU1 tSU2 tH0 tH1 tPD0 VDD=5.0V VIH=VDD VIL=GND Rext=460 VLED=4.5V RL=152 CL=10pF C1=100nF C2=10F 1 1 5 3 7.0 15.0 16.0 5.0 20.0 125.0 - 22.0 130 24.0 30.0 60.0 90.0 90.0 70.0 2.0 35.0 37.0 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s Propagation Delay Time GCLK - OUT 4n * tPD1 LE - SDO** OUT 4n + 1 * tPD2** tDL1 tDL2 tDL3 tw(L) tw(DCLK) tw(GCLK) tOR tOF tEDD*** Stagger Delay Time OUT 4n + 2 * OUT 4n + 3 * LE Pulse Width DCLK GCLK Output Rise Time of Output Ports Output Fall Time of Output Ports Error Detection Minimum Duration *There will be one GCLK latency at the first PWM output data. Refer to the Timing Waveform, where n=0, 1, 2, 3. **In timing of "Read Configuration" and "Read Error Status Code", the next DCLK rising edge should be tPD2 after the falling edge of LE. ***Refer to Figure 6. -7- March 2006, V1.00 MBI5031 Switching Characteristics (VDD= 3.3V) Characteristics SDI - DCLK Setup Time LE - DCLK LE - DCLK Hold Time DCLK - SDI DCLK - LE DCLK - SDO Symbol tSU0 tSU1 tSU2 tH0 tH1 tPD0 16-channel PWM-Embedded LED Driver Condition Min. 1.0 1.0 5.0 3.0 7.0 VDD=3.3V VIH=VDD VIL=GND Rext=460 VLED=4.5V RL=152 CL=10pF C1=100nF C2=10F 5.0 25.0 125.0 Typ. 40.0 150 40.0 30.0 60.0 90.0 90.0 70.0 2.0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s Propagation Delay Time GCLK - OUT 4n * tPD1 LE - SDO OUT 4n + 1 * tPD2** tDL1 tDL2 tDL3 tw(L) tw(DCLK) tw(GCLK) tOR tOF tEDD*** Stagger Delay Time OUT 4n + 2 * OUT 4n + 3 * LE Pulse Width DCLK GCLK Output Rise Time of Output Ports Output Fall Time of Output Ports Error Detection Minimum Duration *There will be one GCLK latency at the first PWM output data. Refer to the Timing Waveform, where n=0, 1, 2, 3. **In timing of "Read Configuration" and "Read Error Status Code", the next DCLK rising edge should be tPD2 after the falling edge of LE. ***Refer to Figure 6. Test Circuit for Switching Characteristics IDD V DD C1 I OUT V IH,VIL VDD SDI DCLK LE G CLK R - EXT GND Logic input VIH=VDD VIL=G ND waveform SDO OUT0 Function Generator . . . RL CL RL CL VL ED C2 OUT 15 Rext CL Figure 3 -8- March 2006, V1.00 MBI5031 Timing Waveform (1) tW(DCLK) DCLK tSU1 tH1 tw(LE) tSU2 16-channel PWM-Embedded LED Driver LE tSU0 tH0 SDI tPD0 tPD2 SDO (2) GCLK 1 clock latency OUT4n tDL1 tPD1 OUT4n+1 tDL2 OUT4n+2 tDL3 OUT4n+3 (3) tW(GCLK) GCLK Output Ports 90% 10% 90% 10% tOF tOR -9- March 2006, V1.00 MBI5031 Principle of Operation Control Command Command Name 16-channel PWM-Embedded LED Driver Signals Combination Number of DCLK LE Rising Edge when LE is asserted High 0 or 1 Description The Action after a Falling Edge of LE Data Latch Global Latch Read Configuration Enable "Error detection" Read "Error status code" Write Configuration High High High High High 2 or 3 4 or 5 6 or 7 8 or 9 10 or 11 Serial data are transferred to the buffers Buffer data are transferred to the comparators Move out "configuration register" to the shift registers Enable "open circuit detection" of each output's LED Move out "error status code" of 16 outputs to the shift registers Serial data are transferred to the "configuration register" Data Latch DCLK LE SDI SDO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Next Data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N1 N2 N3 Previous Data D0 D1 D2 Global Latch DCLK LE SDI SDO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Next Data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N1 N2 N3 Previous Data D0 D1 D2 Read Configuration DCLK LE SDI SDO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Next Data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N1 N2 N3 Previous Data D0 D1 D2 Write Configuration DCLK LE SDI SDO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Next Data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N1 N2 N3 Previous Data D0 D1 D2 - 10 - March 2006, V1.00 MBI5031 Setting Gray Scales of Pixels 16-channel PWM-Embedded LED Driver MBI5031 implements the gray level of each output port using the S-PWMTM control algorithm. With the 16-bit data, all output channels can be built with 4,096 gray scales. The 16-bit input shift register latches 15 times of the gray scale data into each data buffer with a "data latch" command sequentially. With a "global latch" command for the 16th gray scale data, the 256-bit data buffers will be clocked in with the MSB first, loading the data from port 15 to port 0. Full Timing for Data Loading Port 15 Port 14 Port 1 Port 0 DCLK LE SDI SDO 00 01 02 0E 0F 10 11 12 1E 1F 20 21 22 EE EF F0 F1 F2 FD FE FF N0 N1 N2 D00 D01 D02 D0E D0F D10 D0F D11 D10 D12 D11 D1E D1D D1F D1E D20 D1F D21 D20 D22 D21 DEE DEF DED DEE DF0 DEF DF1 DF0 DF2 DF1 DFD DFE DFC DFD DFF DFE DN0 DFF DN1 DN0 DN2 DN1 Previous Data Previous Data Data latch Data latch Data latch Global latch Figure 4 Open-Circuit Detection Principle Iout Iout, target Given Rext MBI5031 Output Characteristics Curve Iout, effect Loading Line VDS, effect Vknee VDS, Th ~ Vknee + 0.2Volt VDS Figure 5 The principle of MBI5031 LED Open-Circuit Detection is based on the fact that the LED loading status is judged by comparing the effective current value (Iout, effect) of each output port with the target current (Iout, target) set by Rext. As shown in the above figure, the knee voltage (Vknee) is the one between triode region and saturation region. The cross point between the loading line and MBI5031 output characteristics curve is the effective output point (VDS, effect, Iout, effect).Thus, after the command of "enabling error detection", the output ports of MBI5031 will be turned on for a while. It is required to obtain the stable error status result for 2 second. Then, the error status saved in the built-in register would be shifted out through SDO pin bit by bit by sending the command of "Read Error Status Code". Thus, to detect the status of LED correctly, the output ports of MBI5031 must be turned on. The relationship between the Error Status code and the effective output point is shown below: State of Output Port Detected Open-Circuit Error Status Code "0" "1" "0" Condition of Effective Output Point Meaning Iout, effect = 0 Iout, effect Iout, target and Vout, effect VDS, Th On Iout, effect Iout, target and Vout, effect VDS, Th Note: the threshold voltage VDS, Th is around Vknee + 0.2 Volt Off Open Circuit Normal - 11 - March 2006, V1.00 MBI5031 1. Enable error detection 2. Start error detection T5 T6 16-channel PWM-Embedded LED Driver 3. Read error status code T0 T1 T2 T7 T8 1 4. Shift out error data 2 3 15 16 T1 T2 DCLK LE SDO GCLK OUT0~15 T0 Previous Data Previous Data Previous Data D0 D1 D2 D14 D15 Next Data All the output ports are turned "ON" PWM current outputs At least 2 seconds PWM current outputs Note : tEDD = 2 s is required to obtain the stable error status result. Definition of Configuration Register Bit Attribute Definition Value Figure 6 Function F E D X X X X X X X X X 00 (Default) Reserved bit Reserved bit Reserved bit 64 times of 6-bit PWM counting and once of PWM 6-bit counting 16 times of 6-bit PWM counting by 1/4 GCLK and once of 6-bit PWM counting 4 times of 6-bit PWM counting by 1/16 GCLK and once of 6-bit PWM counting 12-bit PWM counting Auto-synchronization Self-synchronization 8'b10101011 (Default) C Write B PWM counting mode selection 01 10 11 PWM data A Write synchronization mode 9~2 1 0 Write X Write Current gain adjustment X Time-out alert of GCLK disconnection 0 1 (Default) 00000000 ~ 11111111 X 0 (Default) 1 Reserved bit Enable Disable - 12 - March 2006, V1.00 MBI5031 16-channel PWM-Embedded LED Driver Setting the PWM Gray Scale Counter MBI5031 provides a 12-bit color depth. The value of each 16-bit serial data input will be valid only for 12 bits and implemented according 12-bit PWM counter. Setting the PWM Counting Mode MBI5031 defines the different counting algorithms that support S-PWMTM, scrambled PWM, technology. With S-PWMTM , the total PWM cycles can be broken down into MSB ( Most Significant Bits) and LSB (Least Significant Bits) of gray scale cycles, and the MSB information can be dithered across many refresh cycles to achieve overall same high bit resolution. MBI5031 also allows changing different counting algorithms and provides the better output linearity when there are fewer transitions of output. Mode 00 6 6-bit x 2 + 6-bit counting 6 6 6 # of GCLKs=(2 -1)x2 +2 6-bit PWM Counting, 31 GCLKs 6-bit PWM counting Total 64 times 6-bit PWM Counting, 252 GCLKs Mode 01 2 4 6-bit x 2 x2 + 6-bit counting 6 2 4 6 # of GCLKs=(2 -1)x2 x2 +2 6-bit PWM counting Total 16 times Mode 10 4 2 6-bit x 2 x2 + 6-bit counting 6 4 2 6 # of GCLKs=(2 -1)x2 x2 +2 6-bit PWM Counting, 1008 GCLKs 6-bit PWM Counting Total 4 times Mode 10 12 direct counting 12 # of GCLKs=2 12-bit PWM Counting, 4096 GCLKs Total 1 time - 13 - March 2006, V1.00 MBI5031 Synchronization for PWM Counting 16-channel PWM-Embedded LED Driver Between the data frame and the video frame, when the bit "A" is set to "0", MBI5031 will automatically handle the synchronization of previous data and next data for PWM counting. The next image data will be updated to output buffers and start PWM counting when the previous data has finished one internal PWM cycle. It will prevent the lost count of image data resolution and guarantee the data accuracy. In this mode, system controller only needs to provide a continuous running GCLK for PWM counter. The output will be renewed after finishing one of MSB PWM cycles. Load data from SDI Update data in buffers Move data form buffers to outputs DCLK LE SDI GCLK OUT0~15 Outputs are switching according to previous data value Outputs are switching to finish one MSB PWM cycle One GCLK latency Outputs are switching according to next data value D0 0 D1 D2 1 D3 D12 D13 D14 D15 Next Data Next Data N N +1 N +2 N +3 `global latch' command Figure 7 When the bit "A" is set to "1" (Default), MBI5031 will update the next image data into output buffer immediately, no matter the counting status of previous image data is. In this mode, system controller will synchronize the GCLK according image data outside MBI5031 by itself. Otherwise, the conflict of previous image data and next image data will cause the data lost. DCLK LE SDI GCLK OUT0~15 Load data from SDI One GCLK latency `global latch' command Outputs are ON/OFF according to NEW data D0 0 D1 D2 1 D3 D12 D13 D14 N D15 Next Data N+ 1 N+ 2 N+ 3 N+ 4 Figure 8 Time-Out Alert of GCLK Disconnection When signal of GCLK is disconnected for around 1 second period, the all output ports will be turned off automatically. This function will protect the LED display system to stay on always and prevent a big current to damage the power system. The default is set to `enable" when bit "0" is 0. When the GCLK is active again, the driver resumes to work after resetting the internal counters and comparators. - 14 - March 2006, V1.00 MBI5031 Setting Output Current the following figure. IOUT(mA) 70 60 50 40 30 20 10 0 100 300 500 700 900 16-channel PWM-Embedded LED Driver The output current (IOUT) is set by an external resistor, Rext. The default relationship between IOUT and Rext is shown in MBI5031 Rext vs. IOUT 1100 Rext() 1300 1500 1700 1900 Figure 9 Also, the output current can be calculated from the equation: VR-EXT=0.625Volt x G; IOUT= (VR-EXT/Rext) x15.5 Whereas Rext is the resistance of the external resistor connected to R-EXT terminal and VR-EXT is its voltage. G is the digital current gain, which is set by the bit9 - bit2 of the configuration register. The default value of G is 1. For your information, the output current is about 21mA when Rext=460 and 10.5mA when Rext=920 if G is set to default value 1. The formula and setting for G are described in next section. Current Gain Adjustment Gain =1.9882 ... 128 steps ... Gain =1 128 steps ... ... (0,0,0,0,0,0,0,0) ... Gain = 1/8 (1,0,1,0,1,0,1,1) (0,0,0,0,0,0,1,0) (1,1,1,1,1,1,1,1) March 2006, V1.00 (0,0,0,0,0,0,0,1 - 15 - MBI5031 16-channel PWM-Embedded LED Driver The bit 9 to bit 2 of the configuration register set the gain of output current, i.e., G. As totally 8-bit in number, i.e., ranged from 8'b00000000 to 8'b11111111, these bits allow the user to set the output current gain up to 256 levels. These bits can be further defined inside Configuration Register as follows: F E D C B A 9 HC 8 DA6 7 DA5 6 DA4 5 DA3 4 DA2 3 DA1 2 DA0 1 0 - 1. Bit 9 is HC bit. The setting is in low current band when HC=0, and in high current band when HC=1. 2. Bit 8 to bit 2 are DA6 ~ DA0. The relationship between these bits and current gain G is: G= [(1+3xHC)/4]x[(1+3xD/128)/2] Whereas HC is 1 or 0 and D=DA6x26+DA5x25+DA4x24+DA3x23+DA2x22+DA1x21+DA0x20 In other words, these bits can be looked as a floating number with 1-bit exponent HC and 7-bit mantissa DA6~DA0. For example, 1. When the bit9 to bit2 of configuration register are set to 8'b11111111, the current gain G becomes [(1+3x1)/4]x[(1+3x127/128)/2]=1.9882 2. When the bit9 to bit2 of configuration register are set to 8'b10000000, the current gain G becomes [(1+3x1)/4]x[(1+3x0/128)/2]=0.5 3. when the bit9 to bit2 of configuration register are set to 8'b00000000, the current gain G becomes [(1+3x0)/4]x[(1+3x0/128)/2]=1/8 Delay Time of Staggered Output MBI5031 has a built-in staggered circuit to perform delay mechanism. Among output ports exist a graduated 30ns delay time among OUT 4n , OUT 4n + 1 , OUT 4n + 2 , and OUT 4n + 3 , by which the output ports will be divided to four groups at a different time so that the instant current from the power line will be lowered. - 16 - March 2006, V1.00 MBI5031 16-channel PWM-Embedded LED Driver Package Power Dissipation (PD) The maximum allowable package power dissipation is determined as PD (max) = (Tj - Ta) / Rth(j-a). When 16 output channels are turned on simultaneously, the actual package power dissipation is PD (act) = (IDD x VDD) + (IOUT x Duty x VDS x 16). Therefore, to keep PD (act) PD (max), the allowable maximum output current as a function of duty cycle is: IOUT = { [ (Tj - Ta) / Rth(j-a) ] - (IDD x VDD) } / VDS / Duty / 16, where Tj = 150C. IOUT vs. Duty Cycle@ Rth(j-a)=52.37/W Max. IOUT(mA) 70 60 50 40 30 20 10 VDS=1V@Ta=25 VDS=1V@Ta=85 VDS=2V@Ta=25 VDS=2V@Ta=85 0 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% Duty Cycle Figure 10 Condition: IOUT=60mA, 16 output channels Device Type Rth(j-a) (C /W) GF 52.37 The maximum power dissipation, PD (max) = (Tj - Ta) / Rth(j-a), decreases as the ambient temperature increases. MBI5031 Maximum Power Dissipation at Various Ambient Temperatures Power Dissipation (W) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 35 45 55 65 75 Ambient Temperature () 85 95 105 GF Type: Rth=52.37/W Safe Operation Area Figure 11 - 17 - March 2006, V1.00 MBI5031 LED Supply Voltage (VLED) 16-channel PWM-Embedded LED Driver MBI5031 are designed to operate with VDS ranging from 0.4V to 0.8V (depending on IOUT=5~60mA) considering the package power dissipating limits. VDS may be higher enough to make PD (act) > PD (max) when VLED = 5V and VDS = VLED - VF, in which VLED is the load supply voltage. In this case, it is recommended to use the lowest possible supply voltage or to set an external voltage reducer, VDROP. A voltage reducer lets VDS = (VLED -VF) - VDROP. Resistors or Zener diode can be used in the applications as shown in the following figures. VLED Voltage Supply Voltage Supply (VLED) VDrop VF VDS VDrop VF VDS MBI5031 Figure 12 MBI5031 Switching Noise Reduction LED drivers are frequently used in switch-mode applications which always behave with switching noise due to the parasitic inductance on PCB. To eliminate switching noise, refer to "Application Note for 8-bit and 16-bit LED DriversOvershoot". - 18 - March 2006, V1.00 MBI5031 Package Outline 16-channel PWM-Embedded LED Driver MBI5031GF Outline Drawing Note: The unit for the outline drawing is mm. - 19 - March 2006, V1.00 MBI5031 16-channel PWM-Embedded LED Driver Product Top Mark Information The first row of printing MBIXXXX or Part number ID number The second row of printing XXXXXXXX MBIXXXX Package Code Manufacture Code Device Version Code Product No. Process Code G: Green and Pb-free Product Revision History Datasheet version V1.00 Device Version Code A Product Ordering Information Part Number "Pb-free & Green" Package Type SOP24-300-1.00 Weight (g) MBI5031GF 0.30 - 20 - March 2006, V1.00 |
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