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SSM75T10GP,S N-channel Enhancement-mode Power MOSFET Low gate-charge Simple drive requirement Fast switching G Pb-free, RoHS compliant. D BV ID DSS 100V 15m 72A R DS(ON) S DESCRIPTION The SSM75T10GS is in a TO-263 package, which is widely used for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. The through-hole version, the SSM75T10GP in TO-220, is available for low-footprint vertical mounting. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. G GD S TO-263 (S) D TO-220 (P) S ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID @ TC=25C ID @ TC=100C IDM PD @ TC=25C Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current 1 3 Rating 100 20 72 45 260 138 1.11 Units V V A A A W W/C Total Power Dissipation Linear Derating Factor TSTG TJ Storage Temperature Range Operating Junction Temperature Range -55 to 150 -55 to 150 C C THERMAL DATA Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 0.9 62 Units C/W C/W 2/16/2005 Rev.1.1 www.SiliconStandard.com 1 of 5 SSM75T10GP,S ELECTRICAL CHARACTERISTICS @ Tj=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=1mA Min. 100 1 Min. Typ. 0.09 52 69 12 39 12 75 220 250 540 310 1.1 Typ. 51 74 Max. Units 15 21 3 10 100 100 110.4 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance2 VGS=10V, ID=30A VGS=4.5V, ID=16A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Rg Symbol VSD trr Qrr Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (T j=25oC) Drain-Source Leakage Current (T j=150oC) VDS=VGS, ID=250uA VDS=10V, ID=30A VDS=100V, VGS=0V VDS=80V ,VGS=0V VGS= 20V ID=30A VDS=80V VGS=4.5V VDS=50V ID=30A RG=10 , VGS=10V RD=1.6 VGS=0V VDS=25V f=1.0MHz f=1.0MHz Test Conditions IS=30A, VGS=0V IS=30A, VGS=0V dI/dt=100A/s Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Parameter Forward On Voltage 2 2 2 5690 9100 Source-Drain Diode Max. Units 1.3 V ns nC Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%. 2/16/2005 Rev.1.1 www.SiliconStandard.com 2 of 5 SSM75T10GP,S 250 120 T C = 25 C 200 o ID , Drain Current (A) ID , Drain Current (A) 10V 6.0 V 5.0V 4.5V 100 T C = 150 o C 80 10V 6.0V 5.0V 4.5V V G =3.0V 150 60 100 V G =3.0V 50 40 20 0 0 2 4 6 8 0 0 1 2 3 4 5 6 7 8 9 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 17 2.0 I D =16A 16 1.8 o T C =25 C 1.6 I D =30A V G =10V RDS(ON) (m ) 15 Normalized R DS(ON) 1.4 14 1.2 1.0 13 0.8 12 0.6 11 3 5 7 9 11 0.4 -50 0 50 100 150 V GS Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 2 45 1.5 30 Normalized VGS(th) (V) 1.4 IS(A) T j =150 o C 15 1 T j =25 o C 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 0 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j ,Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 2/16/2005 Rev.1.1 Fig 6. Gate Threshold Voltage v.s. Junction Temperature www.SiliconStandard.com 3 of 5 SSM75T10GP,S f=1.0MHz 12 10000 VGS , Gate to Source Voltage (V) I D = 30 A 10 C iss 8 V DS = 50 V V DS = 64 V V DS = 80 V C (pF) 1000 6 4 C oss C rss 2 0 0 20 40 60 80 100 120 140 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS ,Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 1000 1 Normalized Thermal Response (Rthjc) Duty factor=0.5 100 0.2 ID (A) 0.1 100us 1ms 10 0.1 0.05 0.02 0.01 PDM t T Duty factor = t/T Peak Tj = PDM x Rthjc + TC T c =25 o C Single Pulse 1 10ms 100ms DC Single Pulse 0.01 0.1 1 10 100 1000 0.00001 0.0001 0.001 0.01 0.1 1 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 2/16/2005 Rev.1.1 Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM75T10GP,S Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 2/16/2005 Rev.1.1 www.SiliconStandard.com 5 of 5 |
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