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SSM9934GM 2N AND 2P-CHANNEL ENHANCEMENT MODE POWER MOSFET PRODUCT SUMMARY P2G N-CH BVDSS RDS(ON) N2G N1S/N2S N1D/P1D 35V 48m 4.3A -35V 72m -3.6A Simple Drive Requirement Low On-resistance Full Bridge Application on LCD Monitor Inverter N2D/P2D P1S/P2S P1G ID P-CH BVDSS RDS(ON) ID P1S P1G P2S SO-8 N1G DESCRIPTION The advanced power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SO-8 package is universally preferred for all commercialindustrial surface mount applications and suited for low voltage applications such as DC/DC converters. P2G P1N1D P2N2D N1G N1S N2S N2G Pb-free; RoHS-compliant ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating N-channel 35 20 4.3 3.4 20 1.38 0.01 -55 to 150 -55 to 150 P-channel -35 20 -3.6 -2.8 -20 Units V V A A A W W/ Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 90 Unit /W 09/13/2007 Rev.1.00 www.SiliconStandard.com 1 SSM9934GM N-CH ELECTRICAL CHARACTERISTICS @Tj=25 C (unless otherwise specified) Symbol BVDSS BVDSS/Tj o Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 35 1 - Typ. 0.03 8 6 2 3 6 5 14 4 490 130 55 Max. Units 48 70 3 1 25 100 10 780 V V/ m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA RDS(ON) Static Drain-Source On-Resistance 2 VGS=10V, ID=4A VGS=4.5V, ID=3A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=250uA VDS=10V, ID=4A VDS=30V, VGS=0V VDS=24V, VGS=0V VGS=20V ID=4A VDS=28V VGS=4.5V VDS=15V ID=1A RG=3.3,VGS=10V RD=15 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 SOURCE-DRAIN DIODE Symbol VSD trr Qrr Parameter Forward On Voltage 2 Test Conditions IS=1.2A, VGS=0V IS=4A, VGS=0V dI/dt=100A/s Min. - Typ. 18 11 Max. Units 1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge 09/13/2007 Rev.1.00 www.SiliconStandard.com 2 SSM9934GM P-CH ELECTRICAL CHARACTERISTICS @Tj=25 C (unless otherwise specified) o Symbol BVDSS BVDSS/Tj Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (T j=25 C) Drain-Source Leakage Current (T j=70 C) o o Test Conditions VGS=0V, ID=-250uA 2 Min. -35 -1 - Typ. -0.02 6 6 1 3 7 5 19 4 420 140 65 Max. Units 72 100 -3 -1 -25 100 10 1100 V V/ m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25,ID=-1mA RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss VGS=-10V, ID=-3A VGS=-4.5V, ID=-2A VDS=VGS, ID=-250uA VDS=-10V, ID=-3A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS=20V ID=-3A VDS=-28V VGS=-4.5V VDS=-15V ID=-1A RG=3.3,VGS=-10V RD=15 VGS=0V VDS=-25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 SOURCE-DRAIN DIODE Symbol VSD trr Qrr Parameter Forward On Voltage 2 Test Conditions IS=-1.2A, VGS=0V IS=-3A, VGS=0V dI/dt=-100A/s Min. - Typ. 20 16 Max. Units -1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 2 3.Surface mounted on 1 in copper pad of FR4 board , t <10sec ; 186 /W when mounted on Min. copper pad. 09/13/2007 Rev.1.00 www.SiliconStandard.com 3 SSM9934GM N-Channel 21 21 T A =25 C 18 o ID , Drain Current (A) ID , Drain Current (A) 15 10V 7.0V 5.0V 4.5V T A = 150 o C 18 10V 7.0V 5.0V 4.5V 15 12 12 9 9 6 6 V G =2.5V 3 V G =2.5V 3 0 0 1 2 3 4 5 6 0 0 1 2 3 4 5 6 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 70 1.6 I D =3A 60 T A =25 o C Normalized RDS(ON) 1.4 I D =4A V G =10V RDS(ON) (m ) 1.2 50 1.0 40 0.8 30 2 4 6 8 10 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 2 5 4 3 T j =150 o C 2 Normalized VGS(th) (V) 1.2 1.5 IS(A) T j =25 o C 1 0.5 1 0 0 0.2 0.4 0.6 0.8 1 0 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j ,Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 09/13/2007 Rev.1.00 Fig 6. Gate Threshold Voltage v.s. Junction Temperature 4 www.SiliconStandard.com SSM9934GM N-Channel f=1.0MHz 12 1000 VGS , Gate to Source Voltage (V) 10 ID=4A V DS = 2 8 V C iss 8 6 C (pF) C oss 100 4 C rss 2 0 0 3 6 9 12 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 Normalized Thermal Response (Rthja) 10 0.2 ID (A) 100us 1ms 1 0.1 0.1 0.05 0.02 0.01 Single Pulse P DM t T 10ms 100ms 0.1 0.01 Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 186/W T A =25 o C Single Pulse 1s DC 0.01 0.1 1 10 100 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 09/13/2007 Rev.1.00 Fig 12. Gate Charge Waveform 5 www.SiliconStandard.com SSM9934GM P-Channel 21 21 18 T A =25 o C -ID , Drain Current (A) 15 -ID , Drain Current (A) -10V -7.0V -5.0V -4.5V 18 T A = 150 C o -10V -7.0V -5.0V -4.5V 15 12 12 9 9 V G = - 2.5V 6 6 V G = - 2.5V 3 3 0 0 1 2 3 4 5 0 0 1 2 3 4 5 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 1.6 I D = -2 A 90 T A =25 o C Normalized R DS(ON) 1.4 I D = -3 A V G = - 10V RDS(ON) (m ) 1.2 80 1.0 70 0.8 60 2 4 6 8 10 0.6 -50 0 50 100 150 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 2 4 Normalized -VGS(th) (V) 1.2 3 1.5 -IS(A) 2 T j =150 o C T j =25 o C 1 1 0.5 0 0 0.2 0.4 0.6 0.8 1 0 -50 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 09/13/2007 Rev.1.00 Fig 6. Gate Threshold Voltage v.s. Junction Temperature 6 www.SiliconStandard.com SSM9934GM P-Channel f=1.0MHz 12 1000 -VGS , Gate to Source Voltage (V) 10 I D = -3 A V DS = - 2 8 V C iss 8 6 C (pF) C oss 100 C rss 4 2 0 0 3 6 9 12 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 Normalized Thermal Response (Rthja) 0.2 10 0.1 0.1 100us -ID (A) 1 0.05 1ms 10ms 100ms 0.02 0.01 PDM t T Single Pulse 0.01 0.1 Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 186/W T A =25 o C Single Pulse 0.01 0.1 1 10 1s DC 100 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 09/13/2007 Rev.1.00 Fig 12. Gate Charge Waveform 7 www.SiliconStandard.com SSM9934GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 09/13/2007 Rev.1.00 www.SiliconStandard.com 4 |
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