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| CAT5251 Quad Digitally Programmable Potentiometer (DPPTM) with 256 Taps and SPI Interface FEATURES Four linear-taper digitally programmable potentiometers 254 resistor taps per potentiometer End to end resistance 50 k or 100 k Potentiometer control and memory access via SPI interface Low wiper resistance, typically 100 Nonvolatile memory storage for up to four wiper settings for each potentiometer Automatic recall of saved wiper settings at power up 2.5 to 6.0 volt operation Standby current less than 1 A 1,000,000 nonvolatile WRITE cycles 100 year nonvolatile memory data retention SOIC 24-lead and TSSOP 24-lead Industrial temperature range For Ordering Information details, see page 14. DESCRIPTION The CAT5251 is four Digitally Programmable Potentiometers (DPPsTM) integrated with control logic and 16 bytes of NVRAM memory. Each DPP consists of a series of resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 8-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 8-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a SPI serial bus. On power-up, the contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control register. The CAT5251 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. It is available in the -40C to 85C industrial operating temperature range and offered in a 24-lead SOIC and TSSOP package. PIN CONFIGURATION SOIC 24-Lead (W) TSSOP 24-Lead (Y) SO A0 RW3 RH3 RL3 NC VCC RLO RHO RWO CS WP 1 2 3 4 5 24 23 22 21 20 HOLD SCK RL2 RH2 RW2 NC GND RW1 RH1 RL1 A1 SI WP A0 A1 HOLD CS SCK SI SO FUNCTIONAL DIAGRAM RH0 RH1 RH2 RH3 SPI BUS INTERFACE WIPER CONTROL REGISTERS RW0 RW1 RW2 6 CAT 19 7 5251 18 8 9 10 11 12 17 16 15 14 13 CONTROL LOGIC NONVOLATILE DATA REGISTERS RL0 RL1 RL2 RL3 RW3 (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 1 Doc. No. MD-2017 Rev. H CAT5251 PIN DESCRIPTION SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses and data to be written to the CAT5251. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the CAT5251. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the CAT5251. Opcodes, byte addresses or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. A0, A1: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of four devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5251. RH, RL: Resistor End Points The four sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW: Wiper The four RW pins are equivalent to the wiper terminal of a mechanical potentiometer. : Chip Select CS is the Chip select pin. low enables the CS CS CAT5251 and high disables the CAT5251. CS CS high takes the SO output pin to high impedance and forces the devices into a Standby mode (unless an internal write operation is underway). The CAT5251 draws ZERO current in the Standby mode. A high to low transition on is required prior to any CS sequence being initiated. A low to high transition on after a valid write sequence is what initiates an CS internal write cycle. : Write Protect WP is the Write Protect pin. The Write Protect pin WP will allow normal read/write operations when held high. When is tied low, all non-volatile write WP operations to the Data registers are inhibited (change of wiper control register is allowed). WP going low while is still low will interrupt a write to CS the registers. If the internal write cycle has already been initiated, going low will have no effect on WP any write operation. HOLD: Hold The pin is used to pause transmission to the HOLD CAT5251 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is should be held high any time this low. (HOLD function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor. PIN DESCRIPTION Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name SO A0 RW3 RH3 RL3 NC VCC RL0 RH0 RW0 CS WP SI A1 RL1 RH1 RW1 GND NC RW2 RH2 RL2 SCK HOLD Function Serial Data Output Device Address, LSB Wiper Terminal for Potentiometer 3 High Reference Terminal for Potentiometer 3 Low Reference Terminal for Potentiometer 3 No Connect Supply Voltage Low Reference Terminal for Potentiometer 0 High Reference Terminal for Potentiometer 0 Wiper Terminal for Potentiometer 0 Chip Select Write Protection Serial Input Device Address Low Reference Terminal for Potentiometer 1 High Reference Terminal for Potentiometer 1 Wiper Terminal for Potentiometer 1 Ground No Connect Wiper Terminal for Potentiometer 2 High Reference Terminal for Potentiometer 2 Low Reference Terminal for Potentiometer 2 Bus Serial Clock Hold Doc. No. MD-2017 Rev. H 2 (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5251 SERIAL BUS PROTOCOL The CAT5251 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT5251 to interface directly with many of today's popular microcontrollers. The CAT5251 contains an 8-bit instruction register. The instruction set and the operation codes are detailed in Table 3, Instruction Set on page 8. After the device is selected with going low the CS first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. DEVICE OPERATION The CAT5251 is four resistor arrays integrated with an SPI serial interface logic, four 8-bit wiper control registers and sixteen 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the SPI bus. Additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer's nonvolatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode. ABSOLUTE MAXIMUM RATINGS Parameter Temperature Under Bias Storage Temperature (1) Ratings -55 to +125 -65 to +150 -2.0 to +VCC +2.0 -2.0 to +7.0 1.0 300 6 Units C C V V W C mA Voltage on any Pin with Respect to VSS(2)(3) VCC with Respect to Ground Package Power Dissipation Capability (TA = 25C) Lead Soldering Temperature (10 s) Wiper Current Recommended Operating Conditions VCC = +2.5 V to +6 V Parameter Operating Ambient Temperature (Industrial) Ratings -40 to +85 Units C Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) (3) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V. 3 Doc. No. MD-2017 Rev. H (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5251 POTENTIOMETER CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter RPOT RPOT Potentiometer Resistance (-00) Potentiometer Resistance (-50) Potentiometer Resistance Tolerance RPOT Matching Power Rating Wiper Current Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (2) Relative Linearity (3) Temperature Coefficient of RPOT Ratiometric Temp. Coefficient Potentiometer Capacitances Frequency Response Test Conditions Min Typ 100 50 20 1 50 3 300 150 VCC Max Units k k % % mW mA V nV/Hz % LSB(4) LSB(4) ppm/C ppm/C pF MHz 25C, each pot IW = 3 mA @ VCC = 3 V IW = 3 mA @ VCC = 5 V VSS = 0 V (1) RW(n)(actual) - R(n)(expected) RW(n+1) - [RW(n)+LSB](5) (1) (1) (1) RPOT = 50 k (1) (5) IW RW VTERM VN 200 100 GND 0.4 1 0.5 300 20 10/10/25 0.4 TCRPOT TCRATIO CH/CL/CW fc D.C. OPERATING CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol ICC1 ICC2 ISB ILI ILO VIL VIH VOL1 VOH1 Parameter Power Supply Current Power Supply Current Non-volatile Write Standby Current (VCC = 5.0 V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3 V) Output High Voltage (VCC = 6 V) IOL = 3 mA IOH = -1.6 mA VCC - 0.8 Test Conditions fSCK = 2.5 MHz, SO Open VCC = 6 V Inputs = GND fSCK = 2.5 MHz, SO = Open VCC = 6 V Inputs = GND VIN = GND or VCC; SO Open VIN = GND to VCC VOUT = GND to VCC -1 VCC x 0.7 Min Typ Max 1 5 1 10 10 VCC x 0.3 VCC + 1.0 0.4 Units mA mA A A A V V V V Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) (3) (4) (5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. LSB = RTOT / 255 or (RH - RL) / 255, single pot n = 0, 1, 2, ..., 255. 4 (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice Doc. No. MD-2017 Rev. H CAT5251 PIN CAPACITANCE (1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0 V (unless otherwise noted). Symbol COUT CIN Parameter Output Capacitance (SO) Input Capacitance (CS , SCK, SI, , HOLD, A0, A1) WP Test Conditions VOUT = 0 V VIN = 0 V Min Typ Max 8 6 Units pF pF A.C. CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol tSU tH tWH tWL fSCK tLZ tRI(1) tFI(1) tHD tCD tV tHO tDIS tHZ tCS tCSS tCSH Parameter Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD to Output High Z High Time CS Setup Time CS Hold Time CS 250 250 250 0 250 100 CL = 50 pF 100 100 200 Test Conditions Min 50 50 125 125 DC 3 50 2 2 Typ Max Units ns ns ns ns MHz ns s s ns ns ns ns ns ns ns ns ns POWER UP TIMING (1)(2) Over recommended operating conditions unless otherwise stated. Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min Typ Max 1 1 Units ms ms WIPER TIMING Symbol tWRPO tWRL Parameter Wiper Response Time After Power Supply Stable Wiper Response Time After Instruction Issued Min 5 5 Max 10 10 Units s s Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 5 Doc. No. MD-2017 Rev. H (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5251 WRITE CYCLE LIMITS Over recommended operating conditions unless otherwise stated. Symbol tWR Parameter Write Cycle Time Min Typ Max 5 Units ms RELIABILITY CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol NEND (1) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Typ Max Units Cycles/Byte Years V mA TDR(1) VZAP(1) ILTH(1) Figure 1. Sychronous Data Timing VIH tCS CS VIL VIH VIL tSU VIH tCSS tCSH SCK tWH tH tWL SI VIL VALID IN tRI tFI tV tHO tDIS HI-Z SO VOH VOL HI-Z Note: Dashed Line = mode (1, 1) Figure 2. HOLD Timing CS tCD SCK tHD HOLD tHZ SO HIGH IMPEDANCE tCD tHD tLZ Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. MD-2017 Rev. H 6 (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5251 INSTRUCTION AND REGISTER DESCRIPTION DEVICE TYPE / ADDRESS BYTE The first byte sent to the CAT5251 from the master/processor is called the Device Address Byte. The most significant four bits of the Device Type address are a device type identifier. These bits for the CAT5251 are fixed at 0101[B] (refer to Table 1). The two least significant bits in the slave address byte, A1 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A1 - A0 input pins for the CAT5251 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The remaining two bits in the device address byte must be set to 0. INSTRUCTION BYTE The next byte sent to the CAT5251 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I3-I0. The R1 and R0 bits point to one of the four data registers of each associated potentiometer. The least two significant bits point to one of four Wiper Control Registers. The format is shown in Table 2. Data Register Selection Data Register Selected DR0 DR1 DR2 DR3 R1 0 0 1 1 R0 0 1 0 1 Table 1. Identification Byte Format Device Type Identifier Slave Address ID3 0 (MSB) ID2 1 ID1 0 ID0 1 0 0 A1 A0 (LSB) Table 2. Instruction Byte Format Instruction Opcode Data Register Selection WCR/Pot Selection I3 (MSB) I2 I1 I0 R1 R0 P1 P0 (LSB) (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 7 Doc. No. MD-2017 Rev. H CAT5251 WIPER CONTROL AND DATA REGISTERS Wiper Control Register (WCR) The CAT5251 contains four 8-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction; it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. The Wiper Control Register is a volatile register that loses its contents when the CAT5251 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers (DR) Each potentiometer has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 5ms. Table 3. Instruction Set Instruction Set Instruction Read Wiper Control Register Write Wiper Control Register Read Data Register Write Data Register XFR Data Register to Wiper Control Register XFR Wiper Control Register to Data Register Global XFR Data Registers to Wiper Control Registers Global XFR Wiper Control Registers to Data Register Increment/Decrement Wiper Control Register Read Status (WIP bit) Doc. No. MD-2017 Rev. H If the application does not require storage of multiple settings for the potentiometer; the Data Registers can be used as standard memory locations for system parameters or user preference data. Write in Process The contents of the Data Registers are saved to nonvolatile memory when the input goes HIGH CS after a write sequence is received. The status of the internal write cycle can be monitored by issuing a Read Status command to read the Write in Process (WIP) bit. INSTRUCTIONS Four of the ten instructions are three bytes in length. These instructions are: -- Read Wiper Control Register - read the current wiper position of the selected potentiometer in the WCR -- Write Wiper Control Register - change current wiper position in the WCR of the selected potentiometer -- Read Data Register - read the contents of the selected Data Register -- Write Data Register - write a new value to the selected Data Register -- Read Status - Read the status of the WIP bit which when set to "1" signifies a write cycle is in progress. Note: 1/0 = data is one or zero Operations WCR0/ P0 I3 I2 I1 I0 R1 R0 WCR1/ P1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1/0 1/0 1/0 1/0 1/0 1/0 0 0 1/0 0 8 1/0 1/0 1/0 1/0 1/0 1/0 0 0 1/0 1 Read the contents of the Wiper Control Register pointed to by P1-P0 Write new value to the Wiper Control Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and R1-R0 Write new value to the Data Register pointed to by P1-P0 and R1-R0 Transfer the contents of the Data Register pointed to by P1-P0 and R1-R0 to its associated Wiper Control Register Transfer the contents of the Wiper Control Register pointed to by P1-P0 to the Data Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of all four pots to their respective Wiper Control Registers Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of all four pots Enable Increment/decrement of the Control Latch pointed to by P1-P0 Read WIP bit to check internal write cycle status (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 1 1/0 1/0 0 1/0 1/0 1 1/0 1/0 0 1/0 1/0 1 1/0 1/0 0 1/0 1/0 0 1 0 0 0 0 CAT5251 The basic sequence of the three byte instructions is illustrated in Figure 8. These three-byte instructions exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. Four instructions require a two-byte sequence to complete, as illustrated in Figure 7. These instructions transfer data between the host/processor and the CAT5251; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: -- XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. -- XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. Figure 7. Two-Byte Instruction Sequence SI 0 1 0 1 0 0 A2 A1 A0 I3 Internal Address I2 I1 I0 R1 R0 P1 P0 Register Address Pot/WCR Address -- Global XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. -- Global XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 9 and 10). The Increment/Decrement command is different from the other commands. Once the command is issued the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instructions format for more detail. ID3 ID2 ID1 ID0 A3 Device ID Instruction Opcode Figure 8. Three-Byte Instruction Sequence SI 0 1 0 1 0 0 A2 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 Data Pot/WCR Register Address Address D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register D[7:0] ID3 ID2 ID1 ID0 A3 Device ID Internal Address Instruction Opcode Figure 9. Increment/Decrement Instruction Sequence SI 0 1 0 1 0 A3 0 A2 A1 A0 Internal Address I3 I2 I1 I0 I N Pot/WCR C Data Register Address 1 Address R1 R0 P1 P0 I N C 2 I N C n D E C 1 D E C n ID3 ID2 ID1 ID0 Device ID Instruction Opcode (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 9 Doc. No. MD-2017 Rev. H CAT5251 Figure 10. Increment/Decrement Timing Limits INC/DEC Command Issued SCK tWRL SI RW Voltage Out INSTRUCTION FORMAT Read Wiper Control Register (WCR) DEVICE ADDRESSES 0 1 0 1 CS 0 0 A 1 A10 0 INSTRUCTION 0 1 0 0 P 1 P 0 7 6 5 DATA 4 3 2 1 0 CS Write Wiper Control Register (WCR) DEVICE ADDRESSES 0 1 0 1 CS 0 0 A 1 A 0 1 0 INSTRUCTION 1 0 0 0 P 1 P 0 7 6 5 DATA 4 3 2 1 0 CS Read Data Register (DR) DEVICE ADDRESSES 0 1 0 1 CS 0 0 A 1 A 0 INSTRUCTION 1011R 1 R 0 P 1 DATA P 7 6 5 4 3 2 1 0 CS 0 Write Data Register (DR) DEVICE ADDRESSES INSTRUCTION DATA High Voltage 0 1 0 1 0 0 A A 1 1 0 0 R R P P 7 6 5 4 3 2 1 0 CS CS Write Cycle 10 1010 Read Status (WIP) DEVICE ADDRESSES 0 1 0 1 CS 0 0 A 1 A 0 0 1 INSTRUCTION 0 1 0 0 0 1 7 0 6 0 5 0 DATA 4 0 3 0 2 0 1 W CS 0I P Doc. No. MD-2017 Rev. H 10 (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5251 Global Transfer Data Register (DR) to Wiper Control Register (WCR) DEVICE ADDRESSES 0101 0 0 A 1 A 0 INSTRUCTION 0001RR 10 0 0 CS (1) Global Transfer Wiper Control Register (WCR) to Data Register (DR) DEVICE ADDRESSES 0 1 0 1 0 CS 0 INSTRUCTION 0 High Voltage CS Write Cycle A A1000RR0 10 10 Transfer Wiper Control Register (WCR) to Data Register (DR) DEVICE ADDRESSES 0 1 0 1 0 CS 0 INSTRUCTION A A 1 1 1 0 R R P P High Voltage CS Write Cycle 10 1010 Transfer Data Register (DR) to Wiper Control Register (WCR) DEVICE ADDRESSES 0 1 0 1 CS 0 0 A 1 A 0 INSTRUCTION 1101RRP 101 P CS 0 Increment (I)/Decrement (D) Wiper Control Register (WCR) DEVICE ADDRESSES 0 1 0 1 CS 0 0 A 1 A 0 INSTRUCTION 00100 0 P P I/D I/D 10 DATA ... I/D I/D CS Notes: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued. (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 11 Doc. No. MD-2017 Rev. H CAT5251 PACKAGING OUTLINE DRAWINGS SOIC 24-Lead 300 mils (W) (1)(2) SYMBOL MIN NOM MAX A A1 A2 b E1 E 2.35 0.10 2.05 0.31 0.20 15.20 10.11 7.34 1.27 BSC 0.25 0.40 0 5 2.65 0.30 2.55 0.51 0.33 15.40 10.51 7.60 0.75 1.27 8 15 c D E E1 e h b PIN#1 IDENTIFICATION e L 1 TOP VIEW D h h 1 A A2 1 END VIEW A1 SIDE VIEW L c Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-013. 12 (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice Doc. No. MD-2017 Rev. H CAT5251 (1)(2) TSSOP 24-Lead 4.4 mm (Y) b SYMBOL MIN NOM MAX A A1 A2 b E1 E 1.20 0.05 0.80 0.19 0.09 7.70 6.25 4.30 7.80 6.40 4.40 0.65 BSC 1.00 REF 0.50 0 0.60 0.70 8 0.15 1.05 0.30 0.20 7.90 6.55 4.50 c D E E1 e L L1 1 e TOP VIEW D c A2 A 1 L1 L SIDE VIEW END VIEW A1 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-153. (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 13 Doc. No. MD-2017 Rev. H CAT5251 EXAMPLE OF ORDERING INFORMATION Prefix CAT Optional Company ID Product Number (1) Device # Suffix 5251 W I Temperature Range I = Industrial (-40C to 85C) Package W: SOIC Y: TSSOP -50 Resistance -50: 50 k -00: 100 k - T1 Tape & Reel T: Tape & Reel 1: 1000/Reel - SOIC 2: 2000/Reel - TSSOP 5251 ORDERING INFORMATION Orderable Part Number CAT5251WI-50-T1 CAT5251WI-00-T1 CAT5251YI-50-T2 CAT5251YI-00-T2 CAT5251WI50 CAT5251WI00 CAT5251YI50 CAT5251YI00 Resistance (k) 50 100 50 100 50 100 50 100 Package SOIC TSSOP Matte-Tin SOIC TSSOP Lead Finish Notes: (1) All packages are RoHS compliant (Lead-free, Halogen-free). (2) This device used in the above example is a CAT5251WI-50-T1 (SOIC, Industrial Temperature, 50 k, Tape & Reel). Doc. No. MD-2017 Rev. H 14 (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5251 REVISION HISTORY Date 11-Nov-03 Rev. C Description Eliminated BGA package in all areas Eliminated Commercial temperature range Updated Functional Diagram Updated wiper resistance from 50 to 100 Updated notes in Absolute Max Ratings Eliminated Commercial temperature range in all areas Updated Potentiometer Characteristics table Updated DC Characteristics table Updated AC Characteristics table Added Wiper Timing Table on page 6 Corrected Synchronous Data Timing (Figure 1) drawing Updated Package Outline Drawings Updated Example of Ordering Information Added MD- to document number Reformatted data sheet layout Update Instruction Format - Read Data Register (DR) and Write Data Register (DR) Change logo and fine print to ON Semiconductor Update Ordering Information table 06-May-04 D 13-Dec-07 07-Feb-08 26-Nov-08 31-Jul-09 E F G H ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative (c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 15 Doc. No. MD-2017 Rev. H |
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