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800 MHz, Linear-in-dB VGA with AGC Detector AD8368
FEATURES
Analog variable gain range: -12 dB to +22 dB Linear-in-dB scaling: 37.5 dB/V 3 dB bandwidth: 800 MHz @ VGAIN = 0.5 V Integrated rms detector P1dB: 16 dBm @ 140 MHz Output IP3: 33 dBm @ 140 MHz Noise figure at maximum gain: 9.5 dB @ 140 MHz Input and output impedances: 50 Single-supply voltage from 4.5 V to 5.5 V RoHS-compliant, 24-lead LFCSP
ICOM 16 OCOM 6 GAIN 1 OCOM 7 gm STAGES 0dB -2dB INPT 19 ICOM 17 ICOM 18 ICOM 20 50 DECL ATTENUATOR LADDER -4dB -36dB REF
-
FUNCTIONAL BLOCK DIAGRAM
VPSO
10
MODE
21
VPSO VPSI VPSI VPSI VPSI VPSI
9 11 12 22 23 13
AD8368
GAIN INTERPOLATOR FIXED-GAIN AMPLIFIER OUTPUT BUFFER
24 ENBL 8 3 4
OUTP HPFL DECL
14 DECL
X2
+ 2 5
15 DECL
APPLICATIONS
Complete IF AGC amplifiers Gain trimming and leveling Cellular base stations Point-to-point radio links RF instrumentation
Figure 1.
DETO
DETI
GENERAL DESCRIPTION
The AD8368 is a variable gain amplifier (VGA) with analog linear-in-dB gain control that can be used from low frequencies to 800 MHz. Its excellent gain range, conformance, and flatness are attributed to the Analog Devices, Inc. X-AMP(R) architecture, an innovative technique for implementing high performance variable gain control. The gain range of -12 dB to +22 dB is scaled accurately to 37.5 dB/V with excellent conformance error. The AD8368 has a 3 dB bandwidth of 800 MHz that is nominally independent of gain setting. At 140 MHz, the OIP3 is 33 dBm at maximum gain. The output noise floor is -143 dBm/Hz, which corresponds to a 9.5 dB noise figure at maximum gain. The single-ended input and output impedances are nominally 50 . The gain of the AD8368 can be configured to be an increasing or decreasing function of the gain control voltage depending on whether the MODE pin is pulled to the positive supply or to ground, respectively. When MODE is pulled high, the AD8368 operates as a typical VGA with increasing gain. By connecting MODE to ground and using the on-board rms detector, the AD8368 can be configured as a complete AGC system with RSSI. The output power is accurately leveled to the internal default setpoint of 63 mV rms (-11 dBm referenced to 50 ), independent of the waveform crest factor. Because the uncommitted detector input is available at DETI, the AGC loop can level the signal at the AD8368 output or at any other point in the signal chain over a maximum input power range of 34 dB. Furthermore, the setpoint level can be raised by dividing down the output signal before applying it to the detector. The AD8368 operates from a supply voltage of 4.5 V to 5.5 V and consumes 60 mA of current. It can be fully powered down to <3 mA by grounding the ENBL pin. The AD8368 is fabricated using the Analog Devices proprietary SiGe SOI complementary bipolar IC process. It is available in a 24-lead LFCSP and operates over the industrial temperature range of -40C to +85C. Application boards are available upon request.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006-2007 Analog Devices, Inc. All rights reserved.
05907-001
AD8368 TABLE OF CONTENTS
Features ............................................................................................ 1 Applications..................................................................................... 1 Functional Block Diagram ............................................................ 1 General Description ....................................................................... 1 Revision History ............................................................................. 2 Specifications................................................................................... 3 Absolute Maximum Ratings.......................................................... 5 ESD Caution................................................................................ 5 Pin Configuration and Function Descriptions........................... 6 Typical Performance Characteristics ........................................... 7 Circuit Description....................................................................... 12 Input Attenuator and Interpolator ......................................... 12 Fixed-Gain Stage and Output Buffer ..................................... 12 Output Offset Correction........................................................ 12 Input and Output Impedances ............................................... 12 Gain Control Interface ............................................................ 13 Applications Information ............................................................ 14 VGA Operation ........................................................................ 14 AGC Operation ........................................................................ 14 Evaluation Board .......................................................................... 17 Outline Dimensions..................................................................... 18 Ordering Guide ........................................................................ 18
REVISION HISTORY
10/07--Rev. 0 to Rev. A Changes to Table 1............................................................................ 3 Changes to Figure 4 to Figure 6 ...................................................... 7 Changes to Figure 16........................................................................ 9 Changes to Figure 31...................................................................... 12 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 4/06--Revision 0: Initial Version
Rev. A | Page 2 of 20
AD8368 SPECIFICATIONS
VS = 5 V, TA = 25C, system impedance Z0 = 50 , VMODE = 5 V, RF input = 140 MHz, unless otherwise noted. Table 1.
Parameter OVERALL FUNCTION Frequency Range Maximum Input Maximum Output 1 AC Input Impedance AC Output Impedance GAIN CONTROL INTERFACE (GAIN) Gain Span Gain Scaling Gain Accuracy Maximum Gain Minimum Gain VGAIN Range Gain Step Response Gain Input Bias Current f = 70 MHz Noise Figure Output IP3 Output P1dB1 f = 140 MHz Noise Figure Output IP3 Output P1dB1 f = 240 MHz Noise Figure Output IP3 Output P1dB1 f = 380 MHz Noise Figure Output IP3 Output P1dB1
1
Min LF
Typ
Max 800
Unit MHz VP VP dB dB/V dB/V dB dB dB V ns A dB dBm dBm dB dBm dBm dB dBm dBm dB dBm dBm
Conditions 3 dB bandwidth To avoid input overload To avoid clipping From INPT to ICOM From OUTP to OCOM
3 2 50 50 34 37.5 -38 0.4 22 -12 0 100 -2 9.5 34 16 9.5 33 16 9.7 33 15 10 29 13 1
VMODE = 5 V, 50 mV VGAIN 950 mV VMODE = 0 V, 50 mV VGAIN 950 mV 100 mV VGAIN 900 mV VGAIN = 1 V VGAIN = 0 V For 6 dB gain step
Maximum gain f1 = 70 MHz, f2 = 71 MHz, VGAIN = 1 V, 0 dBm per output tone VGAIN = 0 V, VMODE = 0 V Maximum gain f1 = 140 MHz, f2 = 141 MHz, VGAIN = 1 V, 0 dBm per output tone VGAIN = 0 V, VMODE = 0 V Maximum gain f1 = 240 MHz, f2 = 241 MHz, VGAIN = 1 V, 0 dBm per output tone VGAIN = 0 V, VMODE = 0 V Maximum gain f1 = 380 MHz, f2 = 381 MHz, VGAIN = 1 V, 0 dBm per output tone VGAIN = 0 V, VMODE = 0 V
Operation at compression is not recommended due to adverse distortion components.
Rev. A | Page 3 of 20
AD8368
VS = 5 V, TA = 25C, system impedance Z0 = 50 , VMODE = 5 V, RF input = 140 MHz, unless otherwise noted. Table 2.
Parameter SQUARE LAW DETECTOR (DETI, DETO) Output Setpoint DETI DC Bias Level to ICOM DETI Impedance DETO Output Range 1 AGC Step Response MODE CONTROL INTERFACE (MODE) MODE Threshold MODE Input Bias Current POWER INTERFACE (VPSI, VPSO) Supply Voltage Total Supply Current Disable Current ENABLE INTERFACE (ENBL) Enable Threshold Enable Response Time Min Typ -11 VS/2 710 0.6 0.1 30 3.5 50 4.5 5 60 2 2.5 1.5 3 ENBL Input Bias Current
1
Max
Unit dBm V pF V s V A V mA mA V s s
Conditions OUTP connected to DETI
VS/2
For -6 dB input power step (CDETO = 1 nF)
5.5
ENBL high ENBL low
150
A
Time delay following off-to-on transition until output reaches 90% of final value Time delay following on-to-off transition until supply current is less than 5 mA VENBL = 5 V
Refer to AGC Operation section.
Rev. A | Page 4 of 20
AD8368 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage (VPSO, VPSI) ENBL and MODE Select Voltage RF Input Level Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 5.5 V 20 dBm 440 mW 52C/W 125C -40C to +85C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. A | Page 5 of 20
AD8368 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
MODE ENBL ICOM
20
VPSI
VPSI
24
23
22
21
GAIN 1 DETO 2 HPFL 3 DECL 4 DETI 5 OCOM 6
INPT
19
18 ICOM 17 ICOM
AD8368
TOP VIEW (Not to Scale)
16 ICOM 15 DECL 14 DECL 13 VPSI
7
8
9
10
11
12
05907-002
OCOM
OUTP
VPSI
VPSO
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4, 14, 15 5 6, 7 8 9, 10 11, 12, 13, 22, 23 16, 17, 18, 20 19 21 24 Mnemonic GAIN DETO HPFL DECL DETI OCOM OUTP VPSO VPSI ICOM INPT MODE ENBL Description Gain Control. Detector Output. Provides an output error current for the AGC function. High-Pass Filter Connection. A capacitor to ground sets the corner frequency of the internal output offset control loop that controls the minimum usable input frequency. Decoupling Pin. Nominally ~VS/2. Decoupling capacitance may need to be adjusted for AGC operation (see the Applications Information section). Detector Input. DC level referenced to DECL pin. Connect OCOM to low impedance ground. Signal Output. Must be ac-coupled. Positive Supply Voltage, 4.5 V to 5.5 V. VPSO and VPSI must be connected together externally and properly bypassed. Positive Supply Voltage, 4.5 V to 5.5 V. VPSO and VPSI must be connected together externally and properly bypassed. Connect ICOM to low impedance ground. Signal Input. Must be ac-coupled. Gain Direction Control. High for positive slope. Low for negative slope. Apply a positive voltage (2.5V VENBL VPSI) to activate device.
Rev. A | Page 6 of 20
VPSO
VPSI
AD8368 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, T = 25C, system impedance Z0 = 50 , MODE = 5 V, unless otherwise noted.
25 20 15 0.75V 10 5 0 -5 -10
05907-003
25 240MHz
4 3 2 +85C 1 0 -1 +25C -40C -2 -3 -4 1.0
CONFORMANCE ERROR (dB)
05907-008
1V
20 15 10
0.5V
GAIN (dB)
S21 (dB)
5 0 -5
0.25V
-20 10
100 FREQUENCY (MHz)
1000
-15
0
0.2
0.4 VGAIN (V)
0.6
0.8
Figure 3. S21 vs. Frequency by VGAIN
25 70MHz 20 15 +85C 10
GAIN (dB)
Figure 6. Gain and Conformance Error vs. VGAIN (f = 240 MHz)
4 25 3 20 2 1 0
CONFORMANCE ERROR (dB)
4 380MHz 3 2 1 0 -1 +25C -40C -2 -3 -4 1.0
CONFORMANCE ERROR (dB)
05907-007
15 10
GAIN (dB)
+85C
5 0 -5 -10 -15 +25C -40C
5 0 -5 -10 -15
-1 -2 -3 -4 1.0
0
0.2
0.4 VGAIN (V)
0.6
0.8
05907-004
0
0.2
0.4 VGAIN (V)
0.6
0.8
Figure 4. Gain and Conformance Error vs. VGAIN (f = 70 MHz)
25 140MHz 20 15 +85C 10
GAIN (dB)
Figure 7. Gain and Conformance Error vs. VGAIN (f = 380 MHz)
4
0.7
3
CONFORMANCE ERROR (dB)
0.6 0.5 0.4
AMPLITUDE (V)
2 1 0 -1 +25C -40C -2 -3 -4 1.0
VGAIN
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 VOUTP
5 0 -5 -10 -15
0
0.2
0.4 VGAIN (V)
0.6
0.8
05907-005
0.5
Figure 5. Gain and Conformance Error vs. VGAIN (f = 140 MHz)
TIME (s)
Figure 8. Gain Step Time Domain Response (6 dB Gain Step)
Rev. A | Page 7 of 20
05907-006
-15
0V
-10
AD8368
40
20
OUTPUT THIRD-ORDER INTERCEPT (dBm)
+85C
OUTPUT 1dB COMPRESSION (dBm)
35 30 25 20 15 10
05907-009
18 16 14 12 10 8 6 4 2 0 70 110 150 190 230
+85C +25C
+25C -40C
-40C
0 70
110
150
190
230
270
310
350
380
270
310
350
380
RF INPUT (MHz)
RF INPUT (MHz)
Figure 9. Output Third-Order Intercept vs. RF Input Frequency at Maximum Gain (VMODE = 0 V)
40 70MHz 35 30 25 20 15 10
05907-010
Figure 12. Output 1dB Compression Point vs. RF Input Frequency at Maximum Gain (VMODE = 0 V)
20 70MHz 18
OUTPUT 1dB COMPRESSION (dBm)
OUTPUT THIRD-ORDER INTERCEPT (dBm)
140MHz
140MHz
16 14 12 10 8 6 4 2 0 0 0.2 0.4 VGAIN (V) 0.6 0.8
05907-013
240MHz
380MHz 240MHz
380MHz
5 0
0
0.2
0.4 VGAIN (V)
0.6
0.8
1.0
1.0
Figure 10. Output Third-Order Intercept vs. VGAIN (VMODE = 0 V)
0 -10 -20 -30 -40 -50 -60
05907-011
Figure 13. Output 1dB Compression Point vs. VGAIN (VMODE = 0 V)
20 18 5.5V
OUTPUT 1dB COMPRESSION (dBm)
16 14 12 10 8 6 4 2 0 70 110 150 190 230 270 310 350
05907-014
THIRD-ORDER IMD (dBc)
5.0V 4.5V
240MHz
380MHz
-70 140MHz -80 0 0.2 0.4 VGAIN (V) 0.6 0.8 70MHz
1.0
380
RF INPUT (MHz)
Figure 11. Third-Order IMD vs. VGAIN (Output Power = 0 dBm per Tone, VMODE = 0 V)
Figure 14. Output 1dB Compression Point vs. RF Input Frequency by Supply Voltage at Maximum Gain (VMODE = 0 V)
Rev. A | Page 8 of 20
05907-012
5
AD8368
50 45 40
NOISE FIGURE (dB)
35 30 25 20 15 10 5 0 10 100 FREQUENCY (MHz)
05907-015
VGAIN = 0.75V
VGAIN = 0V
VGAIN = 1V
VGAIN = 0.25V VGAIN = 0.5V
1000
Figure 15. Noise Figure vs. Frequency at Maximum Gain (VMODE = 0 V)
50 45 0 -5
Figure 18. Input Reflection Coefficient vs. Frequency
OUTPUT RETURN LOSS (dB)
40
NOISE FIGURE (dB)
-10 -15 -20 -25 -30
05907-019
35 30 25 20 15 10 5 0 0 0.2 70MHz 140MHz 240MHz 380MHz 0.4 VGAIN (V) 0.6 0.8
05907-016
-35 -40 10
VGAIN = 1V VGAIN = 0V 100 FREQUENCY (MHz)
1.0
Figure 16. Noise Figure vs. VGAIN (VMODE = 0 V)
Figure 19. Output Return Loss vs. Frequency
0 -5 VGAIN = 0.5V
INPUT RETURN LOSS (dB)
-10 VGAIN = 0.75V -15 VGAIN = 1V -20 -25 -30 VGAIN = 0V VGAIN = 0.25V -40 10 100 FREQUENCY (MHz)
05907-017
VGAIN = 1V
VGAIN = 0V
-35
1000
Figure 17. Input Return Loss vs. Frequency
Figure 20. Output Reflection Coefficient vs. Frequency
Rev. A | Page 9 of 20
05907-020
05907-018
1000
AD8368
1.0 0.9 0.8 0.7
RSSI (V)
1.0 0.8
CONFORMANCE ERROR (dB)
1.0 0.9 0.8 0.7
RSSI (V)
1.0 0.8
CONFORMANCE ERROR (dB)
05907-026
05907-024
0.6 0.4 0.2 0 +85C +25C +25C -40C -0.2 -0.4 -0.6 -0.8 -40C -35 +85C -30 -25 -20 -15 -10 -5 0 5 RF INPUT (dBm) -1.0
0.6 +85C 0.4 0.2 0 -40C +25C -40C -0.2 -0.4 -0.6 -0.8 +25C -35 +85C -30 -25 -20 -15 -10 -5 0 5 RF INPUT (dBm) -1.0
0.6 0.5 0.4 0.3 0.2 0.1 0 -40
0.6 0.5 0.4 0.3 0.2 0.1 0 -40
Figure 21. RSSI (VDETO) and Conformance Error vs. Input Power (f = 70 MHz)
1.0 0.9 0.8 0.7 1.0 0.8
05907-021
Figure 24. RSSI (VDETO) and Conformance Error vs. Input Power (f = 380 MHz)
VRSSI
AMPLITUDE (V)
0.4 0.2 0 +85C +25C -40C -40C -0.2 -0.4 -0.6 -0.8 +25C -35 +85C -30 -25 -20 -15 -10 -5 0 5 RF INPUT (dBm) -1.0
CONFORMANCE ERROR (dB)
0.6
RSSI (V)
0.6 0.5 0.4 0.3 0.2 0.1 0 -40
VOUTP
05907-022
CH2 50mV CH3 100mV M20s 500MS/s A CH1 2.0ns/PT
410mV
Figure 22. RSSI (VDETO) and Conformance Error vs. Input Power (f = 140 MHz)
1.0 0.9 0.8 0.7 1.0 0.8
Figure 25. AGC Time Domain Response (3 dB Power Step, CDETO = 1 nF)
80 70 8 7 4.5V 6 5 5.0V 5.5V 5.5V 4 3 5.0V 20 10 4.5V 0 -40 -20 0 20 40 60 80 0 2 1
CONFORMANCE ERROR (dB)
0.6 0.4 0.2 0 +85C +25C -40C -40C -0.2 -0.4 -0.6 -0.8 +25C -35 +85C -30 -25 -20 -15 -10 -5 0 5 RF INPUT (dBm) -1.0
RSSI (V)
0.6 0.5 0.4 0.3 0.2 0.1 0 -40
50 40 30
05907-023
TEMPERATURE (C)
Figure 23. RSSI (VDETO) and Conformance Error vs. Input Power (f = 240 MHz)
Figure 26. Supply Current and Disable Current vs. Temperature
Rev. A | Page 10 of 20
DISABLE CURRENT (mA)
SUPPLY CURRENT (mA)
60
05907-025
AD8368
50
VENBL
40
VOUTP
PERCENTAGE (%)
05907-027
AMPLITUDE (V)
30
20
10
05907-029
CH2 500mV CH3 5V M2.0s 250MS/s 4.0ns/PT
A CH3
0.0V
0
-15.0
-14.7
-14.4
-14.1
-13.8
-13.5
INTERCEPT (dB)
Figure 27. ENBL Response Time
50
Figure 29. Gain Intercept Distribution (140 MHz)
40
PERCENTAGE (%)
30
20
10
05907-028
0 36.8
37.0
37.2
37.4
37.6
37.8
38.0
38.2
SLOPE (dB/V)
Figure 28. Gain Scaling Distribution (140 MHz)
Rev. A | Page 11 of 20
AD8368 CIRCUIT DESCRIPTION
The AD8368 is a single-ended VGA with a bandwidth of 800 MHz and a gain control span of 34 dB ranging from -12 dB to +22 dB. It incorporates an uncommitted square law detector that can be used to form a tight AGC loop around the VGA. Using the Analog Devices patented X-AMP architecture, the AD8368 achieves accurate linear-in-dB gain control with excellent linearity (OIP3) and noise figure (NF). The part also features 50 input and output impedances for ease of use. The main signal path, shown in Figure 30, consists of a variable input attenuator followed by a fixed-gain amplifier and output buffer. This architecture allows for a constant OIP3 and output noise floor as a function of gain setting. As a result, NF and IIP3 increase 1 dB for every 1 dB decrease in gain, resulting in a part with constant dynamic range over gain setting.
MODE GAIN GAIN INTERPOLATOR gm STAGES 0dB -2dB INPT
05907-033
OUTPUT OFFSET CORRECTION
The dc level at the input, INPT, is driven by an internal reference to VS/2. The reference is made available at the DECL pin for external decoupling with CDECL. The dc level at the output, OUTP, is regulated to the same midsupply reference by an offset correction loop independent of gain setting, temperature, and process. The low-pass response of this loop creates a high-pass corner frequency in the signal path transfer function, which can be set by choosing CDECL and CHPFL.
FIXED-GAIN OUTPUT AMPLIFIER BUFFER FROM INTERPOLATOR gm STAGES gm x1 HPFL DECL CDECL
05907-034
VOUT
VMID
FIXED-GAIN OUTPUT AMPLIFIER BUFFER VOUT -36dB
CHPFL
Figure 31. Output Centering Control Loop
-4dB
50 DECL ATTENUATOR LADDER
Figure 30. Simplified Block Diagram
INPUT ATTENUATOR AND INTERPOLATOR
The input attenuator is built from an 18-section resistor ladder providing 2 dB of attenuation at each successive tap point. The resistor ladder acts as a linear input attenuator, in addition to providing an accurate 50 input impedance. The variable transconductance (gm) stages are used to select the attenuated signal from the appropriate tap point along the ladder and feed this signal to the fixed-gain amplifier. To realize a continuous gain control function from discrete tap points, the gain interpolator creates a weighted sum of signals appearing on adjacent tap points by carefully controlling the variable gm stages.
The input and output coupling capacitors should be selected to provide low impedances at the frequencies of interest relative to 50 so as not to affect the high-pass corner. In this case, the high-pass corner frequency can be set by either CHPFL or CDECL, which form independent poles in the feedback path of the offset correction loop. The high-pass corner is determined by the highest of these poles, which are given by:
fHP , HPFL (kHz) = fHP , DECL (kHz) =
0.8 (0.005 + CHPFL) 5700 (0.005 + CDECL)
where CHPFL and CDECL are in nF. When using this method to set the high-pass frequency, the other capacitor should be sized such that its pole is at least 30x lower in frequency. In addition, note that CDECL represents the total decoupling capacitance at the DECL pins.
FIXED-GAIN STAGE AND OUTPUT BUFFER
The weighted sum of the different tap points is fed into the fixed-gain stage that drives the output buffer. Because the resistive input attenuator is linear and contributes minimal noise as a passive termination, the dynamic range as a function of gain is determined primarily by the noise and the distortion of the fixed-gain amplifier. This architecture explains the constant OIP3 and constant output noise floor with gain setting and the corresponding dB-for-dB increase in IIP3 and NF with decreasing gain. The output buffer has 6 dB of gain and provides a broadband 50 single-ended output impedance.
INPUT AND OUTPUT IMPEDANCES
The AD8368 offers single-ended broadband 50 input and output impedances. The excellent match to 50 is maintained from part to part, over frequency, and over gain setting. Both the input and output pins must be externally ac-coupled to prevent disruption of the internal dc levels. Sufficiently large coupling capacitors should be used so that their impedance is negligible relative to the 50 presented by the ladder at the input and by the output buffer at the output.
Rev. A | Page 12 of 20
AD8368
GAIN CONTROL INTERFACE
The AD8368 has a linear-in-dB gain control interface that can be operated in either a gain-up mode or gain-down mode. In the gain-up mode with the MODE pin pulled high, the gain increases with increasing gain voltages. In the gain-down mode, with the MODE pin pulled low, the gain decreases with increasing gain voltages. In both modes of operation, the gain control slope is maintained at +37.5 dB/V or -38 dB/V (depending on mode selection) over temperature, supply, and process as VGAIN varies from 100 mV to 900 mV. To form an AGC loop with the on-board detector around the VGA, the MODE pin has to be pulled low. The gain functions for MODE pulled high and low are given respectively by:
GainHIGH (dB) = 37.5 x VGAIN - 14 GainLOW (dB) = -38 x VGAIN + 24.8
25 GAIN_H 20 15 10 ERROR_L 3 2 1 0 ERROR_H -1 -2 -3 GAIN_L -15 0 0.2 0.4 VGAIN (V) 0.6 0.8 -4 1.0 4
5 0 -5 -10
Figure 32. Gain and Conformance Error vs. VGAIN
where VGAIN is expressed in volts.
As shown in Figure 32, the gain function can be either an increasing or decreasing function of VGAIN, depending on the MODE pin.
Rev. A | Page 13 of 20
05907-035
CONFORMANCE ERROR (dB)
GAIN (dB)
AD8368 APPLICATIONS INFORMATION
VGA OPERATION
The AD8368 is a general-purpose VGA suitable for use in a wide variety of applications where accurate, continuous, linear-in-dB gain control over a broad range of frequencies is important. Its stability over temperature and supply in comparison to other variable-gain techniques can be traced back to the X-AMP architecture. While having an 800 MHz bandwidth, its low frequency operation can be extended by properly selecting CHPFL and CDECL. The typical connections for using the AD8368 in VGA mode are illustrated in Figure 33. The input (INPT) and output (OUTP) of the AD8368 should be externally ac-coupled to prevent disrupting the dc levels on the chip. Therefore, a sufficiently large coupling capacitor should be used such that the series impedance of the capacitor is negligible at the frequencies of interest.
VIN VPOS
The DECL pin provides the internal midsupply dc reference for the AD8368. It should be well decoupled to ground using a large capacitor with low ESR. The capacitors connected to the HPFL pin and DECL pin are used to control the low-pass corner frequency of the output offset correction loop. The resulting high-pass corner frequency is inversely proportional to their values.
AGC OPERATION
The AD8368 can be configured as a standalone AGC amplifier by using the on-board rms detector, as shown in Figure 34. The detector output, DETO, is an error current representing the difference of squares between the root-mean-square (rms) of the sensed signal and an internal reference of 63 mV rms. This error current is integrated on CDETO and connected to the GAIN pin to form the AGC loop. The 63 mV rms reference corresponds to 178 mV p-p for a sine wave but the detector accuracy is maintained for more complex signals such as Gaussian noise, complex envelopes, and multicarrier signals with high peak-to-average ratios.
VIN
ICOM
VGAIN 0V TO 1V
GAIN DETO HPFL DECL
+
MODE
ENBL
INPT
ICOM ICOM
VPSI
VPSI
VPOS
ICOM VPSI VPSI MODE ENBL INPT
X2
REF -
ICOM DECL DECL
DETI OCOM
RSSI CDETO
GAIN DETO HPFL R2 DECL
+
ICOM ICOM X2
REF -
AD8368
OCOM OUTP VPSO VPSO VPSI VPSI
VPSI
ICOM DECL DECL
05907-036
VPOS VOUT
DETI R1 OCOM
OCOM OUTP VPSO
AD8368
VPSO VPSI VPSI
VPSI
Figure 33. Typical Connections for VGA Mode for Increasing Gain with Increasing VGAIN (MODE High)
The gain control voltage ranging from 0 V to 1 V is applied to the GAIN pin. The MODE pin controls whether the gain of the part is an increasing or decreasing function of the gain voltage. When the MODE pin is pulled high, the gain increases with increasing gain voltages. When the MODE pin is pulled low, the gain decreases with increasing gain voltages. The ENBL pin is used to enable or disable the part. ENBL is active high; when ENBL is pulled low, the part is disabled and draws a fraction of the normal supply current.
VOUT
Figure 34. AGC Mode of Operation
The AGC mode of operation requires a specific gain direction. The gain must fall as VDETO increases to restore the needed balance against the setpoint. Therefore, the MODE pin must be pulled low. By connecting the signal at OUTP directly to the detector input (DETI), the output level is driven to the 63 mV rms reference setpoint.
Rev. A | Page 14 of 20
05907-037
VPOS
AD8368
The output setpoint can be increased using an external resistive divider network between OUTP and DETI, referenced to DECL as depicted in Figure 34. In this configuration, the rms output voltage is forced to (1 + R1/R2) 63 mV rms by the AGC loop. For a 0 dBm (224 mV rms referenced to 50 ) output setpoint, this ratio is 3.5. After correcting for the input impedance of DETI, the choice of R1 = 226 and R2 = 100 yields a setpoint of roughly 0 dBm. This very accurate leveling function is shown in Figure 35, where the rms output is held to within 0.2 dB of the 0 dBm setpoint for >30 dB range of input levels.
10 5 0
Figure 36 shows a plot of the RSSI voltage at DETO as input power is swept.
3.0
2.5
2.0
RSSI (V)
1.5
1.0
0.5
05907-039
POWER OUT (dBm)
-5 -10 -15 -20
05907-038
0 -40
-30
-20
-10 POWER IN (dBm)
0
10
20
Figure 36. Monitoring the GAIN/DETO RSSI Voltage vs. Input Power
-25 -30 -40
In some cases, it can be found that, if driven into AGC overload, the AD8368 requires unusually long times to recover; that is, the voltage at DETO remains at an abnormally high value, and the gain is at its lowest value. To avoid this situation, it is recommended that a clamp be placed on the DETO pin, as shown in Figure 37.
ICOM ICOM ICOM DECL DECL VPSI
-30
-20
-10 POWER IN (dBm)
0
10
20
Figure 35. Output Power vs. Input Power in AGC Mode at 140 MHz
Note that to achieve the accurate level of AGC output power, the DECL capacitor must be adjusted for the corresponding RF frequency. The DECL capacitor value varies depending on board parasitics. Table 5 shows the DECL capacitor value based on the evaluation board parasitics.
Table 5. DECL Capacitor Value
IF Frequency (MHz) 70 140 240 380 480 C4 (pF) 1000 270 68 33 15 C20 (pF) 2200 560 150 68 39
CAGC 0.1F
INPT ICOM MODE VPSI VPSI ENBL
OCOM DETO DECL HPFL GAIN DETI
VPSI VPSI VPSO
AD8368
VPSO OUTP OCOM
+VS
VAGC
RB 0.5V RA
05907-042
Q1 2N2907
A valuable feature of using a square law detector in AGC mode is that the RSSI voltage is a true reflection of signal power and can be converted to an absolute power measurement for any given source impedance. The RSSI in units of dBm referenced to 50 and based on the voltage available on the DETO pin is given by
RSSI = -11 + 20 log10(1 + R1/R2) + 38 x VDETO - 24.8
Figure 37. External Clamp to Prevent AGC Overload
The resistive divider network, RA and RB, should be designed such that the base of Q1 is driven to 0.5 V.
Rev. A | Page 15 of 20
AD8368
The choice of CDETO is a compromise of averaging time constant, response time, and carrier leakage. If CDETO is selected to be too small to speed up the response time, the AGC loop could start tracking and leveling any amplitude envelope and corrupt the constellation. Figure 38 illustrates a 16 QAM, 100 ksymbols per second constellation with a degraded error vector magnitude (EVM) of 5%. By increasing CDETO to 0.01 F, the EVM is improved to 1.1%.
REF -4.9dBm SR 10kHz CF 100MHz 16 QAM MEAS SIGNAL CONST DIAG
Figure 39 illustrates the measured EVM performance for a 16 QAM modulation at 10 Msymbols per second using CDETO = 1 nF.
10 9 8 7
EVM (%)
6 5 4 3 2 1 0 -40 -30 -20 -10 POWER IN (dBm) 0 10 20
05907-041
1U
Figure 39. Error Vector Magnitude Performance for 16 QAM 10 Msymbols per second
05907-040
-1U -1.31289U 262.578mU/ 1.31289U
Figure 38. Degraded Error Vector Magnitude Performance for 16 QAM at 100 ksymbols per second (CDETO Too Small)
Rev. A | Page 16 of 20
AD8368 EVALUATION BOARD
VPOS C20 1nF VPOS1 VPOS2 VPOS3
ICOM ICOM ICOM DECL
INPUT R1 10k LOW VPOS1 C13 0.1F ENABLE HI
CIN 10nF INPT ICOM SW1 MODE VPSI VPSI ENBL
DECL
VPSI
VPSI VPSI VPSO
R11 0 C11 1nF R12 0 COUT 10nF OUTPUT C12 1nF
VPOS2 C14 0.1F VPOS3 C15 0.1F
AD8368
R10 0 SW2 C10 1nF
VPSO OUTP OCOM
OCOM
ON OFF R2 10k
DETO
DECL
HPFL
GAIN
GAIN GAIN DET_OUT_TP R35 OPEN JP4 C23 10nF R32 OPEN C6 1nF C4 1nF
DETI
R31 OPEN
Figure 40. Evaluation Board
Table 6. Evaluation Board Configuration Options
Component R1, R2 R10, R11, R12, C10, C11, C12, C13, C14, C15 CIN COUT R31, R32 Function Pull-Down Resistors for MODE and ENBL. Supply Decoupling. Jumpers, power supply decoupling resistors, and filter capacitors. Default Conditions R1 = R2 = 10 k R10 = R11 = R12 = 0 C10 = C11 = C12 = 1 nF C13 = C14 = C15 = 0.1 F CIN = 10 nF COUT = 10 nF R31 = R32 = Open (VGA mode)
R35 C23 C1, R30 C6 C20, C4 JP4 SW1 SW2
RF Input. CIN provides dc block for RF input. RF Output. COUT provides dc block for RF output. Feedback Path for AGC Operation. For a default setpoint of 63 mV rms, set R31 = 0 and remove R32. For other AGC setpoints, rms voltage = (1 + n) x 63 mV rms, where n = R31/R32. Populate with 0 to feed detector output RSSI voltage to DET_OUT_TP. Sets the corner frequency of the output offset control loop high-pass filter. Used for driving the detector externally. Set R30 to 50 for matching. Set C1 to be a large ac coupling capacitor. DETO Capacitor. Needs to be made larger for lower data rates (see the AGC Operation section). DECL Capacitor. Needs to be adjusted based on RF frequency in AGC operation (see the AGC Operation section). Jumper for AGC Mode of Operation. Provides feedback from the detector output to the gain pin. Mode Switch. Low mode puts the part in gain-down mode. High puts the part in gain-up mode. AGC operation requires gain-down mode. Power-Down. The part is disabled when the enable pin is tied to ground.
R35 = Open C23 = 10 nF C1 = Open R30 = Open C6 = 1 nF C20 = C4 = 1 nF JP4 = not populated (VGA mode) SW1 = JP2 SW2 = JP3
Rev. A | Page 17 of 20
05907-043
C1 OPEN
R30 OPEN
DET_IN
AD8368 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.60 MAX 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP
19 18 EXPOSED PAD 24 1
PIN 1 INDICATOR 2.65 2.50 SQ 2.35
6
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
(BO TTOMVIEW)
13 12
7
0.23 MIN 2.50 REF
0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
SEATING PLANE
0.30 0.23 0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8
Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8368ACPZ-REEL7 1 AD8368ACPZ-WP1, 2 AD8368-EVALZ1
1 2
Temperature Range -40C to +85C -40C to +85C
Package Description 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board
Package Option CP-24-3 CP-24-3
Ordering Quantity 1,500 64
Z = RoHS Compliant Part. WP = waffle pack.
Rev. A | Page 18 of 20
AD8368 NOTES
Rev. A | Page 19 of 20
AD8368 NOTES
(c)2006-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05907-0-10/07(A)
Rev. A | Page 20 of 20

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