View SG6980_4112364.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Product Specification Single-Stage PFC Controller
SG6980 DESCRIPTION
The highly integrated SG6980 is designed for power supplies with boost power-factor-correction (PFC). It requires very few external components to achieve desirable operation and includes versatile protections / compensation. It is available in 16-pin DIP and SOP packages. The innovative switching-charge multiplier divider enhances the PFC circuit's noise immunity. The proprietary multi-vector control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, SG6980 shuts off to prevent extra-high voltage on output. The PFC gate driver can be synchronized with external SYNC signal and the switching noise can be reduced. During start-up, the RDY (ready) is pulled low until the PFC output voltage reaches the setting level. This signal can be used to control the second forward stage for proper power-on sequence. In addition, SG6980 provides complete protection functions, such as brownout and RI open/short.
FEATURES OVERVIEW
Innovative switching-charge multiplier divider Multi-vector control for improved PFC output transient response 1:1 Synchronous switching with SYNC Average current mode control Remote on/off control Power-on sequence control Programmable PFC output-voltage control Cycle-by-cycle current limiting Over-voltage and under-voltage protections Brownout and open-loop protections Low start-up and operating current
APPLICATIONS
Active-PFC switching power supplies TV and home appliances Computer and telecom
TYPICAL APPLICATION
SG6980
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
-1-
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980 PIN CONFIGURATION
MARKING DIAGRAMS
SG6980TP XXXXXXXYWWV
T: D = DIP S=SOP P: Z = Lead Free XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location
VRMS OTP RI IEA IPFC IMP IPK SYNC
IAC VEA FB RDY VDD OUT GND ON/OFF
ORDERING INFORMATION
Part Number
SG6980DZ SG6980SZ
Pb-Free Package
16-Pin DIP 16-Pin SOP
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
-2-
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
PIN DESCRIPTIONS
Name Pin
VRMS 1
Type
Line-Voltage Detection
Function
Line voltage detection. The pin is used for PFC multiplier and brownout protection. For brownout protection, the controller is disabled with a 195ms delay time when the VRMS voltage drops below 0.8V. There is a 200mV hysteresis for brownout protection. This pin supplies an over-temperature protection signal. A constant current is output from this pin. If RI is equal to 24k, the magnitude of the constant current is 50A. An external NTC thermistor must be connected from this pin to ground. The impedance of the NTC thermistor decreases whenever the temperature increases. Once the voltage of the OTP pin drops below 1.2V, the SG6980 is off, and auto restarts when the voltage is back to 1.4V. The resistance of a resistor connected between RI and ground determines the switching frequency. A resistance between 15k and 40K is recommended. The switching frequency is equal to [1560 / RI] kHz, where RI is in k. For example, if RI is equal to 24k, then the switching frequency is 65kHz. This is the output of the PFC current amplifier. The signal from this pin is compared with an internal sawtooth and determines the pulse width for PFC gate drive. The inverting input of the PFC current amplifier. Proper external compensation circuits will result in excellent input power factor via average-current-mode control. The non-inverting input of the PFC current amplifier and also the output of the multiplier. Proper external compensation circuits result in excellent input power factor via average-current-mode control. The peak current setting for PFC. This pin receives the external switching signal. The PFC switching can be synchronized by SYNC with 1:1 ratio. Active high. The SG6980 is disabled whenever the voltage at this pin is lower than 1V or the pin is open. When SG6980 is disabled by ON/OFF, the IDD current is lower than 35A. The ground. The totem pole output drive for the PFC MOSFET. This pin is internally clamped under 18V to protect the MOSFET. The power supply pin. The threshold voltages for start-up and turn-off are 12.5V and 10V, respectively. The operating current is lower than 5mA. This pin outputs a ready signal to control the power on sequence. Once the SG6980 is turned on and the FB (PFC feedback input) voltage is higher than 2.7V, this pin locks high impedance. Disabling the SG6980 resets this pin to the low. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. The error amplifier output for PFC voltage feedback loop. A compensation network (usually a capacitor) is connected between this pin and ground. A large capacitor value results in a narrow bandwidth and improves the power factor. This input is used to provide current reference for the multiplier. The suggested maximum IAC is 350A.
OTP
2
Over-Temperature Protection
RI
3
Oscillator Setting
IEA IPFC
4 5
Current Amplifier Output Inverting Input for PFC Current Amplifier Non-inverting Input for PFC Current Amplifier and Output of Multiplier Peak Current Limit Synchronous Signal Remote On/Off Ground Gate Drive Supply
IMP IPK SYNC
6 7 8
ON/OFF 9 GND OUT VDD 10 11 12
RDY
13
Ready Signal Output
FB
14
Feedback Input
VEA
15
Error Amplifier Output
IAC
16
Input AC Current
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
-3-
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
BLOCK DIAGRAM
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
-4-
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
ABSOLUTE MAXIMUM RATING
Symbol
VVDD IAC VHigh VLow PD TJ TA TSTG Rj-C TL VESD,HBM VESD,MM
Parameter
DC Supply Voltage* Input AC Current OUT, SYNC, ON/OFF, RDY Others Power Dissipation Operating Junction Temperature Operating Ambient Temperature Range Storage Temperature RDY Thermal resistance (Junction-to-Case) Lead Temperature (Wave Soldering or IR, 10 Seconds) ESD Capability, Human Body Model ESD Capability, Machine Model
Value
25 2 -0.3 to 25V -0.3 to 7V DIP SOP +150 -20~+125 -55 to +150 DIP SOP 260 4 250 36.70 37.76 0.8 0.4
Unit
V mA V V W /W KV V
*All voltage values, except differential voltages, are given with respect to the network ground terminal. *Stress beyond those listed under "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the device.
ELECTRICAL CHARACTERISTICS
VDD=15V, TA=25C unless otherwise noted.
VDD Section
Symbol
VDD-OP IDD-OP I IC-OFF IDD-ST VDD-ON VDD-OFF VDD-OVP tD-VDDOVP
Parameter
Continuously Operating Voltage Operating Current Input Current Start-up Current Start Threshold Voltage Minimum Operating Voltage VDD Over-Voltage Protection with a Debounce Time Debounce Time of VDD OVP
Test Conditions
RI= 24K,VDD = 15V; Gate Open VON/OFFMin.
Typ.
4 25 10
Max. Unit
20 5 35 20 13.5 11 25.5 40 V mA A A V V V s
11.5 9 23.5 10
12.5 10 24.5
Oscillator & Green-Mode Operation
Symbol
FOSC RI RIOPEN RISHORT
Parameter
PWM Frequency Nominal RI Value Maximum RI Value for Protection Maximum RI Value for Protection
Test Conditions
RI= 24K
Min.
62 15
Typ.
65 200 2
Max. Unit
68 40 KHz K K K
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
-5-
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
VRMS for UVP and RDY
Symbol
VRMS-UVP-1 VRMS-UVP-2 tUVP
Parameter
RMS AC Voltage Under-Voltage Threshold (with TUVP Delay) Recovery Level on VRMS for UVP Mode Under-Voltage Protection Propagation Delay Time (No Delay at Start-up)
Test Conditions
Min.
0.75
Typ.
0.80
Max.
0.85
Unit
V
VRMS-UVP-1 VRMS-UVP-1 VRMS-UVP-1 V +0.18 +0.20 +0.22 150 195 240 ms
Voltage Error Amplifier
Symbol
VREF Av Zo OVPFB OVPFB tOVP-PFC VFB-H GFB-H VFB-L GFB-L IFB-L UVPFB tUVP-PFC
Parameter
Reference Voltage Open-Loop Gain Output Impedance PFC Over-Voltage Protection on FB PFC Feedback Voltage Protection Hysteresis Debounce Time of PFC OVP Clamp-High Feedback Voltage Clamp-High Gain Clamp-Low Feedback Voltage Clamp-Low Gain Clamp-Low Maximum Current PFC Feedback Under-Voltage Protection Debounce Time of PFC Feedback UVP
Test Conditions
Min.
2.95
Typ.
3 60 110
Max.
3.05
Unit
V dB K
1.066 * VREF 60 40 1.033 * VREF 0.916 * VREF 1.5 0.35 40
1.083 * VREF 90 70 1.050 * VREF 500 0.950 * VREF 6.5 2 0.40 70
1.100 * VREF 120 120 1.066 * VREF 0.966 * VREF
V mV s V A/mV V A/mV mA
0.45 120
V s
Current Error Amplifier
Symbol
VOFFSET AI BW CMRR VOUT-HIGH VOUT-LOW IMR1, IMR2 IL IH
Parameter
Input Offset Voltage ((-) > (+)) Open-Loop Gain Unit Gain Bandwidth Common-Mode Rejection Ratio Output High Voltage Output Low Voltage Reference Current source Maximum Source Current Maximum Sink Current
Test Conditions
Min.
Typ.
8 60 1.5
Max.
Unit
mV dB MHz dB V
VCM = 0 ~ 1.5V 3.2
70 0.2
V A mA mA
RI=24K (IMR=20+IRI * 0.8)
50 3 0.25
70
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
-6-
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
Peak Current Limit
Symbol
IP VPK tPD-PFC tLEB-PFC
Parameter
Constant Current Output Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit (Vsense < Vpk) Propagation Delay Leading-Edge Blanking Time
Test Conditions
RI = 24K VRMS=1.05V VRMS=3V
Min.
90 0.15 0.35 250
Typ.
100 0.20 0.40 330
Max. Unit
110 0.25 0.45 200 430 A V V ns ns
Multiplier
Symbol
IAC IMO-MAX IMO-1 IMO-2 VIMP
Parameter
Input AC Current Maximum Multiplier Current Output Multiplier Current Output (Low-Line, High-Power) Multiplier Current Output (High-Line, High-Power) Voltage of IMP Open
Test Conditions
Linear RDY RI=24 K VRMS=1.05V; IAC=90A; VEA=7.5V; RI=24K VRMS=3V; IAC=264A; VEA=7.5V; RI=24K
Min.
0 230 200 65 3.4
Typ.
250 250 85 3.9
Max. Unit
360 A A 280 A A 4.4 V
PFC Output Driver
Symbol
VZ VOL VOH tR tF DCYMAX
Parameter
Output Voltage Maximum (clamp) Output Voltage Low Output Voltage High Rising Time Falling Time Maximum Duty Cycle
Test Conditions
VDD=20V VDD = 15V; IO = 100mA VDD = 13V; IO = 100mA VDD = 15V; CL = 5nF; OUT = 2V to 9V VDD = 15V; CL = 5nF; OUT = 9V to 2V
Min.
Typ.
15
Max. Unit
18 1.5 V V V ns ns %
8 30 30 93 70 50 120 100 98
RDY Section
Symbol
FB-RDY-high IFB-RDY-high VOL tRDY-delay time tRDY-UVP_delay time
Parameter
FB Voltage, RDY High Impedance Input Leakage Current, RDY High Impedance Output Voltage Low, RDY Failed Interval Between FB > 2.7V and RDY High Impedance Delay Time Between Gate off and RDY Pull Low when UVP Occurs
Test Conditions
FB=2.5V ISINK =1mA
Min.
Typ.
2.7
Max. Unit
V 500 0.5 nA V ms ms
4 10
6 16
OTP Section
Symbol
IOTP VOTP-OFF VOTP-ON TOTP
Parameter
OTP Pin Output Current OTP Threshold Voltage Recovery Level on OTP OTP Debounce Time
Test Conditions
RI = 24K
Min.
90 1.15 1.35 10
Typ.
100 1.20 1.40
Max.
110 1.25 1.45 40
Unit
A V V s
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
-7-
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
SYNC Section
Symbol
VSYNC-HIGH VSYNC-LOW FMin FMax tMIN_PULSE_W tMAX_PULSE_W tD-65KHZ tD-50KHZ
Parameter
Synchronizing Signal High Threshold Synchronizing Signal Low Threshold Minimum Synchronizing Frequency Maximum Synchronizing Frequency Minimum Synchronizing Pulse Width Maximum Synchronizing Pulse Width Delay Time Between SYNC and OUT, Switching Frequency = 65KHz Delay Time Between SYNC and OUT, Switching Frequency = 50KHz
Test Conditions
Min.
3.5
Typ.
Max. Unit
V 0.9 V KHz 150 KHz ns s 3 3 s s
RI=24K RI = 24K RI = 24K RI=24K RI=31.2K
FOSC-6 100 200 15.8 1 1 500
ON/OFF Section
Symbol
Ron/off VON VOFF
Parameter
Impedance of ON/OFF Pin Enable Signal High Threshold Enable Signal Low Threshold
Test Conditions
Min.
18 3
Typ.
27
Max. Unit
50 1 K V V
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
-8-
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
TYPICAL CHARACTERISTICS
Operating Current (IDD OP) vs Temperature
6 .0 5 .5 5 .0 4 .5 4 .0 3 .5 3 .0 -40 -25 -1 0 5 20 35 50 65 80 95 1 10 12 5
2.90 -40 -25 -10 5 20 35 50 65 80 95 110 125 3.05 3.10
Reference Voltage (V REF) vs Temperature
IDD OP (mA)
V REF (V)
3.00
2.95
Temperature ( )
Temperature ( )
Start Threshold Voltage (V DD-ON ) vs Temperature
1 3.0
Min. Operating Voltage (V DD-OFF ) vs Temperature
16 .0 14 .0
1 2.8
V DD-OFF (V)
V DD-ON (V)
1 2.6
12 .0 10 .0 8 .0 6 .0
1 2.4 1 2.2
1 2.0 -4 0 -2 5 -10 5 20 35 50 65 80 95 11 0 1 25
-4 0
-25
-1 0
5
20
35
50
65
80
95
11 0
125
Temperature ( )
Temperature ( )
PW M frequency (FOSC ) vs Temperature
6 6 .0 6 5 .0
5 .00
Minimum synchronizing frequency (Fmin ) vs Temperature
4 .00
FOSC (KHz)
6 4 .0 6 3 .0 6 2 .0 6 1 .0 -4 0 -25 -1 0 5 20 35 50 65 80 95 11 0 12 5
Fmin ( KHz)
3 .00
2 .00 1 .00
0 .00 -4 0 -25 -1 0 5 20 35 50 65 80 95 11 0 1 25
Temperature ( )
Temperature ( )
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
-9-
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
0 .90
RMS AC Voltage Under-voltage Threshold (V RMS-UVP-1) vs Temperature
1 20 .0 1 10 .0
PFC Feedback Voltage Protection Hysteresis ( OVP FB ) vs Temperature
0 .85
OVP FB (mV)
V RMS-UVP-1 (V)
1 00 .0 90 .0 80 .0 70 .0
0 .80
0 .75
0 .70 -4 0 -25 -1 0 5 20 35 50 65 80 95 1 10 12 5
-40
-25
-10
5
20
35
50
65
80
95
1 10
1 25
Temperature ( )
Temperature ( )
Multiplier Current Output (IMO-1 ) vs Tem perature
2 5 0.0 2 4 8.0
80 .0 79 .0
Multiplier Current Output (IMO-2 ) vs Temperature
IMO-1 (uA)
2 4 4.0 2 4 2.0 2 4 0.0 -40 -2 5 -1 0 5 20 35 50 65 80 95 1 10 12 5
IMO-2 (uA)
2 4 6.0
78 .0 77 .0 76 .0 75 .0 -40 -25 -1 0 5 20 35 50 65 80 95 11 0 1 25
Temperature ( )
Temperature ( )
OTP Threshold Voltage (V OTP-OFF ) vs Temperature
1 .3 0
Recovery Level on OTP (V OTP-ON ) vs Temperature
1.4 3
1 .2 5
1.4 1
V OTP-OFF (V)
V OTP-ON (V)
1 .2 0
1.3 9
1 .1 5
1.3 7
1 .1 0 -40 -2 5 -1 0 5 20 35 50 65 80 95 11 0 1 25
1.3 5 -4 0 -25 -1 0 5 20 35 50 65 80 95 11 0 125
Temperature ( )
Temperature ( )
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
- 10 -
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
OPERATION DESCRIPTION
The highly integrated SG6980 is designed for a power supply with boost PFC. It requires very few external components to achieve high performance and includes versatile protections / compensation. The PFC function is implemented by average current mode control. The patented switching-charge multiplier-divider provides a high-degree of noise immunity for the PFC circuit. This enables the PFC circuit to operate over a much wider region. The proprietary multi-vector output voltage control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, the SG6980 shuts off PFC to prevent extra-high voltage on output. Programmable two-level high/low line compensation optimizes THD performance. In addition, SG6980 provides complete protection functions, such as brownout and RI open/short.
Line Voltage Detection (VRMS)
Figure 1 shows a resistive divider with low-pass filtering for line-voltage detection on the VRMS pin. The VRMS voltage is used for the PFC multiplier, brownout protection, and RDY control. For brownout protection, the SG6980 is disabled with 195ms delay time if the voltage VRMS drops below 0.8V. For PFC multiplier and RDY control, please refer to below sections for more detail.
Switching Frequency and Current Sources
The switching frequency of SG6980 can be programmed by the resistor RI connected between RI pin and GND. The relationship is: FIG.1
fPWM =
1560 (kHz ) ------------RI (k)
PFC Output Voltage Control
(1) For a universal input (90VAC ~ 264VAC) power supply applying active boost PFC and forward as a second stage, the output voltage of PFC is usually designed around 400V.
For example, a 24k resistor RI results in a 65kHz switching frequency. Accordingly, constant current IT flows through RI.
Vo =
RA + RB x 3V ---RB
(3)
I
T
=
1.2V RI (k )
(mA) ----------------
(2)
IT is used to generate internal current reference. If there is a SYNC signal input, the switching frequency is defined by the SYNC signal. The SNYC frequency must be larger than the programmed switching frequency, less 6KHz.
FIG.2 Output Voltage Setting
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0) - 11 www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
ON/OFF
For ON/OFF control, the SG6980 is disabled immediately if the voltage at this pin is below 1V. Usually, the pin opens when turn off can have the best power saving. The operating current during turn off is less than 35A.
SYNC Signal Section
The SG6980 can synchronize the OUT and synchronize signals provided by second stage, which reduces switching noise and the ripple on output voltage. Figure 3 shows the relationship between the OUT and SYNC signals. FIG.4 Multiplier and Control Loop of PFC Stage The current source output from the switching-charge multiplier/divider can be expressed as:
IAC x VEA IMO = K x (A ) ----------------VRMS 2
(4)
IMP, the current output from IMP pin, is the summation of IMO and IMR1. IMR1 and IMR2 are identical, fixed-current sources. R2 and R3 are also identical. They are used to pull high the operating point of the IMP and ICS pins if the voltage across RS goes negative with respect to ground. FIG.3 Synchronized Interleaving-Switching Through the differential amplification of the signal across Rs, better noise immunity is achieved. The output of IEA is compared with an internal sawtooth and the pulse width for PFC is determined. Through the average current-mode control loop, the input current IS is proportional to IMO:
RDY Signal Section
SG6980 provides a RDY pin to inform the next stage and other applications. RDY signal is high impedance when the FB voltage goes up to 2.7V and delays around 5ms. Use the pin to turn on the second stage PWM when the bulk capacitor voltage is high enough. In SG6980, the RDY pin (open-drain structure) is used for next-stage-ready signal.
IMO x R 2 = IS x RS ---------------
(5)
According to Equation 5, the minimum value of R2 and maximum of RS can be determined because IMO should not exceed the specified maximum value. There are different concerns in determining the value of the sense resistor, RS. The value of RS should be small enough to reduce power consumption, large enough to maintain the resolution. A current transformer (CT) may be used to improve the efficiency of high-power converters. To achieve a good power factor, the voltage for VRMS and VEA should be kept as DC as possible, according to Equation 4. Good RC filtering for VRMS and narrow bandwidth (lower than the line frequency) for voltage loop are suggested for better input current shaping. The transconductance error amplifier has output impedance RO and a capacitor CEA (1F ~ 10F) connected to ground (as shown in Figure 4). This establishes a dominant pole f1 (per Equation 6) for the voltage loop.
PFC Operation
The purpose of a boost active power factor corrector (PFC) is to shape the input current of a power supply. The input current waveform and phase follow that of the input voltage. Using SG6980, average-current-mode control is utilized for continuous-current-mode operation for the PFC booster. With the innovative multi-vector control for voltage loop and switching-charge multiplier/divider for current reference, excellent input power factor is achieved with good noise immunity and transient response. Figure 4 shows the total control loop for the average-current-mode control circuit of SG6980.
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
- 12 -
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980 Cycle-by-Cycle Current Limiting
f1 =
1 2 x R0 x CEA
----------------------------
(6)
The average total input power can be expressed as:
Pin = Vin(rms) x Iin(rms) VRMS x IMO VRMS x IAC x VEA VRMS 2 Vin x VEA R AC VRMS 2 VEA
SG6980 provides cycle-by-cycle current limiting for PFC stages. Figure 6 shows the peak current limit for the PFC stage. The PFC gate drive is terminated once the voltage on IPK pin goes below VPK. The voltage of VRMS determines the voltage of VPK. The relationship between VPK and VRMS is shown in Figure 6.
--------------
(7)
The amplitude of the constant current IP is determined by the internal current reference IT, according to the equation:
VRMS x
From Equation 7, VEA, the output of the voltage error amplifier, controls the total input power and the power delivered to the load.
Ip = 2 x I
T
= 2x
1.2V ----------------------R I
(8)
Therefore the peak current of the IS is given by:
Multi-Vector Error Amplifier
The voltage-loop error amplifier of SG6980 is transconductance, which has high output impedance (> 90k). A capacitor CEA (1F ~ 10F) connected from VEA to ground provides a dominant pole for the voltage loop. Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of the PFC output voltage. Figure 5 shows the voltage loop with multi-vector for fast transient error amplifier. When the variation of the feedback voltage exceeds 5% of the reference voltage, the transconductance error amplifier adjusts its output impedance to increase the loop response. If the feedback resistance is opened, SG6980 shuts off immediately to prevent extra-high voltage on the output capacitor.
IS_peak =
(Ip x RP) - V pk RS
------------------
(9)
FIG.6 Current Limit
Gate Drivers
SG6980 output stages are fast totem-pole gate drivers. The output driver is clamped by an internal 18V Zener diode to protect the power MOSFET.
Over-Temperature Protection
SG6980 provides an OTP pin for over-temperature protection. A constant current is output from this pin. If RI is equal to 24k, the magnitude of the constant current is 50A. An external NTC thermistor must be connected from this pin to ground. When the OTP voltage drops below 1.2V, SG6980 shuts down. SG6980 auto restarts when the OTP voltage is higher than 1.4V. FIG. 5 Voltage Error Amplifier with Multi-Vector
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
- 13 -
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
Protections & Built-in Latch Circuit
The SG6980 provides full protection functions to prevent the power supply and the load from being damaged. The protection features include:
PFC Feedback Over-Voltage Protection. When the PFC feedback voltage exceeds the over-voltage threshold, the SG6980 inhibits the PFC switching signal. This protection prevents the PFC power converter from operating abnormally while the FB pin is open. PFC Feedback Under-Voltage Protection. The SG6980 stops the PFC switching signal whenever the PFC feedback voltage drops below the under-voltage threshold. This protection feature is designed to prevent the PFC power converter from experiencing abnormal conditions while the FB pin is shorted to ground. VDD Over-Voltage Protection. The built-in clamping circuit clamps VDD whenever the VDD voltage exceeds the over-voltage threshold. RI Pin Open / Short Protection. The RI pin is used to set the switching frequency and internal current reference. If the RI pin is short or open, SG6980 is off. 2 provides a signal ground. It should be connected directly to the decoupling capacitor CDD and/or to the ground pin. The ground trace 3 is independently tied from the decoupling capacitor to the PFC output capacitor CO. The ground in the output capacitor CO is the major ground reference for power switching. To provide a good ground reference and reduce the switching noise of both the PFC and PWM stages, the ground traces 6 and 7 should be located very near and be low impedance.
The ICS pin is connected directly to RS through R3 to improve noise immunity. (Beware that it may incorrectly be connected to the ground trace 2). The IMP and IPK pins should also be connected directly, via the resistors R2 and RP, to another terminal of RS.
PCB Layout
SG6980 has a single ground pin. High sink currents in the output therefore cannot be returned separately. Good high-frequency or RF layout practices should be followed. Avoid long PCB traces and component leads. Locate decoupling capacitors near the SG6980. A resistor of 5 ~ 20 is recommended, connecting in series from the output to the gate of the MOSFET. Isolating the interference between the PFC and PWM stages is also important. Figure 7 shows an example of the PCB layout. The ground trace 1 is connected from the ground pin to the decoupling capacitor, which should be low impedance and as short as possible. The ground trace
FIG. 7 PCB Layout
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
- 14 -
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
REFERENCE CIRCUIT
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
- 15 -
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
PACKAGE INFORMATION 16 PINS - PLASTIC DIP (D)
D
16 9
E1
1 8
E
eB
A2 L e b1 A1
A
Dimensions:
Symbol A A1 A2 b b1 D E E1 e L eB Millimeter Min. 0.381 3.175 Inch Min. 0.015 0.125
Typ.
Max. 5.334 3.429
Typ.
Max. 0.210 0.135
18.669 6.121 2.921 8.509 0
3.302 1.524 0.457 19.177 7.620 6.299 2.540 3.302 9.017 7
19.685 6.477 3.810 9.525 15
0.735 0.241 0.115 0.335 0
0.130 0.060 0.018 0.755 0.300 0.248 0.100 0.130 0.355 7
0.775 0.255 0.150 0.375 15
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
- 16 -
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
16 PINS - PLASTIC SOP (S)
16 9
E
H
Detail A
1
b e
8
F
c
D A2 y A1 A
L Detail A
Dimension:
Symbol A A1 A2 b c D E e H L F y Millimeter Min. 1.346 0.101 1.244 Inch Min. 0.053 0.004 0.049
Typ.
Max. 1.753 0.254 1.499
Typ.
Max. 0.069 0.010 0.059
0.406 0.203 9.804 3.810 1.270 5.791 0.406 0.381X45 0 0.101 8 0 6.198 1.270 0.228 0.016 10.008 3.988 0.386 0.150
0.016 0.008 0.394 0.157 0.050 0.244 0.050 0.015X45 0.004 8
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
- 17 -
www.sg.com.tw * www.fairchildsemi.com September 17, 2007
Product Specification Single-Stage PFC Controller
SG6980
(c) System General Corp. Version 1.0.1 (IAO33.0064.B0)
- 18 -
www.sg.com.tw * www.fairchildsemi.com September 17, 2007

▲Up To Search▲

Price & Availability of SG6980

	To Download SG6980 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .