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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CVF857
1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
Product Features
* Operating Frequency up to 220 MHz for PC3200 Registered DIMM applications * Distributes one differential clock input pair to ten differential clock output pairs * Inputs (CLK,CLK) and (FBIN,FBIN) * Input PWRDWN: LVCMOS * Outputs (Yx, Yx), (FBOUT, FBOUT) * External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input * Operates at 2.5V for PC1600, PC2100, PC2700, and 2.6V for PC3200 * Packaging (Pb-free & Green available, select packages): - 48-pin TSSOP - 40-pin TQFN - 56-ball VFBGA
Product Description
PI6CVF857 PLL clock device is developed for registered DDR DIMM applications. The device is a zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]), and one differential pair feedback clock outputs (FBOUT,FBOUT) . The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V LVCMOS input (PWRDWN), and the Analog Power input (AVDD). When input PWRDWN is low while power is applied, the input receivers are disabled, the PLL is turned off, and the differential clock outputs are 3-stated. When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. When the input frequency falls below a suggested detection frequency that is below the operating frequency of the PLL, the device will enter a low power mode. An input frequency detection circuit will detect the low frequency condition and perform the same low power features as when the PWRDWN input is low. The PLL in the PI6CVF857 clock driver uses the input clocks (CLK, CLK) and the feedback clocks (FBIN,FBIN) to provide high-performance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]). The PI6CVF857 is also able to track Spread Spectrum Clocking for reduced EMI.
Block Diagram
Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT
CLK CLK FBIN FBIN PLL
PWRDWN AVDD
Powerdown and Test Logic
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VDDQ
Y5 VDDQ
Y6
Y1
Y1
Y0
GND Y2 Y2 VDDQ CLK CLK VDDQ AVDD AGND GND
1 2 3 4 5 6 7 8 9
40 39 38 37 36 35 34 33 32 31
Y0
Y5
Y6
VDDQ
Y9
Y3
Y3
Y4
Y4 Y9
VDDQ
Y8
Ball Configuration VFBGA (NF)
Ball Configuration
1 A Y0 Y1 GND Y2 VDDQ CLK VDDQ AGND Y3 Y4 2 Y0 Y1 GND Y2 VDDQ CLK AVDD GND Y3 Y4 3 GND VDDQ NC NC NB NB NC NC VDDQ GND 4 GND VDDQ NC NC NB NB NC NC VDDQ GND 5 Y5 Y6 GND Y7 VDDQ FBIN FBOUT GND Y8 Y9 6 Y5 Y6 GND Y7 PWRDWN FBIN VDDQ FBOUT Y8 Y9
1 A B C D E F G H J K
2
3
4
5
6
B C D E F G H J
NO CONNECT on C3, C4, D3, D4, G3, G4, H3 and H4
K
Notes: NC = No Contact NB = No Ball
Y8
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
Pin Configuration TSSOP ( A)
GND Y0 Y0 VD D Q Y1 Y1 GND GND Y2 Y2 VD D Q VD D Q CLK CLK VD D Q AV D D AG N D GND Y3 Y3 VD D Q Y4 Y4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND Y5 Y5 VD D Q Y6 Y6 GND GND Y7 Y7 VD D Q P W R DW N FBIN FBIN VD D Q FBOUT FBOUT GND Y8 Y8 VD D Q Y9 Y9 GND
Pin Configuration QFN (ZD)
30 29 28 27 26 25 24 23 22
Y7 Y7 VDDQ PWRDWN FBIN FBIN VDDQ VDDQ FBOUT FBOUT
48-Pin A
GND
21 10 11 12 13 14 15 16 17 18 19 20
2
PS8683B
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
Pinout Table
Pin Name CLK CLK Yx Yx FBOUT FBOUT FBIN FBIN PWRDWN VDDQ AVDD AGND GND Reference Clock input Clock outputs. Complement Clock outputs. Feedback output, and Complement Feedback Output Feedback Input, and Complement Feedback Input Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and the differential clock outputs are disabled to a - state. When PWRDWN = 1, all differential clock outputs are enabled and run at the same frequency as CLK. Power Supply for I/O. Analog /core power supply. AVDD can be used to bypass the PLL for testing purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Analog/core ground. Provides the ground reference for the analog/core circuitry Ground De s cription
Function Table
Inputs AVDD GND GND X X Nominal(2) Nominal(2) Nominal(2) PWRDWN H H L L H H X CLK L H L H L H < 20 CLK H L H L H L MHz (1) Y L H Z Z L H Z Y H L Z Z H L Z Outputs FBOUT L H Z Z L H Z FBOUT H L Z Z H L Z Bypassed/off Bypassed/off off off on on off PLL
Notes: 1. For testing and power saving purposes, PI6CVF857 will power down if the frequency of the reference inputs CLK, CLK is well below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CVF857 will be powered down when the CLK,CLK stop running. 2. AVDD Nominal is 2.5V for PC1600, PC2100, and PC2700. AVDD Nominal is 2.6V for PC3200. Z = High impedance X = Don't care
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol VDDQ, AVDD VI VO IIK IOK IO IO(PWR) Tstg JA JC Parame te r I/O supply voltage range and analog/core supply voltage range Input voltage range Output voltage range Input Clamp Current Output Clamp Current Continuous output Current Continuous current through each AVDD, VDDQ, or GND Storage temperature Junction to ambient thermal (package A) Junction to case thermal (package A) M in. - 0.5 - 0.5 - 0.5 - 50 - 50 - 50 - 100 - 65 M a x. 3.6 VDDQ +0.5 50 50 50 100 150 10 4 38
o o oC
Units
V
mA
C/w C/w
Note: Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
DC Specifications
Recommended Operating Conditions
Symbol AVDD VDDQ VIL VIH IOH IOL VIX VIN VID TA Analog/core supply voltage Output supply voltage Low- level input voltage for PWRDWN pin High- level input voltage for PWRDWN pin High- level output current Low- level output current Input differential- pair crossing voltage Input voltage level Input differential voltage between CLK and CLK Operating free air temperature DC AC PC1600 - PC2700 P C 3200 Parame te r M in. VDDQ - 0.12 2.3 2.5 -0.3 1. 7 - - (VDDQ/2) -0 . 2 -0.3 0.36 0.7 -40 Nom. VDDQ 2.5 2.6 M ax. 2.7 2.7 2.7 0.7 VDDQ +0.3 12 -12 (VDDQ/2) +0.2 VDDQ +0.3 VDDQ +0.6 VDDQ +0.6 85 C V mA V Units
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
Timing Requirements for PC1600 ~ PC2700 (Over recommended operating free-air temperature)
Symbol De s cription Operating clock frequency(1,2) Application clock frequency(3) Input clock duty cycle PLL stabilization time after powerup AVDD, VDDQ = 2.5V 0.2V M in. 60 95 40 M a x. 170 170 60 100 Units
fCK tDC tSTAB
MHz % s
Notes: 1. The PLL is able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing parameters. (Used for low-speed debug). 3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
Electrical Characteristics for PC1600 ~ PC2700 (Over recommended operating free-air temperature)
Parame te r VIK VOH All inputs High output voltage Te s t Conditions II = -18mA IOH = -100A IOH = -12mA IOL = 100A IOL = 12mA VI = VDDQ or GND VI = VDDQ or GND AVDD, VDDQ 2.3V 2.3 to 2.7V 2.3V 2.3 to 2.7V 2.3V 2.7V 2.7V VDDQ- 0.1 1.7 0.1 0.6 10 A 200 2.7V 2.7V 2.5V 2.0 300 12 3.5 pF VI = VDDQ or GND 2.5V -0 . 2 5 0.25 mA mA V M in. Typ. M ax. -1.2 Units
VOL
Low output voltage CLK, FBIN PWRDWN
II IDDPD IDDQ IADD CI
CLK & CLK = 0 MHz, Static supply current IDDQ + IADD PWRDWN = Low Dynamic supply current of VDDQ Dynamic supply current of AVDD CLK and CLK FBIN and FBIN CLK and CLK(5) FBIN and FBIN(5) CLK & CLK = 170 MHz All outputs are open CLK & CLK = 170 MHz VI = VDDQ or GND
CI()
Note: 4. The maximum power-down clock frequency is below 20 MHz. 5. Guaranteed by design, but not production tested.
5
PS8683B
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
Timing Requirements for PC3200 (Over recommended operating free-air temperature)
Symbol De s cription Operating clock frequency(1,2) Application clock frequency(3) Input clock duty cycle PLL stabilization time after powerup AVDD, VDDQ = 2.6V 0.1V M in. 60 95 40 M a x. 220 220 60 100 Units
fCK tDC tSTAB
MHz % s
Notes: 1. The PLL is able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing parameters. (Used for low-speed debug). 3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
Electrical Characteristics for PC3200 (Over recommended operating free-air temperature)
Parame te r VIK VOH All inputs High output voltage Te s t Conditions II = -18mA IOH = -100A IOH = -12mA IOL = 100A IOL = 12mA VI = VDDQ or GND VI = VDDQ or GND AVDD, VDDQ 2.5V 2.5 to 2.7V 2.5V 2.5 to 2.7V 2.5V 2.7V 2.7V VDDQ- 0.1 1.7 0.1 0.6 10 A 200 2.7V 2.7V 2.6V 2.0 300 12 3.5 pF VI = VDDQ or GND 2.6V -0 . 2 5 0.25 mA mA V M in. Typ. M ax. -1.2 Units
VOL
Low output voltage CLK, FBIN PWRDWN
II IDDPD IDDQ IADD CI
CLK & CLK = 0 MHz, Static supply current IDDQ + IADD PWRDWN = Low Dynamic supply current of VDDQ Dynamic supply current of AVDD CLK and CLK FBIN and FBIN CLK and CLK(5) FBIN and FBIN(5) CLK & CLK = 200 MHz All outputs are open CLK & CLK = 200 MHz VI = VDDQ or GND
CI()
Note: 4. The maximum power-down clock frequency is below 20 MHz. 5. Guaranteed by design, but not production tested.
6
PS8683B
10/17/03
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
AC Specifications for PC1600 ~ PC2700
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 )
Parame te r tjit(cc) t() tsk(o) tjit(per) tjit(hper) tsl(i) tsl(o) VOX
De s cription Cycle- to- cycle jitter Static phase offset(1) Output clock skew Period jitter Half- period jitter Input clock slew rate Output clock slew rate(2) Output differential- pair cross- voltage
Diagram Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 9
AVDD, VDDQ = 2.5V 0.2V M in. -50 -50 0 Nom. M ax 50 50 75 -75 -100 1. 0 1.0 (VDDQ/2) -0.1 75 100 4.0 2.0 (VDDQ/2) +0.1
Units
ps
V/ns V
The PLL is capable of meeting all the above parameters while supporting SSC synthesizers with the following parameters SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth(4) Phase angle
Notes: 1. Static Phase offset does not include Jitter. 2. The Output Skew Rate is calculated by using the load shown in Figure 3. 3. VOX specified at the DRAM clock input or the test load in Figure 2. 4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
30.00 0.00 2
50.00 -0.50
kHz % MHz
-0.031
degrees
7
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
AC Specifications for PC3200
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 )
Parame te r tjit(cc) t() tsk(o) tjit(per) tjit(hper) tsl(i) tsl(o) VOX
De s cription Cycle- to- cycle jitter Static phase offset(1) Output clock skew Period jitter Half- period jitter Input clock slew rate Output clock slew rate(2) Output differential- pair cross- voltage
Diagram Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 9
AVDD, VDDQ = 2.6V 0.1V M in. -50 -50 0 Nom. M ax 50 50 75 -5 0 -75 1.0 1.0 (VDDQ/2) -0.1 50 75 4.0 2.0 (VDDQ/2) +0.1
Units
ps
V/ns V
The PLL is capable of meeting all the above parameters while supporting SSC synthesizers with the following parameters SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth(4) Phase angle
Notes: 1. Static Phase offset does not include Jitter. 2. The Output Skew Rate is calculated by using the load shown in Figure 3. 3. VOX specified at the DRAM clock input or the test load in Figure 2. 4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
30.00 0.00 2
50.00 -0.50
kHz % MHz
-0.031
degrees
8
PS8683B
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VDDQ
GND
Z=60
Z=60
Figure 2. Output Load Test Circuit 1
Figure 1. IBIS Model Output Load
VDD
9 C=14pF C=14pF R=120
VCLK
VCLK
R=60
R=60
VDD/2
PROBE
GND
GND
PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
R=1M C=1pF
R=1M C=1pF
PS8683B
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-VDD/2
VDD/2
Z=60
Z=60
Figure 3. Output Load Test Circuit 2
C=14pF
C=14pF
-VDD/2
R=10
R=10
10 -VDD/2 Z=50 Z=50
VTT = GND
Scope
VTT
VTT
PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
R=50
R=50
PS8683B
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
Yx,FBOUT Yx,FBOUT
t cycle n t jit(cc) = t cycle n - t cycle n+1
t cycle n+1
Figure 4. Cycle-to-Cycle Jitter
CLK CLK FBIN FBIN
t(
)n
t(
n=N
) n+1
t
1 =
t(
)n (N > 1000 samples)
N
Figure 5. Static Phase Offset
Yx Yx Yx, FBOUT Yx, FBOUT
t sk(o)
Figure 6. Output Skew
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
Yx, FBOUT Yx, FBOUT
t cycle n
Yx, FBOUT Yx, FBOUT
1 fO
t jit(per) = t cycle n
1 fO
(f O = input frequency measured at CLK, CLK)
Figure 7. Period Jitter
Yx, FBOUT Yx, FBOUT
t half period n
1 fO
t n+1 half period
t jit(hper) = t half period n
Figure 8. Half-Period Jitter
1 2*f O
80% Clock Inputs and Outputs 20%
80% V ID , V OD 20%
t r(i), t r(o)
t f(i), t f(o)
t slr(i/o) =
t r(i/o)
t slf(i/o) =
t f(i/o)
Figure 9. Input and Output Slew Rates
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PS8683B 10/17/03
2.90 NOM.
6.00 BSC
Pin #1 Corner
0 - 0.05 0.20 REF. 1.00 MAX. 2.90 NOM. Pin #1 Corner
13
PS8683B
0.40
10/17/03
0.10
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
Packaging Mechanical: 48-Pin TSSOP (A)
48
.236 .244
6.0 6.2
1
.488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE
.004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1
X.XX X.XX
DENOTES DIMENSIONS IN MILLIMETERS
.0197 BSC 0.50
.007 .010 0.17 0.27
.002 .006 0.05 0.15
Packaging Mechanical: 40-Contact TQFN (ZD)
6.00 BSC 0.50 BSC
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PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
Packaging Mechanical: 56-Ball VFBGA (NF)
Ordering Information
Orde ring Code PI6CVF857A PI6CVF857AE PI6CVF857ZDE PI6CVF857NF Package Code A AE ZDE NF Pin Count - Package Type 48- pin TSSOP Pb- free & Green, 48- pin TSSOP Pb- free & Green, 40- contact TQFN 56- ball, VFBGA
Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/
Pericom Semiconductor Corporation * 1-800-435-2336 * http://www.pericom.com
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PS8683B 10/17/03

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