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| Philips Semiconductors Product specification PowerMOS transistor PHD6N10E GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope suitable for surface mounting featuring high avalanche energy capability, stable blocking voltage, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. QUICK REFERENCE DATA SYMBOL VDS ID Ptot RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance MAX. 100 6.3 50 0.54 UNIT V A W PINNING - SOT428 PIN 1 2 3 tab gate drain source DESCRIPTION PIN CONFIGURATION tab SYMBOL d g 2 drain 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER ID IDM PD PD/Tmb VGS EAS IAS Tj, Tstg Continuous drain current Pulsed drain current Total dissipation Linear derating factor Gate-source voltage Single pulse avalanche energy Peak avalanche current Operating junction and storage temperature range CONDITIONS Tmb = 25 C; VGS = 10 V Tmb = 100 C; VGS = 10 V Tmb = 25 C Tmb = 25 C Tmb > 25 C VDD 50 V; starting Tj = 25C; RGS = 50 ; VGS = 10 V VDD 50 V; starting Tj = 25C; RGS = 50 ; VGS = 10 V MIN. - 55 MAX. 6.3 4.5 25 50 0.33 30 30 6.3 175 UNIT A A A W W/K V mJ A C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. pcb mounted, minimum footprint 50 MAX. 3 UNIT K/W K/W September 1997 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHD6N10E ELECTRICAL CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL V(BR)DSS V(BR)DSS / Tj RDS(ON) VGS(TO) gfs IDSS IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ls Ciss Coss Crss PARAMETER Drain-source breakdown voltage Drain-source breakdown voltage temperature coefficient Drain-source on resistance Gate threshold voltage Forward transconductance Drain-source leakage current Gate-source leakage current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA VGS = 10 V; ID = 3.4 A VDS = VGS; ID = 0.25 mA VDS = 50 V; ID = 3.4 A VDS = 100 V; VGS = 0 V VDS = 80 V; VGS = 0 V; Tj = 150 C VGS = 30 V; VDS = 0 V ID = 5.6 A; VDD = 80 V; VGS = 10 V MIN. 100 2.0 1.3 TYP. 0.15 0.25 3.0 3.0 0.1 1 10 9.2 1.7 4.7 7 40 22 18 3.5 7.5 222 74 30 MAX. 0.54 4.0 25 250 100 12 3 6 UNIT V V/K V S A A nA nC nC nC ns ns ns ns nH nH pF pF pF VDD = 50 V; ID = 5.6 A; RG = 24 ; RD = 8.4 Measured from tab to centre of die Measured from source lead solder point to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL IS ISM VSD trr Qrr PARAMETER Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tmb = 25C Tmb = 25C IS = 5.6 A; VGS = 0 V IS = 5.6 A; VGS = 0 V; dI/dt = 100 A/s MIN. TYP. 70 0.4 MAX. 6.3 25 1.5 UNIT A A V ns C September 1997 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHD6N10E 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating Zth j-mb, Transient Thermal Impedance (K/W) 10 1 0.5 0.2 0.1 0.05 0.1 0.02 0 P D tp t D= p T T t 0.1s 1s 10s 0 20 40 60 80 100 Tmb / C 120 140 160 180 0.01 1us 10us 100us 1ms 10ms tp, pulse widtht (s) Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) ID% Normalised Current Derating 12 10 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 120 110 100 90 80 70 60 50 40 30 20 10 0 ID, Drain current (Amps) 10 V Tj = 25 C PHP5N10 7V 6.5 V 8 6V 6 5.5 V 4 5V 2 0 VGS = 4.5 V 0 5 10 15 20 VDS, Drain-Source voltage (Volts) 25 30 0 20 40 60 80 100 Tmb / C 120 140 160 180 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS 100 ID, Drain current (Amps) PHP5N10E 0.8 0.7 RDS(on), Drain-Source on resistance (Ohms) 5V 5.5 V 6V 6.5 V PHP5N10 7V 10 RD O S( N )= VD S/ ID tp = 10 us 100 us 0.6 0.5 0.4 1 ms 1 DC 10 ms 100 ms 0.3 0.2 0.1 Tj = 25 C VGS = 10 V 0.1 1 10 100 VDS, Drain-source voltage (Volts) 1000 0 0 2 4 6 8 ID, Drain current (Amps) 10 12 Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS September 1997 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHD6N10E 8 7 6 ID, Drain current (Amps) VDS = 30 V PHP5N10E Tj = 25 C Tj = 175 C 4 VGS(TO) / V max. typ. 3 5 4 3 2 1 0 0 1 min. 2 0 2 4 6 VGS, Gate-source voltage (Volts) 8 10 -60 -20 20 60 Tj / C 100 140 180 Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj PHP5N10E Tj = 25 C Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS ID / A SUB-THRESHOLD CONDUCTION 4 gfs, Transconductance (S) VDD = 30 V 1E-01 1E-02 3 1E-03 2% typ 98 % Tj = 175 C 2 1E-04 1 1E-05 0 1E-06 0 2 4 6 ID, Drain current (Amps) 8 10 0 1 2 VGS / V 3 4 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj a Normalised RDS(ON) = f(Tj) Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1000 Ciss, Coss, Crss, Junction capacitances (pF) PHP5N10E Ciss Coss 100 Crss -60 -20 20 60 Tj / C 100 140 180 10 1 10 VDS, Drain-source voltage (Volts) 100 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 5.6 A; VGS = 5 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz September 1997 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHD6N10E 15 VGS, Gate-Source voltage (Volts) ID = 5.6 A Tj = 25 C VDS = 20 V 50 V PHP5N10E 80 V 20 IF, Source-drain diode current (Amps) VGS = 0 V PHP5N10E 15 10 10 5 5 Tj = 175 C Tj = 25 C 0 0 5 10 Qg, Gate charge (nC) 15 0 0 0.5 1 1.5 VSDS, Source-drain voltage (Volts) 2 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Switching times (ns) PHP5N10E Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj EAS, Normalised unclamped inductive energy (%) 100 tr td(off) tf 10 td(on) VDD = 50 V VGS = 10 V RD = 8.4 Ohms ID = 5.6 A Tj = 25 C 1 0 20 40 60 RG, Gate resistance (Ohms) 80 100 120 110 100 90 80 70 60 50 40 30 20 10 0 20 40 60 80 Starting Tj ( C) 100 120 140 160 180 Fig.14. Normalised drain-source breakdown voltage. V(BR)DSS/V(BR)DSS 25 C = f(Tj) Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C Fig.17. Normalised unclamped inductive energy. EAS% = f(Tj) 1.15 1.1 1.05 1 0.95 0.9 + L VDS VGS 0 RGS T.U.T. R 01 shunt VDD -ID/100 0.85 -100 -50 0 50 Tj, Junction temperature (C) 100 150 Fig.15. Normalised drain-source breakdown voltage. V(BR)DSS/V(BR)DSS 25 C = f(Tj) Fig.18. Unclamped inductive test circuit. 2 EAS = 0.5 LID V(BR)DSS /(V(BR)DSS - VDD ) September 1997 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHD6N10E MECHANICAL DATA Dimensions in mm : Net Mass: 1.4 g seating plane 6.73 max 1.1 2.38 max 0.93 max 5.4 tab 4 min 6.22 max 10.4 max 4.6 2 1 3 0.5 min 0.3 0.5 0.5 0.8 max (x2) 2.285 (x2) Fig.19. SOT428 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 7.0 7.0 2.15 2.5 1.5 4.57 Fig.20. SOT428 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". September 1997 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHD6N10E DEFINITIONS Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September 1997 7 Rev 1.000 |
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