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LOW POWER 3V CMOS SRAM 1 MEG (64K x 16-BIT)
Integrated Device Technology, Inc.
ADVANCE INFORMATION IDT71L016
FEATURES:
* * * * * * * 64K x 16 Organization Wide Operating Voltage Range: 2.7V to 3.6V Speed Grades: 70ns, 100ns Low Operating Power: 45mA (max) Low Standby Power: 5A (max) Low-Voltage Data Retention: 1.5V (min) Available in a 44-pin TSOP package
DESCRIPTION:
The IDT71L016 is a 1,048,576-bit very low-power Static RAM organized as 64K x 16. It is fabricated using IDT's highreliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for low-power memory needs. It uses a 6-transistor memory cell. All input and output signals of the IDT71L016 are LVTTLcompatible and operation is from a single extended-range 3.3V supply. This extended supply range makes the device ideally suited for unregulated battery-powered applications. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71L016 is packaged in a JEDEC standard 44-pin TSOP Type II.
FUNCTIONAL BLOCK DIAGRAM
OE
Output Enable Buffer
A0 - A15
Address Buffers
Row / Column Decoders
I/O 15 Chip Enable Buffer 8 High Byte I/O Buffer 8
CS
I/O 8
WE
Write Enable Buffer
64K x 16 Memory Array
16
Sense Amps and Write Drivers I/O 7 8 Low Byte I/O Buffer 8
I/O 0
BHE
Byte Enable Buffers
BLE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
(c)1997 Integrated Device Technology, Inc.
MAY 1997
DSC-3771/2
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IDT71L016 LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A4 A3 A2 A1 A0
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SO44-2
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7
OE BHE BLE
I/O 0 I/O 1 I/O 2 I/O 3 VDD VSS I/O 4 I/O 5 I/O 6 I/O 7
WE
I/O 15 I/O 14 I/O 13 I/O 12 VSS VDD I/O 11 I/O 10 I/O 9 I/O 8 NC A8 A9 A10 A11 NC
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CAPACITANCE
(TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 6 7 Unit pF pF
A15 A14 A13 A12 NC
NOTE: 3771 tbl 06 1. This parameter is guaranteed by device characterization, but not production tested.
TSOP TOP VIEW
PIN DESCRIPTIONS
A0 - A15
CS WE OE BHE BLE
Address Inputs Chip Select Write Enable Output Enable High Byte Enable Low Byte Enable Data Input/Output Power Ground
Input Input Input Input Input Input I/O Pwr Gnd
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I/O0 - I/O15 VDD VSS
TRUTH TABLE(1)
CS OE WE BLE BHE
I/O0-I/O7 High-Z DATAOUT High-Z DATAOUT DATAIN DATAIN High-Z High-Z High-Z
I/O8-I/O15 High-Z High-Z DATAOUT DATAOUT DATAIN High-Z DATAIN High-Z High-Z
Function Deselected - Standby Low Byte Read High Byte Read Word Read Word Write Low Byte Write High Byte Write Outputs Disabled Outputs Disabled
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H L L L L L L L L
X L L L X X X H X
X H H H L L L H X
X L H L L L H X H
X H L L L H L X H
NOTE: 1.H = VIH, L = VIL, X = Don't care.
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IDT71L016 LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) TBIAS TSTG PT IOUT Rating Terminal Voltage with Respect to VSS Terminal Voltage with Respect to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Com'l. and Ind'l. -0.5 to +4.6 -0.5 to VDD+0.5V -55 to +125 -55 to +125 1.0 20 Unit V V C C W mA
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Industrial Temperature 0C to +70C -40C to +85C VSS 0V 0V VDD 2.7V to 3.6V 2.7V to 3.6V
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RECOMMENDED DC OPERATING CONDITIONS
Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.0 -0.3
(2)
NOTES: 3771 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. Input, Output,and I/O terminals; 4.6V maximum.
Typ. 3.0 0 -- --
Max. 3.6 0
VDD+0.3(1)
Unit V V V V
0.8
NOTE: 3771 tbl 05 1. VIH (max.) = VDD + 1.5V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = -1.5V for pulse width less than 5ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 3.6V, Commercial and Industrial Temperature Ranges
Symbol |ILI| |ILO| VOH VOL Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Test Conditions VDD = Max., VIN = VSS to VDD VDD = Max., CS = VIH, VOUT = VSS to VDD IOH = -1mA, VDD = Min. IOL = 2mA, VDD = Min. Min. -- -- 2.4 -- Max. 1 1 -- 0.4 Unit A A V V
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DC ELECTRICAL CHARACTERISTICS(1, 2)
VDD = 2.7 to 3.6V, VLC = 0.2V, VHC = VDD-0.2V, Commercial and Industrial Temperature Ranges
Symbol ICC2 Parameter Dynamic Operating Current
CS
Test Conditions = VLC, Outputs Open, -70 ns -100 ns VDD = 3.6V, f = fMAX(3)
Typ.(5) -- -- -- -40 to 85C 0 to 70C 40C 25C -- -- -- --
Max. 45 35 10 10 5 2 1
Unit mA
ICC ISB1
Static Operating Current Standby Supply Current
CS WE CS
= VLC, Outputs Open, = VHC, VDD = 3.6V, f = 0(4) = VHC, Outputs Open,
mA A
VDD = 3.6V
NOTES: 1. All values are maximum guaranteed values. 2. Input low and high voltage levels are 0.2V and VDD-0.2V respectively for all tests. 3. fMAX = 1/tRC (all address inputs are cycling at fMAX). 4. f = 0 means no address input lines are changing . 5. Typical conditions are VDD = 3.0V and specified temperature.
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IDT71L016 LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(VLC = 0.2V, VHC = VDD - 0.2V)
Symbol VDR ICCDR tCDR(3) tR(3) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
CS
Test Condition -- VHC
Min. 1.5 -- 0 tRC(2)
Typ. (1) -- <1 -- --
Max. -- 5 -- --
Unit V A ns ns
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NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested.
LOW VDD DATA RETENTION WAVEFORM
DATA RETENTION MODE V DD tCDR
CS
2.7V V DR 1.5V V IH
2.7V tR V IH
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V DR
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 2.5V 3ns 1.5V 1.5V See Figure 1
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AC TEST LOAD
VDD 3070 DATAOUT 50pF* 3150
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*Including jig and scope capacitance.
Figure 1. AC Test Load
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IDT71L016 LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VDD = 2.7 to 3.6V, All Temperature Ranges)
71L016L70 Symbol Read Cycle tRC tAA tACS tCLZ(1) tCHZ tOE tOLZ(1) tOHZ tOH tBE tBLZ
(1) (1) (1)
71L016L100 Min. 100 -- -- 10 -- -- 5 -- 15 -- 5 -- 100 80 80 80 0 0 70 40 0 5 -- Max. -- 100 100 -- 30 50 -- 30 -- 50 -- 30 -- -- -- -- -- -- -- -- -- -- 30 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Select Low to Output in Low-Z Chip Select High to Output in High-Z Output Enable Low to Output Valid Output Enable Low to Output in Low-Z Output Enable High to Output in High-Z Output Hold from Address Change Byte Enable Low to Output Valid Byte Enable Low to Output in Low-Z Byte Enable High to Output in High-Z Write Cycle Time Address Valid to End of Write Chip Select Low to End of Write Byte Enable Low to End of Write Address Set-up Time Address Hold from End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Enable High to Output in Low-Z Write Enable Low to Output in High-Z
Min. 70 -- -- 10 -- -- 5 -- 10 -- 5 -- 70 65 65 65 0 0 55 30 0 5 --
Max. -- 70 70 -- 25 35 -- 25 -- 35 -- 25 -- -- -- -- -- -- -- -- -- -- 25
tBHZ(1) Write Cycle tWC tAW tCW tBW tAS tWR tWP tDW tDH tOW(1) tWHZ(1)
NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1(1,2,3)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
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NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW.
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IDT71L016 LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1)
tRC ADDRESS tAA
OE
tOH
tOE tOLZ
CS
tOHZ
(3)
(3)
tCLZ (3)
BHE, BLE
tACS (2)
tCHZ
(3)
tBE (2) tBLZ DATAOUT
(3)
tBHZ DATA OUT VALID
(3)
NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured 200mV from steady state.
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TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1,2,3,5) WE
tWC ADDRESS tAW
CS
tCW
BHE
(3)
tCHZ
(6)
tBW
,
BLE
tWP
WE
tWR
tBHZ
(6)
tAS DATAOUT PREVIOUS DATA VALID
(4)
tWHZ
(6)
tOW
(6)
DATA VALID tDW tDH
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DATAIN
DATAIN VALID
NOTES: 1. WE or (BHE and BLE) or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state.
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IDT71L016 LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1,2,5) CS
tWC ADDRESS tAW
CS
tAS tBW
BHE
tCW (3)
,
BLE
tWP
WE
tWR
DATAOUT tDW DATAIN DATAIN VALID
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tDH
TIMING WAVEFORM OF WRITE CYCLE NO. 3 (BHE BLE CONTROLLED TIMING)(1,2,5) BHE,
tWC ADDRESS tAW
CS
tCW tAS
BHE , BLE
(3)
tBW
tWP
WE
tWR
DATAOUT tDW DATAIN DATAIN VALID
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tDH
NOTES: 1. WE or (BHE and BLE) or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state.
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IDT71L016 LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT 71L016 Device Type L Power XXX Speed XX Package X Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C)
PH
400-mil TSOP Type II (SO44-2)
70 100
Speed in nanoseconds
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