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| SI9912 Vishay Siliconix Half-Bridge MOSFET Driver for Switching Power Supplies FEATURES D D D D D D D D D D 4.5- to 5.5-V Operation Undervoltage Lockout 250-kHz to 1-MHz Switching Frequency Shutdown Quiescent Current <5 mA One Input PWM Signal Generates Both Drive Bootstrapped High-Side Drive Operates from 4.5- to 30-V Supply TTL/CMOS Compatible Input Levels 1-A Peak Drive Current Break-Before-Make Circuit APPLICATIONS D D D D D Multiphase Desktop CPU Supplies Single-Supply Synchronous Buck Converters Mobile Computing CPU Core Power Converters Standard-Synchronous Converters High Frequency Switching Converters DESCRIPTION The SI9912 is a dual MOSFET high-speed driver with break-before-make. It is designed to operate in high frequency dc-dc switchmode power supplies. The high-side driver is bootstrapped to handle the high voltage slew rate associated with "floating" high-side gate drivers. Each driver is capable of switching a 3000-pF load with 60-ns propogation delay and 25-ns transition time. The SI9912 comes with an internal break-before-make feature to prevent shoot-through current in the external MOSFETs. A shutdown pin is used to enable the driver. When disabled, the quiescent current of the driver is less than 5 mA. The SI9912 is available in both standard and lead (Pb)-free, 8-pin SOIC packages for operation over the industrial operation range (-40_C to 85_C). FUNCTIONAL BLOCK DIAGRAM AND TRUTH TABLE VDD D1 BOOT VDC Q1 OUTH CBOOT TRUTH TABLE VS SD IN L H L H L H L H Level Shift Undervoltage VOUTL L L H L L L L L VOUTH L L L H L L L H VS VDD OUTL Q2 OUTPUT L L L L H H H H L L H H L L H H SD IN + - VBBM GND Document Number: 71311 S-40134--Rev. B, 16-Feb-04 www.vishay.com 1 SI9912 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED) Parameter Low Side Driver Supply Voltage Input Voltage on IN Shutdown Pin Voltage Bootstrap Voltage High Side Driver (Bootstrap) Supply Voltage Operating Junction Temperature Range Storage Temperature Range Power Dissipation (Note a and b) Thermal Impedance Lead Temperature (soldering 10 Sec) Notes a. Device mounted with all leads soldered to P.C. Board b. Derate 8.3 W/_C above 25_C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol VDD VIN VSD VBOOT VBOOT - VS TJ Tstg PD qJA Limit 7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 35.0 7.0 -40 to 125 -40 to 150 830 125 300 Unit V _C mW C/W C RECOMMENDED OPERATING CONDITIONS Parameter Bootstrap Voltage (High-Side Drain Voltage) Logic Supply Bootstrap Capacitor Ambient Temperature Symbol VBOOT VDD CBOOT TA Limit 4.5 to 30 4.5 to 5.5 100 n to 1 m -40 to 85 Unit V F _C SPECIFICATIONS Test Conditions Unless Specified Parameter Power Supplies VDD Supply IDD Supply IDD Supply IDD Supply IDD Supply IDD Supply IDD Supply Boot Strap Current VDD IDD1(en) IDD2(en) IDD3(dis) IDD4(en) IDD5(dis) IDD(en) IDD(dis) IBOOT SD = H, IN = H, VS = 0 V SD = H, IN = L, VS = 0 V SD = L, IN = X, VS = 0 V SD = H, IN = X, VS = 25 V, VBOOT = 30 V SD = L, IN = X, VS = 25 V, VBOOT = 30 V FIN = 300 kHz, SD = High, Driving Si4412DY FIN = 300 kHz, SD = Low, Driving Si4412DY VBOOT = 30 V, VS = 25 V, VOUTH = High 0.9 9 3 3 4.5 1000 500 5 200 5 mA mA mA mA Limits Mina Typb Maxa Unit Symbol VDD = 4.5 to 5.5 V VBOOT = 4.5 to 30 V, TA = -40 to 85_C Reference Voltage Break-Before-Make Reference Voltage VBBM 1.1 3 V Logic Inputs (SD, IN) Input High Input Low VIH VIL 0.7 VDD -0.3 VDD + 0.3 0.3 VDD V Undervoltage Lockout VDD Undervoltage VDD Undervoltage Hysteresis www.vishay.com VUVL VHYST VDD Rising 3.7 0.4 4.3 V 2 Document Number: 71311 S-40134--Rev. B, 16-Feb-04 SI9912 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Specified Parameter Bootstrap Diode Diode Forward Voltage VFD1 Forward Current = 100 mA 0.8 1 V Limits Mina Typb Maxa Unit Symbol VDD = 4.5 to 5.5 V VBOOT = 4.5 to 30 V, TA = -40 to 85_C Output Drive Current OUTH Source Current OUTH Sink Current OUTL Source Current OUTL Sink Current IOUT(H+) IOUT(H-) IOUT(L+) IOUT(L-) VBOOT - VS = 3.7 V, VOUTH - VS = 2 V VBOOT - VS = 3.7 V, VOUTH - VS = 1 V VDD = 4.5 V, VOUTL = 2 V VDD = 4.5 V, VOUTL = 1 V 0.6 0.4 -0.4 -0.4 A Timing (CLOAD = 3 nF) OUTL Off Propagation Delay OUTL On Propagation Delay OUTH Off Propagation Delay OUTH On Propagation Delay OUTL Turn On Time OUTL Turn Off Time OUTH Turn On Time OUTH Turn Off Time tpdl(OUTL) tpdh(OUTL) tpdl(OUTH) tpdh(OUTH) tr(OUTL) tf(OUTL) tr(OUTH) tf(OUTH) VDD = 4.5 V 45 30 20 30 20 25 25 30 20 ns VBOOT - VS = 4 5 V 4.5 OUTL = 10 to 90% OUTL = 90 to 10% OUTH - VS = 10 to 90% OUTH - VS = 90 to 10% Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. TIMING WAVEFORMS IN 50% 50% tpdh(OUTL) 90% OUTL 10% tpdl(OUTH) tf(OUTL) 90% 10% tr(OUTL) tpdl(OUTL) OUTH tpdh(OUTH) tr(OUTH) 90% 10% 90% 10% tf(OUTH) VS Document Number: 71311 S-40134--Rev. B, 16-Feb-04 www.vishay.com 3 SI9912 Vishay Siliconix PIN CONFIGURATION SO-8 OUTH GND IN SD 1 2 3 4 Top View 8 7 6 5 VS BOOT VDD OUTL PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 Name OUTH GND IN SD OUTL VDD BOOT VS Output drive for upper MOSFET. Ground supply CMOS level input signal. Controls both output drives. Shutdown pin Output drive for lower MOSFET. Input power supply Floating bootstrap supply for the upper MOSFET Function Floating GND for the upper MOSFET. VS is connected to the buck switching node and the source side of the upper MOSFET. ORDERING INFORMATION Part Number SI9912DY SI9912DY-T1 SI9912DY-T1--E3 (Lead (Pb)-Free) -40 to 85_C Temperature Range Package Bulk Tape and Reel Eval Kit SI9912DB Temperature Range -40 to 85_C Board Type Surface Mount TYPICAL WAVEFORMS Driver On Switch Delay VS CL = Si4412DY VS Driver Off Switch Delay CL = Si4412DY OUTH OUTH See Figure 1 OUTL OUTL See Figure 1 IN SI9912 tr, tf, tpd www.vishay.com IN SI9912 tr, tf, tpd Document Number: 71311 S-40134--Rev. B, 16-Feb-04 4 SI9912 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) IDD Supply Current vs. Frequency 30 50 See Figure 2 See Figure 1 10 Current (mA) Rise and Fall times (ns) 40 tr(OUTH) tf(OUTL) tf(OUTH) tr(OUTL) Rise and Fall Time vs. CLOAD 30 20 10 1 1 10 100 1000 Frequency (kHz) 0 0.3 1 3 10 Load Capacitance (nF) VOUT(H+) vs. Supply 0 0.5 A -1 Output Voltage Drop (V) Output Voltage Drop (V) 4 5 VOUT(H-) vs. Supply See Figure 3 2A 3 1.5 A 2 1A 1 0.5 A -2 1A -3 1.5 A -4 See Figure 3 -5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Supply Voltage (V) Supply Voltage (V) VOUT(L+) vs. Supply 0 -1 Output Voltage Drop (V) -2 -3 -4 2A -5 -6 4.0 See Figure 3 1.5 A 0.5 A 2.5 VOUT(L-) vs. Supply See Figure 3 2.0 Output Voltage Drop (V) 1A 1.5 2A 1.5 A 1.0 1A 0.5 0.5 A 4.5 5.0 Supply Voltage (V) 5.5 6.0 0.0 4.0 4.5 5.0 Supply Voltage (V) 5.5 6.0 Document Number: 71311 S-40134--Rev. B, 16-Feb-04 www.vishay.com 5 SI9912 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) VOUT(H+) vs. Temperature 0 5 See Figure 3 -1 Output Voltage Drop (V) 0.5 A Output Voltage Drop (V) 4 VOUT(H-) vs. Temperature -2 1A 3 2A 2 1.5 A 1A 1 0.5 A -3 See Figure 3 -4 -5 -50 -25 0 25 50 75 100 0 -50 -25 0 25 50 75 100 Temperature (_C) Temperature (_C) 0 VOUT(L+) vs. Temperature 2.0 0.5 A VOUT(L-) vs. Temperature See Figure 3 1.5 -1 Output Voltage Drop (V) Output Voltage Drop (V) 1A 2A -2 1.5 A 1.0 1.5 A 1A -3 -4 2A -5 -50 See Figure 3 0.5 0.5 A -25 0 25 50 75 100 0.0 -50 -25 0 25 50 75 100 Temperature (_C) Temperature (_C) THEORY OF OPERATION Break-Before-Make Function The SI9912 has an internal break-before-make function to ensure that both high-side and low-side MOSFETs are not turned on at the same time. The high-side drive (OUTH) will not turn on until the low-side gate drive voltage (measured at the OUTL pin) is less than VBBM, thus ensuring that the low-side MOSFET is turned off. The low-side drive (OUTL) will not turn on until the voltage at the MOSFET half-bridge output (measured at the VS pin) is less than VBBM, thus ensuring that the high-side MOSFET is turned off. www.vishay.com Under Voltage Lockout Function The SI9912 has an internal under-voltage lockout feature to prevent driving the MOSFET gates when the supply voltage (at VDD) is less than the under-voltage lockout specification (VUVL). This prevents the output MOSFETs from being turned on without sufficient gate voltage to ensure they are fully on. There is hysteresis included in this feature to prevent lockout from cycling on and off. 6 Document Number: 71311 S-40134--Rev. B, 16-Feb-04 SI9912 Vishay Siliconix Bootstrap Supply Operation (see Functional Block Diagram) The power to drive the high-side MOSFET (Q2) gate comes from the bootstrap capacitor (CBOOT). This capacitor charges through D1 during the time when the low-side MOSFET is on (VS is at GND potential), and then provides the necessary charge to turn on the high-side MOSFET. CBOOT should be sized to be greater than ten times the high-side MOSFET gate capacitance, and large enough to supply the bootstrap current (IBOOT) during the high-side on time, without significant voltage droop. Shutdown (SD) (shutdown input, active low) When this pin is high, the IC operates normally. When this pin is low, both high- and low-side MOSFETs are turned off . Layout Considerations There are a few critical layout considerations for these parts. Firstly, the IC must be decoupled as closely as possible to the power pins. Secondly the IC should be placed physically close to the high- and low-side MOSFETs it is driving. The major consideration is that the MOSFET gates must be charged or discharged in a few nanoseconds, and the peak current to do this is of the order of 1 A. This current must flow from the decoupling and bootstrap capacitors to the IC, and from the output driver pin to the MOSFET gate, returning from the MOSFET source to the IC. The aim of the layout is to reduce the parasitic inductance of these current paths as much as possible. This is accomplished by making these traces as short as possible, and also running trace and its current return path adjacent to each other. APPLICATIONS +VDC 5 6 7 8 4 U1 1 2 PWM IN 3 4 OUTH GND IN SD VS BOOT VDD OUTL 8 7 6 5 4 C2 0.1 mF C1 0.1 mF +5 V Q1 0.1 mF C3 15 mF C4 + Si4412 L1 15 mH 5 6 7 8 1 2 3 GND 1 mF C5 RLOAD Enable Q2 SI9912 Si4412 GND FIGURE 1. Typical Applications Schematic Circuit Used to Obtain Typical Rising and Falling Switching Waveforms Document Number: 71311 S-40134--Rev. B, 16-Feb-04 1 2 3 GND www.vishay.com 7 SI9912 Vishay Siliconix +5 V +5 V U1 1 2 PWM IN 3 4 OUTH GND IN SD VS BOOT VDD OUTL 8 7 6 5 CLOAD C8 C2 0.1 mF CLOAD C9 1 2 Input 3 4 OUTH GND IN SD U1 VS BOOT VDD OUTL 8 7 6 5 ISRC C2 0.1 mF ISRC SI9912 SI9912 GND GND FIGURE 2. Capacitive Load Test Circuit Used to Measure Rise and Fall Times vs. Capacitance FIGURE 3. Load Test Schematic Circuit Used to Measure Driver Output Impedance www.vishay.com 8 Document Number: 71311 S-40134--Rev. B, 16-Feb-04 |
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