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HM62W8127H Series HM62W9127H Series
131072-word x 8/9-bit High Speed CMOS Static RAM
Description
The HM62W8127H/HM62W9127H is an asynchronous 3.3 V operation high speed static RAM organized as 131,072-word x 8/9-bit. It realize high speed access time (30/35/45 ns) with employing 0.8 m CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W8127H/HM62W9127H is packaged in 400-mil 32/36-pin SOJ for high density surface mounting.
Features
* Single 3.3 V supply: 3.3 V 0.3 V * Access time 30/35/45 ns (max) * Completely static memory No clock or timing strobe required * Equal access and cycle times * Directly CMOS compatible All inputs and outputs * 400-mil 32/36-pin SOJ package * Center VCC and VSS type pinout
HM62W8127H/HM62W9127H Series
Ordering Information
Type No. HM62W8127HJP-30 HM62W8127HJP-35 HM62W8127HJP-45 HM62W8127HLJP-30 HM62W8127HLJP-35 HM62W8127HLJP-45 HM62W9127HJP-30 HM62W9127HJP-35 HM62W9127HJP-45 HM62W9127HLJP-30 HM62W9127HLJP-35 HM62W9127HLJP-45 Access Time 30 ns 35 ns 45 ns 30 ns 35 ns 45 ns 30 ns 35 ns 45 ns 30 ns 35 ns 45 ns 400-mil 36-pin plastic SOJ (CP-36D) Package 400-mil 32-pin plastic SOJ (CP-32DB)
2
HM62W8127H/HM62W9127H Series
Pin Arrangement
HM62W8127H Series A3 A2 A1 A0 CS I/O1 I/O2 VCC VSS I/O3 I/O4 WE A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A4 A5 A6 A7 OE I/O8 I/O7 VSS VCC I/O6 I/O5 A8 A9 A10 A11 A12 NC A3 A2 A1 A0 CS I/O1 I/O2 VCC VSS I/O3 I/O4 WE A16 A15 A14 A13 NC HM62W9127H Series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A4 A5 A6 A7 OE I/O9 I/O8 I/O7 VSS VCC I/O6 I/O5 A8 A9 A10 A11 A12 NC
Pin Description
Pin Name HM62W8127H A0 - A16 I/O1 - I/O8 CS WE OE VCC VSS -- HM62W9127H A0 - A16 I/O1 - I/O9 CS WE OE VCC VSS NC Function Address Data input/output Chip select Write enable Output enable Power supply Ground No connection
3
HM62W8127H/HM62W9127H Series
Block Diagram
A4 A3 A2 A1 A0 A7 A6 A5
VCC Row Decoder Memory Matrix 256 rows x 512 x 8/9 columns VSS
CS I/O1 . . . I/O8/9 Column I/O Input Data Control Column Decoder CS
A13 A12 A11 A16 A15 A14 A10 A9 A8 WE CS
OE CS
Absolute Maximum Ratings
Parameter Supply voltage relative to VSS Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Note: Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +4.6 -0.5 1.0 0 to +70 -55 to +125 -10 to +85
*1
Unit V V W C C C
to V CC + 0.5
1. -2.5 V for pulse width (under shoot) 10 ns
4
HM62W8127H/HM62W9127H Series
Function Table
CS H L L L OE X H L X WE X H H L VCC Current I SB , I SB1 I CC I CC I CC I/O High-Z High-Z Output Input Ref. Cycle Read cycle Write cycle
Note: X: H or L
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage
*2
Symbol VCC VSS
Min 3.0 0 2.0 -0.3
*1
Typ 3.3 0 -- --
Max 3.6 0 VCC + 0.3 0.8
Unit V V V V
Input voltage
VIH VIL
Notes: 1. -2.0 V for pulse width (under shoot) 10 ns 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
5
HM62W8127H/HM62W9127H Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)
Parameter Input leakage current Output leakage current Symbol Min |ILI| |ILO | -- -- -- -- -- Standby power supply current I SB -- -- -- Standby power supply current (1) I SB1 -- Typ*1 Max Unit Test Conditions -- -- 50 45 40 18 15 13 -- 2 2 90 85 80 35 30 25 1 A A Vin = VSS to V CC VI/O = VSS to V CC Note
Operating power supply I CC current
mA 30 ns cycle CS = VIL, Iout = 0 mA Other inputs = VIH/V IL mA 35 ns cycle mA 45 ns cycle mA 30 ns cycle CS = VIH, Other inputs = VIH/V IL mA 35 ns cycle mA 45 ns cycle mA VCC CS V CC - 0.2 V, 0 V Vin 0.2 V or VCC Vin V CC - 0.2 V L-version I OL1 = 0.1 mA I OL2 = 2 mA I OH1 = -0.1 mA I OH2 = -2 mA
-- Output voltage VOL1 VOL2 VOH1 VOH2 Note: -- --
-- -- --
0.15 mA 0.2 0.4 -- -- V V V V
VCC - 0.2 -- 2.4 --
1. Typical values are at VCC = 3.3 V, Ta = +25C and not guaranteed.
Capacitance (Ta = 25C, f = 1.0 MHz)*1
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min -- -- Typ -- -- Max 6 8 Unit pF pF Test Conditions Vin = 0 V VI/O = 0 V
1. This parameter is sampled and not 100% tested.
6
HM62W8127H/HM62W9127H Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, unless otherwise noted.)
Test Conditions * * * * Input pulse levels: 2.4 V/0.4 V Input rise and fall time: 3 ns Input and output timing reference level: 1.4 V Output load: See figures
Dout 500 30 pF*1 1.4 V Output load (A) Note: 1. Including scope and jig 5 pF*1 1.4 V Output load (B) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW)
Dout 500
Read Cycle
HM62W8127H/HM62W9127H -30 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Note: Symbol Min t RC t AA t ACS t OE t OH t CLZ t OLZ t CHZ t OHZ 30 -- -- -- 5 5 1 -- -- Max -- 30 30 15 -- -- -- 12 12 -35 Min 35 -- -- -- 5 5 1 -- -- Max -- 35 35 20 -- -- -- 12 12 -45 Min 45 -- -- -- 5 5 1 -- -- Max -- 45 45 25 -- -- -- 12 12 Unit ns ns ns ns ns ns ns ns ns 1 1 1 1 Note
1. Transition is measured 200 mV from steady voltage with Load (B). This parameter is sampled and not 100% tested.
7
HM62W8127H/HM62W9127H Series
Read Timing Waveform (WE = VIH)
t RC
Address
Valid address t AA t ACS t OH t CHZ
CS t OE OE t OLZ t CLZ Dout High Impedance
*1
t OHZ
Valid data
Note: 1. When CS and OE are low, Dout is low impedance.
8
HM62W8127H/HM62W9127H Series
Write Cycle*1
HM62W8127H/HM62W9127H -30 Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Write disable to output in low-Z Write enable to output in high-Z Notes: 1. 2. 3. 4. Symbol Min t WC t AW t CW t WP t AS t WR t DW t DH t OW t WHZ 30 20 20 20 0 0 15 0 5 -- Max -- -- -- -- -- -- -- -- -- 12 -35 Min 35 25 25 25 0 0 20 0 5 -- Max -- -- -- -- -- -- -- -- -- 12 -45 Min 45 30 30 30 0 0 25 0 5 -- Max -- -- -- -- -- -- -- -- -- 12 Unit Notes ns ns ns ns ns ns ns ns ns ns 4 4 2 3
A write occurs during the overlap of low CS, low WE. t AS is measured from the latest address transition to the later of CS or WE going low. t WR is measured from the earliest of CS or WE going high to the first address transition. Transition is measured 200 mV from high impedance state's voltage with Load (B). This parameter is sampled and not 100% tested.
9
HM62W8127H/HM62W9127H Series
Write Timing Waveform (1) (WE Controlled)
t WC Address Valid address t AW t AS WE
*1
t WR t WP
t CW CS t WHZ Dout t DW Din
*2
t OW
t DH
*2
Valid data
Notes: 1. WE must be high during address transition except when the device is disabled with CS. 2. If CS and OE are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them.
10
HM62W8127H/HM62W9127H Series
Write Timing Waveform (2) (CS Controlled)
t WC Address Valid address t AW t WP WE t CW CS t AS t DW
*1
t WR
t DH
Din
Valid data
Note: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state.
11
HM62W8127H/HM62W9127H Series
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
This characteristics is guaranteed only for L-version.
Parameter VCC for data retention Symbol VDR Min 2.0 Typ -- Max -- Unit V Test Conditions VCC CS VCC - 0.2 V, VCC Vin VCC - 0.2 V or 0 V Vin 0.2 V
Data retention current Chip deselect to data retention time
I CCDR t CDR
-- 0 5
2 -- --
80*1 -- --
A ns ms
Operation recovery time t R Note: 1. VCC = 3.0 V
Low V CC Data Retention Timing Waveform
t CDR V CC 4.5 V Data retention mode tR
2.2 V V DR CS 0V VCC > CS > VCC - 0.2 V
12
HM62W8127H/HM62W9127H Series
Package Dimensions
HM62W8127HJP/HLJP Series (CP-32DB)
20.71 21.08 Max Unit: mm
32
17 10.16 0.13 11.18 0.13
1
3.50 0.26
1.3 Max
0.43 0.10
1.27 0.10
0.80
9.40 0.25
HM62W9127HJP/HLJP Series (CP-36D)
23.25 23.62 Max 36 19 10.16 0.13
2.85 0.12
0.74
16
+0.25 -0.17
Unit: mm
1
3.50 0.26
0.74
18
2.85 0.12
1.30 Max
0.43 0.10
1.27 0.10
0.80
+0.25 -0.17
11.18 0.13
9.40 0.25
13

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