View MB81P643287_325537.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11402-2E
MEMORY
CMOS
8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM
MB81P643287-50/-60
CMOS 8-BANK x 262,144-WORD x 32 BIT, FCRAM Core Based Synchronous Dynamic Random Access Memory with Double Data Rate
s DESCRIPTION
The Fujitsu MB81P643287 is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) with Fujitsu advanced FCRAM (Fast Cycle Random Access Memory) Core Technology, containing 67,108,864 memory cells accessible in an 32-bit format. The MB81P643287 features a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB81P643287 is designed to reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timin.g constraints. The MB81P643287 uses Double Data Rate (DDR) where data bandwidth is twice of fast speed compared with regular SDRAMs. The MB81P643287 is ideally suited for Digital Visual Systems, High Performance Graphic Adapters, Hardware Accelerators, Buffers, and other applications where large memory density and high effective bandwidth are required and where a simple interface is needed. The MB81P643287 adopts new I/O interface circuitry, SSTL_2 interface, which is capable of extremely fast data transfer of quality under either terminated or point to point bus environment.
s PRODUCT LINE
Parameter Clock Frequency Burst Mode Cycle Time Random Address Cycle Time DQS Access Time From Clock Operating Current Power Down Current Note: FCRAM is a trademark of Fujitsu Limited, Japan. CL = 3 CL = 2 CL = 3 CL = 2 MB81P643287 -50 200 MHz Max. 133 MHz Max. 2.5 ns Min. 3.75 ns Min. 30 ns Min. 0.1 x tCK + 0.2 ns Max. 460 mA Max. 35 mA Max. -60 167 MHz Max. 111 MHz Max. 3.0 ns Min. 4.5 ns Min. 36 ns Min. 0.1 x tCK + 0.2 ns Max. 405 mA Max.
MB81P643287-50/-60
s FEATURES
* * * * * * * Double Data Rate Bi-directional Data Strobe Signal Eight bank operation Burst read/write operation Programmable burst length and CAS latency Byte write control by DM0 to DM3 Standby Power Down Mode * * * * 4096 Auto-refresh cycles in 32 ms SSTL_2 (class 2) for all signals +2.5V Supply 0.2V tolerance VDD: VDDQ: +2.5V Supply 0.2V tolerance
s PACKAGE
86-pin plastic TSOP(II)
(FPT-86P-M01) (Normal Bend)
2
MB81P643287-50/-60
s PIN ASSIGNMENTS
86-pin TSOP (II) (TOP VIEW) (Normal Bend)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 DQS0 VDD DM0 WE CAS RAS CS BA2 BA0 BA1 A10/AP A0 A1 A2 DM2 VDD DQS2 DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 DQS1 VSS DM1 VREF CLK CLK CKE A9 A8 A7 A6 A5 A4 A3 DM3 VSS DQS3 DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
(FPT-86P-M01)
3
MB81P643287-50/-60
s DESCRIPTIONS
Pin Number 1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81 6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 Symbol VDD, VDDQ VSS, VSSQ Supply Voltage Ground * * * * * * * * Byte 0: DQ0 to DQ7 Byte 1: DQ8 to DQ15 Byte 2: DQ16 to DQ23 Byte 3: DQ24 to DQ31 DQS0: for DQ0 to DQ7 DQS1: for DQ8 to DQ15 DQS2: for DQ16 to DQ23 DQS3: for DQ24 to DQ31 Function
DQ0 to DQ31
Data I/O
14, 30, 57, 73
DQS0 to DQS3
Data Strobe
16, 28, 59, 71 17 18 19 20 21, 22, 23 24 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 67 68 69 70
DM0 to DM3 WE CAS RAS CS BA2, BA1, BA0 AP A0 to A10 CKE CLK CLK VREF
Input Mask Write Enable Column Address Strobe Row Address Strobe Chip Select Bank Select (Bank Address) Auto Precharge Enable Address Input Power Down Clock Input Clock Input Input Reference Voltage * Row: A0 to A10 * Column: A0 to A6
4
MB81P643287-50/-60
s BLOCK DIAGRAM
Fig. 1 - MB81P643287 BLOCK DIAGRAM
CLK CLK CKE Bank-7 CLOCK BUFFER To each block
Enable RAS CS RAS COMMAND DECODER CONTROL SIGNAL LATCH CAS
Bank-1 Bank-0
CAS WE AP
WE
MODE REGISTER
DRAM CORE (2048 x 128 x 32)
11 A0 to A10 BA0, BA1, BA2 ADDRESS BUFFER/ REGISTER
ROW ADDRESS
DM0 to DM3 DQ0 to DQ31 DQS0 to DQS3 I/O DATA BUFFER/ REGISTER & DQS GENERATOR DLL
COLUMN ADDRESS COUNTER
7
COLUMN ADDRESS I/O
32 VDD Clock Buffer VREF VSS/VSSQ
VDDQ, VSSQ
5
MB81P643287-50/-60
s FUNCTION TRUTH TABLE (Note*1)
COMMAND TRUTH TABLE (Note *2, and *3) Function Notes Symbol CKE Device Deselect No Operation Burst Stop Read Read with Auto-precharge Write Write with Auto-precharge Bank Active (RAS) Precharge Single Bank Precharge All Banks *4 *4 *5 *6 *6 *7 *8 *8 DESL NOP BST READ WRIT ACTV PRE PALL MRS/ EMRS H H H H H H H H H H H CS H L L L L L L L L L L RAS X H H H H H H L L L L CAS X H H L L L L H H H L WE X H L H H L L H L L L BA2-0 X X X V V V V V V V V A10/AP X X X L H L H V L H L A9-7 X X X X X X X V X X V A6-0 X X X V V V V V X X V
*6 READA *6 WRITA
Mode Register Set/ *8,9,10 Extended Mode Register Set
Notes: *1. V = Valid, L = Logic Low, H = Logic High, X = either L or H, Hi-Z = High Impedance. *2. All commands are assumed to be valid state transitions. *3. All inputs for command are latched on the rising edge of clock(CLK). *4. NOP and DESL commands have the same effect on the part. Unless specifically noted, NOP will represent both NOP and DESL command in later descriptions. *5. BST is effective after READ command is issued. *6. READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has been activated (ACTV command). Refer to "s STATE DIAGRAM". *7. ACTV command should only be issued after corresponding bank has been page closed by PRE or PALL command. *8. Either PRE or PALL command and MRS or EMRS command are required after power up. *9. MRS or EMRS command should only be issued after all banks have been page closed (PRE or PALL command), and DQs are in Hi-Z. Refer to "s STATE DIAGRAM". *10. Refer to"s MODE REGISTER TABLE".
6
MB81P643287-50/-60
DM TRUTH TABLE (Effective during Write mode) Function Data Mask for DQ0 to DQ7 Data Mask for DQ8 to DQ15 Data Mask for DQ16 to DQ23 Data Mask for DQ24 to DQ31 CKE TRUTH TABLE Current State Idle Idle Selfrefresh Selfrefresh Idle Power Down Power Down CKE Function Auto-refresh Self-refresh Entry Self-refresh Continue Self-refresh Exit Power Down Entry *13 Notes *11 *11 *12 Command REF SELF -- SELFX PDEN -- PDEX
(n-1) (n)
Command MASK0 MASK1 MASK2 MASK3
CKE (n - 1) H H H H (n) X X X X
DM0 H X X X
DM1 X H X X
DM2 X X H X
DM3 X X X H
CS RAS CAS WE L L X L H L H X L H L L X H X H X X H X L L X H X H X X H X H H X H X H X X H X
AP X X X X X X X X X X
BA0 to BA2
A0
to
A10 X X X X X X X X X X
DQ0 to DQ31
H H L L L H H L L L
H L L H H L L L H H
X X X X X X X X X X
-- Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Power Down Continue Power Down Exit
*11: The REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL command). In case of SELF command, it should also be issued after the last read data have been appeared on DQ. Refer to "s STATE DIAGRAM". *12: CKE must bring to Low level together with REF command. *13: The PDEN command should only be issued after the last read data have been appeared on DQ and after the lDPL is satisfied from last write data input.
7
MB81P643287-50/-60
OPERATION COMMAND TABLE (Applicable to single bank)(Note*13) Current Address Command CS RAS CAS WE State H L L L L Idle L L L L L H L L L Bank Active L L L L L L X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L X H L H L H L L H L X H L H L H L L H L X X X BA, CA, AP BA, CA, AP BA, RA BA, AP BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP BA, AP X MODE DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS NOP NOP NOP Illegal Illegal
Function
Notes
*15 *16 *16
Bank Active after lRCD NOP NOP Auto-refresh or Self-refresh Mode Register Set (Idle after lMRD) NOP NOP NOP Begin Read; Determine AP Begin Write; Determine AP Illegal Precharge Precharge Illegal Illegal *15 *16 *15 *15 *17 *17
8
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current State CS H L L L Read L L L L L L H L L L Write L L L L L L H L L L L L X H H H H L L L L L L H H H L L X H H L L H H H L L L H L L H L X H L H L H L L H L BA, CA, AP BA, RA BA, AP BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP BA, AP X MODE WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS RAS CAS X H H H X H H L WE X H L H Address X X X BA, CA, AP Command DESL NOP BST READ/READA Function Notes
NOP (Continue Burst to End Bank Active) NOP (Continue Burst to End Bank Active) Terminate Burst Bank Active Terminate Burst, New Read; Determine AP Illegal Illegal Terminate Burst, Precharge Terminate Burst, Precharge Illegal Illegal NOP (Continue Burst to End Write Recovering) NOP (Continue Burst to End Write Recovering) Illegal Terminate Burst, Start Read; Determine AP Terminate Burst, New Write; Determine AP Illegal Terminate Burst, Precharge Terminate Burst, Precharge Illegal Illegal *16 *18 *15, *18 *20 *15 *16
9
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current State CS H L L Read With AutoPrecharge L L L L L L L H L L Write with Auto Precharge L L L L L L L RAS CAS X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L WE X H L H L H L L H L X H L H L H L L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP BA, AP X MODE Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS Function Notes
NOP (Continue Burst to End Precharge) NOP (Continue Burst to End Precharge) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal NOP (Continue Burst to End Write Recovering with Precharge) NOP (Continue Burst to End Write Recovering with Precharge) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal *16 *16 *16 *16 *16 *16
10
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current State CS H L L L Precharging L L L L L L H L L L Bank Activating L L L L L L RAS CAS X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L WE X H L H L H L L H L X H L H L H L L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP BA, AP X MODE Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS Function NOP (Idle after lRP) NOP (Idle after lRP) NOP (Idle after lRP) Illegal Illegal Illegal NOP NOP Illegal Illegal NOP (Bank Active after lRCD) NOP (Bank Active after lRCD) NOP (Bank Active after lRCD) Illegal Illegal Illegal Illegal Illegal Illegal Illegal *15 *16 *16 *19 *16 *15 *16 *16 *16 *16 *15 Notes
11
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current State CS H L L L Write Recovering L L L L L L H L L Write Recovering with Autoprecharge L L L L L L L H L L Refreshing L L L L H L X X X X RAS CAS X H H H H L L L L L X H H H H L L L L L X H H X H H L L H H H L L X H H L L H H H L L X H L WE X H L H L H L L H L X H L H L H L L H L X X X Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP BA, AP X MODE X X X Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP/BST Function NOP (Bank Active after lWRD) NOP (Bank Active after lWRD) NOP (Bank Active after lWRD) Illegal New Write; Determine AP Illegal Illegal Illegal Illegal Illegal NOP (Idle after lWAL) NOP (Idle after lWAL) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal NOP (Idle after lRFC) NOP (Idle after lRFC) *16 *16 *16 *16 *16 *16 *15 *16 Notes
READ/READA/ Illegal WRIT/WRITA ACTV/ PRE/PALL REF/SELF/ MRS Illegal Illegal
12
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current State CS H L Mode Register Setting L L RAS CAS X H H H X H H L WE X H L X Address X X X X Command DESL NOP BST Function NOP (Idle after lMRD) NOP (Idle after lMRD) Illegal Notes
READ/READA/ Illegal WRIT/WRITA Illegal
ACTV/PRE/ PALL/REF/ SELF/MRS Abbreviations: RA = Row Address BA = Bank Address CA = Column Address AP = Auto Precharge L L X X X
Notes: *14. All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle. *15. Entry may affect other banks. *16. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state of that bank. *17. Illegal if any bank is not idle. *18. Must mask preceding data that don`t satisfy lDPL. *19. Legal if other bank specified in BA is idle state and lRRD is satisfied for that bank. *20. Must mask preceding data that don`t satisfy lWRD.
13
MB81P643287-50/-60
COMMAND TRUTH TABLE FOR CKE Current State CKE (n-1) H L CKE (n) X H CS X H RAS X X CAS X X WE X X Address X X Invalid Exit Self-refresh (Self-refresh Recovery Idle after tPDEX + lSCD or lXSNR) Exit Self-refresh (Self-refresh Recovery Idle after tPDEX + lSCD or lXSNR) Illegal Illegal Illegal NOP (Maintain Self-refresh) Invalid Idle after lSCD or lXSNR Idle after lSCD or lXSNR Illegal Illegal Illegal Illegal Invalid Power Down Exit Return to original state after tPDEX Power Down Exit Return to original state after tPDEX Illegal Illegal Illegal NOP (Maintain Power Down Mode) Function Notes
Selfrefresh
L L L L L L H H H H H H H L
H H H H L X H H H H H L X H H H H H L
L L L L X X H L L L L X X H L L L L X
H H H L X X X H H H L X X X H H H L X
H H L X X X X H H L X X X X H H L X X
H L X X X X X H L X X X X X H L X X X
X X X X X X X X X X X X X X X X X X X
Selfrefresh Recovery
Power Down
L L L L L
14
MB81P643287-50/-60
COMMAND TRUTH TABLE FOR CKE (continued) Current State CKE (n-1) H H H H H All Banks Idle H H H H H H H L H Bank Active H L L CKE (n) H H H H H L L L L L L L X H L H L CS H L L L L H L L L L L L X X X X X RAS X H L L L X H H H L L L X X X X X CAS X X H L L X H H L H L L X X X X X WE X X X H L X H L X X H L X X X X X Address X V V X V X X X X X X X X X X X X NOP Refer to the Command Truth Table. Refer to the Command Truth Table. Auto-refresh Mode Register Set Power Down Entry Power Down Entry Illegal Illegal Illegal Self-refresh Entry Illegal Invalid Refer to the Command Truth Table. Illegal Invalid Invalid *22 *21 *22 *22 Function Notes
15
MB81P643287-50/-60
COMMAND TRUTH TABLE FOR CKE (continued) Current State Bank Activating, Read, Write, Write Recovering, Precharging Any State Other Than Listed Above CKE (n-1) H H L L L H H H H H Refresh H H L L H CKE (n) H L H L X H L L L L L L L H H CS X X X X X X X H L L L L X X X RAS X X X X X X X L H H H L X X X CAS X X X X X X X L H H L X X X X WE X X X X X X X L H L X X X X X Address X X X X X X X X X X X X X X X Function Notes
Refer to the Command Truth Table. Illegal Invalid Invalid Invalid Refer to the Command Truth Table. Illegal Illegal Illegal Illegal Illegal Illegal Invalid Invalid Refer to the Command Truth Table. *23 *23
Notes: *21. Refer to "s MODE REGISTER TABLE". *22. PDEN and SELF command should only be issued after the last read data have been appeared on DQ. *23. The Clock Suspend mode is not supported on this device and it is illegal if CKE is brought to Low during the Burst Read or Write mode.
16
MB81P643287-50/-60
s STATE DIAGRAM
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION Second command (same bank) First command MRS
*1
MRS
ACTV READ
READA
WRIT
WRITA
BST
PRE
PALL
REF
SELF
lMRD
lMRD
*4 *4
lMRD
lMRD
lMRD
lMRD
lMRD
ACTV
lRCD
lRCD
*4
lRCD
*3
lRCD
*3, 4
1
lRAS
*4
lRAS
*4
READ
*5, 6
1
1
lRWD
lRWD
1
1
*4
1
*4 *6 *5, 6
READA
BL/2 + lRP
BL/2 + lRP
*7 *4, 7 *4
BL/2 + lRP
*4,7
BL/2 + lRP
*4,7
BL/2 + lRP
BL/2 + lRP
WRIT
*6
lWRD
lWRD
1
1
lDPL
*4
lDPL
*4 *6 *6
WRITA
lWAL
lWAL
*3 *3
lWAL
*4
lWAL
*4
lWAL
lWAL
BST
*5, 6
1
1
lBSNC
lBSNC
1
1
1
*4 *6 *5, 6
PRE
lRP
*5
lRP
1
1
1
lRP
lRP
*5
PALL
lRPA
lRPA
1
1
1
lRPA
lRPA
REF
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
SELFX
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
Notes: *1. BL/2 = tCK x BL / 2. (Example: In case of BL = 4, BL/2 means 2 clocks.) *2. Assume PALL command does not affect any operation on the other bank(s). *3. Assume no I/O conflict. *4. lRAS must be satisfied. *5. Assume all outputs are in High-Z state. *6. Assume all other banks are in idle state. *7. lDPL and lWRD are specified from last data input and assumed preceding pair of write data are masked by DM0 to DM3 input. Illegal Command 17
MB81P643287-50/-60
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTIPLE BANK OPERATION Second command (other bank)
*10 *8 *8 *8 *8 *9 *2, 9
MRS
ACTV READ
READA
WRIT
WRITA
BST
PRE
PALL
REF
SELF
First command MRS lMRD lMRD
*6 *11 *11 *11 *11
lMRD
*11
lMRD
lMRD
lMRD
lMRD
ACTV
lRRD
*6
1
1
1
*3
1
*3
1
1
lRAS
*4
READ
*5, 6
1
*6
1
*4
1
*4
lRWD
* 3, 4
lRWD
* 3, 4
1
1
1
*6 *5, 6
READA
BL/2 + lRP
1
*6
1
*7
1
*7
lRWD
lRWD
1
BL/2 + BL/2 + BL/2 + lRP lRP lRP
*4,7
WRIT
*6
1
*6
lWRD
*4
lWRD
*4
1
*4
1
*4
1
lDPL
*6 *6
WRITA
lWAL
1
*6
BL/2 BL/2 + lWRD + lWRD
*11 *11
1
*3, 11
1
*3, 11
1
lWAL
*4
lWAL
lWAL
BST
*5, 6
1
*6
1
*11
1
*11
lBSNC
*3, 11
lBSNC
*3, 11
1
*11
1
1
*4 *6 *5, 6
PRE
lRP
*5
1
1
1
1
1
1
1
1
lRP
lRP
*5
PALL
lRPA
lRPA
1
1
1
lRPA
lRPA
REF
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
SELFX
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
18
MB81P643287-50/-60
Notes: *1. BL/2 = tCK x BL / 2. (Example: In case of BL = 4, BL/2 means 2 clocks.) *2. Assume PALL command does not affect any operation on the other bank(s). *3. Assume no I/O conflict. *4. lRAS must be satisfied. *5. Assume all outputs are in High-Z state. *6. Assume the other bank(s) is in idle state. *7. lDPL and lWRD are specified from last data input and assumed preceding pair of write data are masked by DM0 to DM3 input. *8. Assume the other bank(s) is in active state and lRCD is satisfied. *9. Assume the other bank(s) is in active state and lRAS is satisfied. *10. Second command have to follow the minimum clock latency or delay time of single bank operation in other bank (second command is asserted.) *11. Assume other banks are not in READA/WRITA state. Illegal Command.
19
MB81P643287-50/-60
Fig. 2 - STATE DIAGRAM (Simplified for Single Bank Operation)
MRS MODE REGISTER SET PDEX PDEN IDLE
SELF SELFX SELFREFRESH
REF
BANK ACTIVE BST WRIT WRIT WRITA WRITE WRIT WRITA READA PRE or PALL WRITA READA READA READ READ READ READ
WRITE WITH AUTO PRECHARGE
ACTV
POWER DOWN
AUTO REFRESH
PRE or PALL
PRE or PALL
READ WITH AUTO PRECHARGE
POWER ON
PDEX and 8 PRE (or 1 PALL)
PRECHARGE
POWER APPLIED with PDEN
DEFINITION OF ALLOWS Manual Input Automatic Sequence
20
MB81P643287-50/-60
s FUNCTIONAL DESCRIPTION
DDR, Double Data Rate Function The regular SDRAM read and write cycle have only used the rising edge of external clock input. When clock signal goes to High from Low at the read mode, the read out data will be available at every rising clock edge after the specified latency up to burst length. The MB81P643287 DDR FCRAM features a twice of data transfer rate within a same clock period by transferring data at every rising and falling clock edge. Refer to Figure 3. FCRAMTM The MB81P643287 utilizes FCRAM core technology. The FCRAM is an acronym of Fast Cycle Random Access Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs. CLOCK INPUT (CLK, CLK) The MB81P643287 adopts differential clock scheme. CLK is a master clock and its rising edge is used to latch all command and address inputs. CLK is a complementary clock input. The MB81P643287 implements Delay Locked Loop (DLL) circuit. This internal DLL tracks the signal cross point between CLK and CLK and generate some clock cycle delay for the output buffer control at Read mode. The internal DLL circuit requires some Lock-on time for the stable delay time generation. In order to stabilize the delay, a constant stable clock input for lPCD period is required during the Power-up initialization and a constant stable clock input for lSCD period is also required after Self-refresh exit as specified lSCD prior to the any command. POWER DOWN (CKE) CKE is a synchronous input signal and enables power down mode. When all banks are in idle state, CKE controls Power Down (PD) and Self-refresh mode. The PD and Self-refresh is entered when CKE is brought to Low and exited when it returns to High. During the Power Down and Self-refresh mode, both CLK and CLK are disabled after specified time. CKE does not have a Clock Suspend function unlike CKE pin of regular SDRAMs, and it is illegal to bring CKE into Low if any read or write operation is being performed. For the detail, refer to Timing Diagrams. It is recommended to maintain CKE to be Low until VDD gets in the specified operating range in order to assure the power-up initialization. CHIP SELECT (CS) CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, all command signals are negated but internal operation such as burst cycle will not be suspended. COMMAND INPUTS (RAS, CAS and WE) As well as regular SDRAMs, each combination of RAS, CAS and WE input in conjunction with CS input at a rising edge of the CLK determines SDRAM operation. Refer to "sFUNCTION TRUTH TABLE".
21
MB81P643287-50/-60
BANK ADDRESS (BA0 to BA2) The MB81P643287 has eight internal banks and each bank is organized as 256K words by 32-bit. Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT or WRITA), and Precharge(PRE) command. ADDRESS INPUTS (A0 to A10) Address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix within each bank. A total of twenty address input signals are required to decode such a matrix. DDR SDRAM adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV), eleven Row addresses are initially latched as well as three Bank addresses and the remainder of seven Column addresses are then latched by a Column address strobe command of either a read command (READ or READA) or write command (WRIT or WRITA). DATA STROBE (DQS0 to DQS3) DQS0 to DQS3 are bi-directional signal and represent byte 0 to byte 3, respectively. During Read operation, DQS0 to DQS3 provides the read data strobe signal that is intended to use input data strobe signal at the receiver circuit of the controller(s). It turns Low before first data is coming out and toggle High to Low or Low to High till end of burst read. Refer to Figure 3 for the timing example. The CAS Latency is specified to the first Low to High transition of these DQS0 to DQS3 output. During the write operation, DQS0 to DQS3 are used to latch write data and Data Mask signals. As well as the behavior of read data strobe, the first rising edge of DQS0 to DQS3 input latches first input data and following falling edge of DQS0 to DQS3 signal latches second input data. This sequence shall be continued till end of burst count. Therefore, DQS0 to DQS3 must be provided from controller that drives write data. Note that DQS0 to DQS3 input signal should not be tristated from High at the end of write mode. DATA INPUTS AND OUTPUTS (DQ0 to DQ31) Input data is latched by DQS0 to DQS3 input signal and written into memory at the clock following the write command input. Output data is obtained together with DQS0 to DQS3 output signals at programmed read CAS latency. The polarity of the output data is identical to that of the input. Data is valid after DQS0 to DQS3 output signal transitions (tQSQ) as specified in Data Valid Time (tDV). WRITE DATA MASK (DM0 to DM3) DM0 to DM3 are active High enable inputs and represent byte 0 to byte 3 respectively. DM0 to DM3 have a data input mask function, and are also sampled by DQS0 to DQS3 input signal together with input data. During write cycle, DM0 to DM3 provide byte mask function. When DMx = High is latched by a DQS0 to DQS3 signal edge, data input at the same edge of DQS0 to DQS3 is masked. During read cycle, all DM0 to DM3 are inactive and do not have any effect on read operation. Refer to DM0 to DM3 TRUTH TABLE.
22
MB81P643287-50/-60
BURST MODE OPERATION AND BURST TYPE The burst mode provides faster memory access and MB81P643287 read and write operations are burst oriented. The burst mode is implemented by keeping the same Row address and by automatic strobing Column address in every single clock edge till programmed burst length(BL). Access time of burst mode is specified as tACC. The internal column address counter operation is determined by a mode register which defines burst type(BT) and burst count length(BL) of 2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 2, the following combinations will be required. Current Stage Next Stage Method (Assert the following command) Burst Read Burst Read Burst Write Burst Write Burst Read Burst Write Burst Read Burst Write Burst Write Burst Read Precharge Precharge Read Command 1st Step 2nd Step 1st Step 2nd Step 1st Step 2nd Step Burst Stop Command (BST) Write Command after lBSNC Data Mask Input Read Command after lWRD from last data input Data Mask Input Precharge Command after lDPL from last data input
Write Command
Precharge Command
The burst type is sequential only. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to the least significant address(= 0). If the first access of column address is even (0), the next address will be odd (1), or vice-versa. Starting Column Address Sequential Mode Burst Length A2 A1 A0 2 XX0 XX1 X00 4 X01 X10 X11 000 001 010 8 011 100 101 110 111 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
23
MB81P643287-50/-60
BURST STOP COMMAND (BST) The Burst Stop command (BST) terminates the burst read operation except for a case that Auto-precharge option is asserted. When the BST command is issued during the burst read operation, the all output buffers, DQs and DQS0 to DQS3, will turn to High-Z state after some latencies that to be matched with programmed CAS latency and internal bank state remains active state. In a case of terminating the burst write operation, the BST command should not be issued at any time during burst write operation. Refer to previous page for the write interrupt and termination rule. PRECHARGE AND PRECHARGE OPTION (PRE, PALL) The DDR SDRAM memory core is the same as conventional DRAMs', requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is executed by the precharge operation (PRE or PALL). With the precharge operation, DDR SDRAM will automatically be in standby state after specified precharge time (lRP lRPA). , The precharged bank is selected by combination of AP and bank address (BA) when precharge command is issued. If AP = High, all banks are precharged regardless of BA (PALL command). If AP = Low, a bank to be selected by BA is precharged (PRE command). The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command issue. This auto-precharge is entered by AP = High when a Read (READ) or Write (WRIT) command is issued. Applying BST is illegal if the Auto-precharge option is used. Refer to "sFUNCTION TRUTH TABLE". AUTO-REFRESH (REF) Auto-refresh uses the internal refresh address counter. The MB81P643287 Auto-refresh command (REF) automatically generates Bank Active and Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be issued within every 8 s period. SELF-REFRESH ENTRY (SELF) Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the refresh operation until cancelled by SELFX. The Self-refresh mode is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once MB81P643287 enters the self-refresh mode, all inputs except for CKE can be either logic high or low level state and outputs will be in a High-Z state. During Self-refresh mode, CKE = Low should be maintained. SELF command should only be issued after last read data has been appeared on DQ. Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted prior to the self-refresh mode entry. SELF-REFRESH EXIT (SELFX) To exit Self-refresh mode, CKE must bring to High for at least 2 clock cycles together with NOP condition. Refer to Timing Diagram for the detail procedure. It is recommended to issue at least one Auto-refresh command just after the lRFC period to avoid the violation of refresh period. WARNING: A stable clock for lSCD period with a constant duty cycle must be supplied prior to applying any read command to insure the DLL is locked against the latest device conditions. Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted both before the self-refresh entry and after the self-refresh exit.
24
MB81P643287-50/-60
MODE REGISTER SET (MRS) The mode register of SDRAM provides a variety of different operations. The register consists of four operation fields; Burst Length, Burst Type, CAS Latency, and Test Mode Entry (This Test Mode Entry must not be used). Refer to MODE REGISTER TABLE. The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power). MRS command should only be issued on condition that all banks are in idle state and all DQS are in High-Z. The condition of the mode register is undefined after the powerup stage. It is required to set each field at power-up initialization. Refer to POWER-UP INITIALIZATION below. Note: The Extended Mode Register Set command (EMRS) and its DLL Enable function of EMRS field is only used at power-on sequence. POWER-UP INITIALIZATION The MB81P643287 internal condition at and after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. Apply VDD voltage to all VDD pins before or at the same time as VDDQ pins and attempt to maintain all input signals to be Low state (or at least CKE to be Low state). 2. Apply VDD voltage to all VDDQ pins before or at the same time as VREF and VTT. 3. Apply VREF and VTT. (VTT is applied to the system). 4. Start clock after all power supplies reached in a specified operating range and maintain stable condition for a minimum of 200 s. 5. After the minimum of 200 s stable power and clock, apply NOP condition and take CKE to be High state. 6. Issue Precharge All Banks (PALL) command or Precharge Single Bank (PRE) command to every banks. 7. Issue EMRS to enable DLL, DE = Low. 8. Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for lPCD*1 period is required to lock the DLL. 9. Apply minimum of two Auto-refresh command (REF).*2 10. Program the mode register by Mode Register Set command (MRS) with DR = Low.*2 *1: The lPCD depends on operating clock period. The lPCD is counted from "DLL Reset" at step-8 to any command input at step-10. *2: The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle. POWER-DOWN The MB81P643287 uses multiple power supply voltage. It is required to follow the reversed sequence of above Power On Sequence. 1. Take all input signals to be VSS or High-Z. 2. Deapply VDDQ. 3. Deapply VDD at the same time as VDDQ.
25
MB81P643287-50/-60
Fig. 3 - SDRAM READ TIMING EXAMPLE (@ CL=2 & BL=2)
t0 t1 t2 t3 t4
CLK (external)
Command
READ Stored by CLK input
DATA
Hi-Z
Q1
Q2
Output in every rising CLK edge
< DDR SDRAM >
t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4
CLK CLK
Command
READ Stored by CLK input DQS signal transition occurs at the same time as data bus. Low High
DQS
Hi-Z
DATA
Hi-Z
Q1
Q2
Output in every cross point of clock input
26
MB81P643287-50/-60
s MODE REGISTER TABLE
MODE REGISTER SET ADDRESS BA2 BA1 BA0 REGISTER 0*1 0*1 0*1 A10 0 A9 0 A8 DR A7 TE A6 to A4 CL A3 BT A2 to A0 BL
A6 0 0 0 1 1 1 1 A7 0 1 A8 0 1
A5 0 1 1 0 0 1 1
A4 X 0 1 0 1 0 1
CAS Latency (CL) Reserved 2 3 Reserved Reserved Reserved Reserved
A2 0 0 0 0 1
A1 0 0 1 1 X
A0 0 1 0 1 X
Burst Length (BL) Reserved 2 4 8 Reserved
Test Mode Entry (TE) Normal Operation Test Mode (Used for Supplier Test Mode) DLL RESET (DR) Normal Operation RESET DLL
A3 0 1 Reserved
Burst Type (BT) Sequential (Wrap round, Binary up)
EXTENDED MODE REGISTER SET (Note *4) ADDRESS BA2 BA1 BA0 A10 A9 EXTENDED MODE REGISTER 0*2 0*2 1*2
A8
A7
A6
A5
A4
A3
A2
A1
A0 DE
RESERVED *3
A0 0 1
DLL Enable (DE) DLL Enable DLL Disable
*1: A combination of BA2 = BA1 = BA0 = 0 (Low) selects standard Mode Register. *2: A combination of BA1 = BA2 = 0 and BA0 = 1 (High) selects Extended Mode Register. *3: These RESERVED field in EMRS must be set as 0.
27
MB81P643287-50/-60
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Storage Temperature Symbol VDD, VDDQ VIN, VOUT IOUT PD TSTG Value -0.5 to +3.6 -0.5 to +3.6 50 2.0 -55 to +125 Unit V V mA W C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS) Parameter Supply Voltage Input Reference Voltage Termination Voltage Single Ended SSTL DC Level Input High Voltage Single Ended SSTL DC Level Input Low Voltage *1 *2 *3 *3 Notes Symbol VDD VDDQ VSS, VSSQ VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VIN (DC) Min. 2.3 VDD 0 VREF - 0.04 VREF + 0.25 - 0.1 VREF + 0.35 -- - 0.1 0.5 0.7 VDDQ/2 - 0.2 VDDQ/2 - 0.2 -- 0 Typ. 2.5 VDD 0 VREF -- -- -- -- -- -- -- VDDQ/2 VDDQ/2 50 -- Max. 2.7 VDD 0 VREF + 0.04 VDDQ + 0.1 VREF - 0.25 -- VREF - 0.35 VDDQ + 0.1 VDDQ + 0.2 -- VDDQ/2 + 0.2 VDDQ/2 + 0.2 -- 70 Unit V V V V V V V V V V V V V V
o
VDDQ x 0.49 VDDQ x 0.5 VDDQ x 0.51
Single Ended SSTL AC Level Input High Voltage *3, *5 Single Ended SSTL AC Level Input Low Voltage *3, *5 Differential DC Level Input Voltage Range Differential DC Level Differential Input Voltage Differential AC Level Differential Input Voltage Differential AC Level Input Crosspoint Voltage Differential Input Signal Offset Voltage Termination Resistor (SSTL I/Os) Ambient Temperature *3
*3 VSWING (DC) *3 VSWING (AC) *3 *4 *2 VX (AC) VISO (AC) RT TA
C
Note 5.
VDD + 1.0 V 50% of pulse amplitude VIH VIHmin VIL Pulse width < 4 ns
Note 6.
VIH VILmax VIL 50% of pulse amplitude -1.0 V Pulse width < 4 ns
28
MB81P643287-50/-60
Notes: *1. VREF is expected to track variations in the DC level of VDDQ of the transmitting device. Peak-to-Peak noise level on VREF may not exceed 2% of the supplied DC value. *2. VTT is used for SSTL_2 bus and is not applied to the device. VTT is expected to be set equal to VREF and must be track variations in the DC level of VREF. *3. Applicable when signal(s) is terminated to the VTT of SSTL_2 bus. *4. VISO means {VIN(CLK) + VIN(CLK)} / 2. Refer to Differential Input Signal Definition. *5. Overshoot limit: VIH (Max.) = VDD + 1.0V for pulse width 4 ns acceptable, pulse width measured at 50% of pulse amplitude. *6. Undershoot limit: VIL (Min.) = VSS -1.0V for pulse width 4 ns acceptable, pulse width measured at 50%of pulse amplitude. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Differential Input Signal Definition Fig. 4 - Differential Input Signal Offset Voltage (For Clock Input)
CLK VX CLK VSS IVSWINGI VSWING (AC)
0 V Differential VISO VISO (Min.) VSS VISO (Max.)
s CAPACITANCE
(TA = 25C, f = 1 MHz) Parameter Input Capacitance, Address & Control Input Capacitance, CLK & CLK Input Capacitance, DM0 to DM3 I/O Capacitance Symbol CIN1 CIN2 CIN3 CI/O Min. 2.5 2.5 4.0 4.0 Typ. -- -- -- -- Max. 3.5 3.5 5.5 5.5 Unit pF pF pF pF
29
MB81P643287-50/-60
s DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1,*2,*3 Parameter Output Minimum Source DC Current Output Minimum Sink DC Current Input Leakage Current (any input) Output Leakage Current VREF Current MB81P643287-50 Operating Current (Average Power Supply Current) MB81P643287-60 IDD1S Symbol IOH(DC) IOL(DC) ILI ILO IREF Burst Length = 2 tCK = Min., One bank active, Address change up to 3 times during lRC (Min.) 0 V VIN VIL (Max.), VIH (Min.) VIN VDD CKE = VIH, tCK = Min. All banks idle, NOP commands only, Input signals (except to CMD) are changed one time during 20 ns 0 V VIN VIL (Max.), VIH (Min.) VIN VDD CKE = VIL, tCK = Min. All banks idle, 0 V VIN VDD CKE = VIH, tCK = Min. All banks Active, NOP commands only, Input signals (except to CMD) are changed one time during 20 ns 0 V VIN VIL (Max.), VIH (Min.) VIN VDD Condition VDDQ = 2.3V, VOH = VDDQ-0.43V VDDQ = 2.3V, VOL = +0.35V 0 V VIN VDD; All other pins not under test = 0 V 0 V VIN VDD; Data out disabled Value Min. -15.2 15.2 -10 -10 -10 Max. -- -- 10 10 10 460 -- 405 mA Unit mA mA A A A
MB81P643287-50 Standby Current MB81P643287-60 IDD2N
85 -- 75 mA
Power Down Current
IDD2P
--
35
mA
MB81P643287-50 Active Standby Current (Power Supply Current) MB81P643287-60 IDD3N
260 -- 225 mA
(Continued)
30
MB81P643287-50/-60
(Continued)
Parameter Symbol Condition Burst Length = 4, CAS Latency = 3, All bank active, Gapless data, tCK = Min., 0 V VIN VIL (Max.), VIH (Min.) VIN VDD Burst Length = 4, CAS Latency = 3, All bank active, Gapless data, tCK = Min., 0 V VIN VIL (Max.), VIH (Min.) VIN VDD Auto-refresh; tCK = Min., 0 V VIN VIL (Max.), VIH (Min.) VIN VDD Self-refresh; CKE = VIL, 0 V VIN VDD Value Min. Max. 535 -- 460 mA Unit
MB81P643287-50 Burst Read Current (Average Power Supply Current) IDD4R MB81P643287-60
MB81P643287-50 Burst Write Current (Average Power Supply Current) IDD4W MB81P643287-60
595 -- 505 mA
Auto-refresh Current MB81P643287-50 (Average Power Supply Current) MB81P643287-60 Self-refresh Current (Average Power Supply Current)
320 -- 270 mA
IDD5
IDD6
--
5
mA
Notes: *1. All voltages referenced to VSS. *2. DC characteristics are measured after following the POWER-UP INITIALIZATION procedure. *3. IDD depends on the output termination or load conditions, clock cycle rate, and number of address and command change within certain period. The specified values are obtained with the output open.
31
MB81P643287-50/-60
s AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.) Note *1,*2,*3 AC PARAMETERS (CAS LATENCY DEPENDENT) Parameter Clock Period tCK Symbol CL = 3 CL = 2 MB81P643287-50 MB81P643287-60 Min. 5.0 7.5 Max. 9.0 10.5 Min. 6.0 9.0 Max. 10.5 10.5 Unit ns
Parameter Input Setup Time (Except for DQS, DM and DQs) Input Hold Time (Except for DQS, DM and DQs) DM and Data Input Setup Time DM and Data Input Hold Time DQS First Input Setup Time (Input Preamble Setup Time) Last Data Output to CKE High Level Hold Time Input Transition Time Precharge Power Down Exit and Self-refresh Exit Time Time between Refresh Time between Auto-refresh Command Pause Time after Power-on
Notes *4 *4 *5 *5 *6
Symbol tIS tIH tDS tDH tDSPRES tQCKEH
MB81P643287-50 MB81P643287-60 Min. 1.0 1.0 0.6 0.6 0 0 0.1 3.0 -- -- 200 Max. -- -- -- -- -- -- 0.8 -- 32 8.0 -- Min. 1.2 1.2 0.7 0.7 0 0 0.1 3.6 -- -- 200 Max. -- -- -- -- -- -- 0.9 -- 32 8.0 --
Unit ns ns ns ns ns ns ns ns ms s s
*7 *4 *8 *8
tT tPDEX tREF tAREF tPAUSE
32
MB81P643287-50/-60
AC PARAMETERS (FREQUENCY DEPENDANT) Note *9 Parameter Clock High Time Clock Low Time DQS Low to High Input Transition Setup Time from CLK DQS Low Input Pulse Width DQS High Input Pulse Width DQS First Low Input Hold Time (Input Preamble Hold Time) DQS First Low Input Pulse Width (Input Preamble Pulse Width) DQS Last Low Input Hold Time (Input Postamble Hold Time) DQS Access Time from Clock DQS Output Valid Time DQS Output in Low-Z (Output Preamble Setup Time) DQS First Low Output Hold Time (Output Preamble Hold Time) DQS Last Low Output Hold Time (Output Postamble Hold Time) DQS Last Low Output in High-Z from CLK or CLK DQ Access Time from CLK & CLK DQ Access Time from DQS DQ Output Data Valid Time from DQS DQ Output in Low-Z DQ Output in High-Z DQ & DM Input Pulse Width DQS Falling Edge to Clock Hold Time DQS Falling Edge to Clock Setup Time *4, *11 *4, *12 *4, *11 *4 *4, *12 *12 *4 *5 *4 *4 Notes Symbol *4 *4 *4, *10 tCH tCL tDQSS tDSL tDSH tDSPREH tDSPRE tDSPST tQSCK tQSV tQSLZ tQSPRE tQSPST tQSHZ tACC tQSQ tDV tLZ tHZ tDIPW tDSCH tDSCS Min. 0.45 x tCK 0.45 x tCK 0.75 x tCK 0.4 x tCK 0.4 x tCK 0.25 x tCK 0.4 x tCK 0.4 x tCK - 0.1 x tCK - 0.2 0.3 x tCK - 0.1 x tCK - 0.2 0.9 x tCK - 0.2 0.4 x tCK - 0.2 -- - 0.1 x tCK - 0.2 - 0.1 x tCK 0.3 x tCK - 0.1 x tCK - 0.2 - 0.1 x tCK - 0.2 0.4 x tCK 0.2 x tCK (1.5 ns Min.) 0.2 x tCK (1.5 ns Min.) Max. -- -- 1.25 x tCK -- -- -- -- -- 0.1 x tCK + 0.2 -- -- 1.1 x tCK + 0.2 0.6 x tCK + 0.2 0.1 x tCK + 0.2 0.1 x tCK + 0.2 0.1 x tCK -- -- 0.1 x tCK + 0.2 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
33
MB81P643287-50/-60
EXAMPLE OF FREQUENCY DEPENDANT AC PARAMETERS (@ Minimum tCK) tCK = 6ns tCK = 7.5ns tCK = 9ns tCK = 5ns Parameter Symbol Clock High Time Clock Low Time DQS Low to High Input Transition Setup Time from CLK DQS Low Input Pulse Width DQS High Input Pulse Width DQS First Low Input Hold Time (Input Preamble Hold Time) DQS First Low Input Pulse Width (Input Preamble Pulse Width) DQS Last Low Input Hold Time (Postamble Hold Time) DQS Access Time from Clock DQS Output Valid Time DQS Output in Low-Z (Output Preamble) DQS First Low Output Hold Time (Output Preamble) DQS Last Low Output Hold Time (Output Postamble) DQS Last Low Output in High-Z from CLK or CLK DQ Output Access Time from CLK & CLK DQ Output Access Time from DQS DQ Output Data Valid Time from DQS DQ Output in Low-Z DQ Output in High-Z DQ & DM Input Pulse Width DQS Falling Edge to Clock Hold Time DQS Falling Edge to Clock Setup Time tCH tCL tDQSS tDSL tDSH tDSPREH tDSPRE tDSPST tQSCK tQSV tQSLZ tQSPRE tQSPST tQSHZ tACC tQSQ tDV tLZ tHZ tDIPW tDSCH tDSCS 2.3 2.3 3.8 2.0 2.0 1.3 2.0 2.0 -0.7 1.5 -0.7 4.3 1.8 -- -0.7 -0.5 1.5 -0.7 -0.7 2.0 1.5 1.5 -- -- 6.3 -- -- -- -- -- 0.7 -- -- 5.7 3.2 0.7 0.7 0.5 -- -- 0.7 -- -- -- 2.7 2.7 4.5 2.4 2.4 1.5 2.4 2.4 -0.8 1.8 -0.8 5.2 2.2 -- -0.8 -0.6 1.8 -0.8 -0.8 2.4 1.5 1.5 -- -- 7.5 -- -- -- -- -- 0.8 -- -- 6.8 3.8 0.8 0.8 0.6 -- -- 0.8 -- -- -- 3.4 3.4 5.7 3.0 3.0 1.9 3.0 3.0 -1.0 2.3 -1.0 6.6 2.8 -- -1.0 -0.8 2.3 -1.0 -1.0 3.0 1.5 1.5 -- -- 9.4 -- -- -- -- -- 1.0 -- -- 8.5 4.7 1.0 1.0 0.8 -- -- 1.0 -- -- -- 4.1 4.1 6.8 3.6 3.6 2.3 3.6 3.6 -1.1 2.7 -1.1 7.9 3.4 -- -1.1 -0.9 2.7 -1.1 -1.1 3.6 1.8 1.8 -- -- 11.3 -- -- -- -- -- 1.1 -- -- 10.1 5.6 1.1 1.1 0.9 -- -- 1.1 -- -- --
tCK = 10.5ns
Min. Max.
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
4.8 4.8 7.9 4.2 4.2 2.7 4.2 4.2 -1.3 3.2 -1.3 9.3 4.0 -- -1.3 -1.1 3.2 -1.3 -1.3 4.2 2.1 2.1
-- -- 13.2 -- -- -- -- -- 1.3 -- -- 11.8 6.5 1.3 1.3 1.1 -- -- 1.3 -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
34
MB81P643287-50/-60
LATENCY (The latency values on these parameters are fixed regardless of clock period.) MB81P643287-50 MB81P643287-60 Symbol Parameter Notes Min. Max. Min. Max. RAS Cycle Time RAS Active Time RAS Precharge Time RAS to CAS Delay Time CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 *14 *13 CL = 3 CL = 2 CL = 3 CL = 2 lRC lRAS lRP lRCD lRRD lRPA lRWD lWRD lDPL lWAL lMRD lCCD lCBD lPDEXP lSCD 6 5 4 3 2 3 2 1 4 3 BL/2+3 BL/2+2 2.5 2.5 BL/2+3+lRP 2 1 1 2 400 -- -- 11000 7333 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6 5 4 3 2 3 2 1 4 3 BL/2+3 BL/2+2 2.5 2.5 BL/2+3+lRP 2 1 1 2 400 -- -- 11000 7333 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit
tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
RAS to RAS Bank Active Delay Time Precharge All Bank to Active Read Command to Write Command Delay Last Input Data to Read Command Delay
Last Input Data to Precharge Command Lead Time *14 Write with Auto Precharge Command to Active command Delay *14 Mode Register Access to Next Command Input Delay CAS to CAS Delay CAS Bank Delay Precharge Power Down Exit to Next Command Input Delay Minimum Stable Clock Input After Self- *15 refresh Exit Before READ Command Input Minimum Stable Clock Input After Selfrefresh Exit Before non-READ Command Input Minimum Stable Clock Input for tCK 7.5ns DLL Lock-on in Power-up Initialization sequence. *16 tCK 10.5ns Auto-refresh Cycle Time
lXSNR
12 400
-- -- -- --
12 400 630 12
-- -- -- --
tCK tCK tCK tCK
lPCD lRFC
630 12
35
MB81P643287-50/-60
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Parameter BST Command to Output in High-Z BST Command to New Command Input *17 DM to Input Data Delay Precharge to Output in High-Z
Notes Symbol MB81P643287-50 CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 lBSH lBSNC lDQD lROH lCKE 3 2 3 2 0 3 2 1
MB81P643287-60 3 2 3 2 0 3 2 1
Unit tCK tCK tCK tCK tCK tCK tCK tCK
CKE Low to Command/Address Input Inactive
36
MB81P643287-50/-60
Notes: *1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure and stable clock input with constant clock period and with 50% duty cycle. *2. Access Times assume input slew rate of 1ns/volt between VREF+0.35V to VREF-0.35V, where VREF is VDDQ/2, with SSTL_2 output load conditions. Refer to AC TEST LOAD CIRCUIT. *3. VREF = 1.25V is a typical reference level for measuring timing of input signals. Transition times are measured between VIH(Min.) and VIL(Max.) unless otherwise noted. Refer to AC TEST CONDITIONS. *4. This parameter is measured from the cross point of CLK and CLK input. *5. This parameter is measured from signal transition point of DQS0 to DQS3 input crossing VREF level. *6. The specific requirement is that DQS be valid (HIGH or LOW) on or before this CLK edge. The case shown (DQS going from High-Z to logic LOW) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be HIGH at this time, depending on tDSS. *7. tT is defined as the transition time between VIH (AC)(Min.) and VIL (AC)(Max.). *8. Total of 4096 REF command must be issued within tREF (Max.). tAREF is a reference value for distributed refresh and specifies the time between one REF command to next REF command except for a condition where CKE = Low during Self-refresh mode. *9. This parameter is scalable by actual clock period (tCK) and affected by an abrupt change of duty cycle, jitters on clock input, TA and level of VDD and VDDQ.The internal DLL circuit can adjust delay time against the change of following condition : TA < 0.1 C / 20 ns, VDD < 1 mV / 10 ns, VDDQ < 1 mV / 10 ns, if change rate is bigger than these values, frequency dependent AC parameters affected by DLL jitters. *10. More than 2 signal edge of DQS0 to DQS3 should not be input within 1 clock (tCK) cycle. *11. Low-Z (Low Impedance State) is specified and measured at VTT 200mV. *12. tQSPST, tQSHZ and tHZ are specified where output buffer is no longer driven. *13. Actual clock count of lRC will be sum of clock count of lRAS and lRP . *14. Assume tDQSS = 1 x tCK. If actual tDQSS is within specified minimum and maximum range, those parameters can be assumed tDQSS = 1 x tCK. *15. Applicable also if device operating conditions such as supply voltages, case temperature, and/or clock frequency (tCK difference must be 0.2 ns or less) is changed during any operation. *16. Clock period must satisfy specified tCK and it must be stable. *17. Assume BST is effective to read operation (issued prior to the end of burst read).
37
MB81P643287-50/-60
Fig. 5 - AC TEST LOAD CIRCUIT (SSTL_2, Class II)
VTT = 0.5 x VDDQ Output measurement point RS = 25 Output Z0 = 50 VDDQ VREF Device Under Test VDDQ 0.5 x VDDQ
VTT = 0.5 x VDDQ
RT1 = 50
RT2 = 50
VREF = 0.5 x VDDQ CL = 20 pF
VSS
Note: AC characteristics are measured in this condition. This load circuit is not applicable for DC Test.
AC TEST CONDITIONS Parameters Single-end Input Input High Level Input Low Level Input Reference Level Input Slew Rate Differential Input (CLK and CLK) Input Reference Level Input Level Input Slew Rate Vr VSWING SLEW VX (AC)* 0.7 1.0 V V V/ns VIH VIL VREF SLEW VREF + 0.35 VREF - 0.35 VDDQ / 2 1.0 V V V V/ns Symbol Value Unit
* : VX means the actual cross point between CLK and CLK input.
38
MB81P643287-50/-60
Fig. 6 - AC TIMING of CLK & CLK
tCK tCL tCH VX
CLK
VSWING (AC)
CLK
Note: Reference level for AC timings of clock are the cross point of CLK and CLK as specified in VX.
Fig. 7 - AC TIMING of Command Input & Address
tCK
CLK CLK
tIS tIH VIH (AC) Input Valid VREF VIL (AC)
VX
Input (Controls & Addresses)
Note: The cross point of CLK and CLK (VX) is used for command and address input. The reference level of single ended input is VREF.
Fig. 8 - AC TIMING of Write Mode (Data Strobe, Write Data and Data Mask Input)
tCK tCK
CLK CLK
tIS tIH VIH (AC) Write Command tDQSS tDSPRES tDSPREH tDSPRE VIL tDS tDH tDSCH tDS tDH tDS tDH tDS tDH tDSH VREF VIL (AC) tDQSS tDSL tDSH tDSPST VREF tDSCS
Input (Controls & Addresses)
DQS Input (@BL = 4)
VREF
Input (Data & DM)
Input Valid tDIPW
Input Valid tDIPW
Input Valid tDIPW
Input Valid tDIPW
39
MB81P643287-50/-60
Fig. 9 - AC TIMING of Read Mode (Clock to DQS Output Delay Time)
tCK tCK VX tQSCK(Min.) tQSPRE tQSCK
(Min.)
CLK CLK
tQSLZ
(Min.)
tQSCK
(Min.)
tQSCK
(Min.)
tQSHZ tQSCK
(Max.)
tQSCK
(Max.)
tQSCK
(Max.)
tQSCK
(Max.)
DQS Output (@BL = 4)
VTT VTT - 0.2 V tQSV tQSV tQSV tQSPST
Note: DQS Access time (tQSCK) is measured from the cross point of clock (VX) and VREF. The end of tQSPST and tQSHZ specification is defined at where output buffer is no longer driven.
Fig. 10 - AC TIMING of Read Mode (Clock to Data Output Delay Time)
tCK tCK VX tACC tLZ
(Min.) (Min.)
CLK CLK
tACC
(Min.)
tACC
(Min.)
tHZ tACC
(Max.)
tACC
tACC
(Max.)
tACC
(Max.)
DQS Data Output (@BL = 4)
(Max.)
VTT
VTT + 0.2 V VTT - 0.2 V
Note: Access time (tACC) is measured from the cross point of clock (VX) and VREF. The end of tHZ specification is defined at where output buffer is no longer driven.
Fig. 11 - AC TIMING of Read Mode (DQS Output to Data Output Delay Time)
DQS Output (@BL = 4)
tQSQ
(Min.)
VREF tQSQ
(Min.)
tQSQ
(Min.)
tQSQ
(Min.)
tQSQ
tQSQ
(Max.)
tQSQ
(Max.)
tQSQ
(Max.)
DQ Data Output (@BL = 4)
(Max.)
VTT
VTT + 0.2 V VTT - 0.2 V tDV tDV tDV tDV
Note: DQS Output Edge to Data Output Edge Skew Time (tQSQ) is measured from VTT to VTT.
40
MB81P643287-50/-60
Fig. 12 - AC TIMING, PULSE WIDTH
CLK CLK
VX VX
IRAS, IRP, IRPA, IRCD, IRRD, tREF, tAREF
Input (Controls & Addresses)
Command
Command
Note: All parameters listed above are measured from the cross point at rising edge of the CLK and falling edge of CLK of one command input to next command input.
Fig. 13 - AC TIMING of Precharge Power Down Mode
IRC (Min.), tREF (Max.)
CKE
VREF tIS tPDEX IPDEXP (Min.) *2
CLK CLK
ICKE Note*1
Command
NOP
NOP
NOP
Don't Care
NOP
NOP
ACTV
Notes: *1. Minimum 2 clock cycles is required for complete power down on clock buffer. *2. If either any supply voltage or clock input condition is changed from the previous operating condition (other than PDEN and REF), lSCD must be satisfied prior to any command input.
Fig. 14 - AC TIMING of Self-refresh Mode
IRFC (Min.) *2
CKE
VREF
tIS
tPDEX
ISCD *3 or IXSNR
CLK CLK
Note *1 ICKE
Command
NOP
SELF
NOP
Don't Care
NOP
NOP
ACTV
Notes: *1. Minimum 2 clock cycles is required for complete power down on clock buffer. *2. CKE must maintain High level and clock must be provided during the lSCD period. lSCD must be satisfied before read command input. *3. lSCD must be satisfied before read command input. 41
MB81P643287-50/-60
s TIMING DIAGRAMS
TIMING DIAGRAM - 1: COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK CLK
lRCD (Min.) lCCD (Min.) Column Address Column Address lCCD Column Address lCCD Column Address lCCD Column Address
Address
Row Address
RAS
CAS
Note: lCCD, CAS to CAS address delay, is applicable to the same bank access and it can be one or more clock period.
TIMING DIAGRAM - 2: DIFFERENT BANK ADDRESS INPUT DELAY
CLK CLK
lRRD (Min.) lCBD (Min.) Row Address lRCD (Min.) lRCD (Min.) Column Address lCBD Column Address lCBD Column Address lCBD Column Address
Address
Row Address
BA0, BA1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 2
bank 3
RAS
CAS
42
MB81P643287-50/-60
TIMING DIAGRAM - 3: READ (EXAMPLE @ BL = 4)
CLK CLK
CKE
High ICCD (Min.)
Command
READ
READ
NOP
CAS Latency CAS Latency
DQS (Output) @CL = 2
Hi-Z Preamble
DQ0 to DQ31 Hi-Z (Output) @CL = 2
Q1
Q2
Q1
Q2
Q3
Q4
CAS Latency CAS Latency
DQS (Output) @CL = 3
Hi-Z Preamble
DQ0 to DQ31 Hi-Z (Output) @CL = 3
Q1
Q2
Q1
Q2
Q3
Q4
Note: CAS Latency is defined from Read command to first rising edge of DQS0 to DQS3 output. Preamble is 1 x tCK length and starts driving Low level.
43
MB81P643287-50/-60
TIMING DIAGRAM - 4: WRITE (EXAMPLE @ BL = 4)
CLK CLK CKE
High ICCD (Min.)
Command
WRIT tDSPRES
WRIT tDSPREH
NOP
Don't Care
tDQSS Don't Care
DQS (Input)
Don't Care
tDSPRE tDQSS
DQ0 to DQ31 (Input)
Don't Care
D1
D2
D1
D2
D3
D4
Note: DQS Setup Time, tDQSS, must be within a range of 0.75*tCK to 1.25*tCK from write command Input.
TIMING DIAGRAM - 5: DM, WRITE DATA MASK (EXAMPLE @ BL = 4)
CLK CLK
Command
WRIT tDQSS
NOP
WRIT tDQSS
NOP
DQS (Input)
Don't Care
Don't Care
DM
Don't Care lDQD = 0 lDQD = 0 D1 Masked D3 D4
Don't Care
DQ0 to DQ31 (Input)
Don't Care
D1
D2
Masked
D4
Don't Care
Note: DM are latched by DQS Input together with Data Input after write command.
44
MB81P643287-50/-60
TIMING DIAGRAM - 6: READ WITH AUTO-PRECHARGE (EXAMPLE @ CL = 2.0, BL = 4 Applied to same bank)
CLK CLK
IRAS (Min.) BL x tCK + lRP (See note) 2
IRP (Min.) ACTV
Command
ACTV IRCD (Min.) Hi-Z
READA
CAS Latency
DQS (Output)
DQ0 to DQ31 Hi-Z (Output)
Q1
Q2
Q3
Q4
Note: Internal precharge operation at Read with Auto-precharge command (READA) is started BL/2 clock later from READA command. If BL=2, the READA command should not be issued no earlier than 1 clock (BL/2 = 1) before lRAS (Min.). If BL=4, the READA command should not be issued no earlier than 2 clock (BL/2=2) before lRAS (Min.).
TIMING DIAGRAM - 7: WRITE WITH AUTO-PRECHARGE (EXAMPLE @ CL = 2.0, BL = 4 Applied to same bank)
CLK CLK
IRAS (Min.) (See note) IWAL (Min.)
Command
ACTV IRCD (Min.) Hi-Z
WRITA
ACTV
tDQSS
DQS (Input)
DQ0 to DQ31 Hi-Z (Input)
D1
D2
D3
D4
Note: Write with Auto-precharge command (WRITA) must be issued after lRCD is satisfied and be considered to meet lRAS requirement applied to end of burst length (BL) regardless of where it is masked or not. 45
MB81P643287-50/-60
TIMING DIAGRAM - 8: READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 8)
CLK CLK
Command
READ
PRE
NOP
IROH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z (Output)
Q1
Q2
Command
READ
NOP
PRE
NOP
IROH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z (Output)
Q1
Q2
Q3
Q4
Command
READ
NOP
PRE
NOP
IROH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z (Output)
Q1
Q2
Q3
Q4
Q5
Q6
Command
READ
NOP
PRE
NOP
No effect (End of Burst)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z (Output)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Note: lROH is the same as CAS Latency (CL). In case of CL =3, the lROH is 3 clock.
46
MB81P643287-50/-60
TIMING DIAGRAM - 9: READ INTERRUPTED BY BURST STOP (EXAMPLE @ CL = 2, BL = 8)
CLK CLK
Command
READ
BST
NOP
IBSH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z (Output)
Q1
Q2
Command
READ
NOP
BST
NOP
IBSH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z (Output)
Q1
Q2
Q3
Q4
Command
READ
NOP
BST
NOP
IBSH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z (Output)
Q1
Q2
Q3
Q4
Q5
Q6
Command
READ
NOP
BST
NOP
No effect (End of Burst)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z (Output)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Note: lBSH is the same as CAS Latency (CL). In case of CL =3, the lBSH is 3 clock.
47
MB81P643287-50/-60
TIMING DIAGRAM - 10: WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 8)
CLK CLK
IRP (Min.)
Command
WRIT tDQSS
NOP IDPL(Min.)
PRE
NOP
ACTV
DQS (Iutput)
Don't Care See Note 1.
Don't Care
DM
Don't Care
Don't Care
DQ0 to DQ31 (Input)
Don't Care
D1
D2

Don't Care
See Note 2.
Note: 1. DQS Input are not required from when Precharge command is issued. 2. This pair of write data must be masked prior to Precharge command.
TIMING DIAGRAM - 11: READ TO WRITE (EXAMPLE @ CL = 2, BL = 4)
CLK CLK
IRWD (Min.)
Command
READ CL
NOP
WRIT tDQSS
NOP
DQS
Hi-Z
DM
Don't Care
DQ0 to DQ31
Hi-Z
Q1
Q2
Q3
Q4
D1
D2
D3
D4
I/O open for bus turn-around
Note: lRWD defines a minimum delay from Read to Write command input applied to the same bank.
48
MB81P643287-50/-60
TIMING DIAGRAM - 12: READ TO WRITE (EXAMPLE @ CL = 2, BL = 4)
CLK CLK
lBSNC
Command
READ
BST
NOP lBSH
WRIT tDQSS
NOP
DQS
Hi-Z
DM
Don't Care
DQ0 to DQ31
Hi-Z
Q1
Q2
D1 Terminated
D2
D3
D4
Note: DM are latched by DQS Input after Write command together with data Input.
TIMING DIAGRAM - 13: WRITE TO READ (EXAMPLE @ CL = 2, BL = 8)
CLK CLK
Command
WRIT tDQSS
NOP lWRD
READ CL
NOP
DQS
Hi-Z
DM
Don't Care
Hi-Z
DQ0 to DQ31
D1
D2 Masked Terminated by Read
Q1
Q2
Note: Read command must be issued after lWRD is satisfied and proceeding pair of data must be masked.
49
MB81P643287-50/-60
TIMING DIAGRAM - 14: READ WITH AUTO-PRECHARGE (EXAMPLE @ CL = 2, BL = 4, Multiple Bank Operation)
CLK CLK
lRP (Min.) BL x tCK + lRP 2 lRCD (Min.) ACTV lCBD Bank 3 Bank 1 lRRD (Min.) Bank 0 ACTV lCBD Bank 1 READ
Command
READA lCBD
PRE lCBD Bank 1 CAS Latency
READA lCBD Bank 2
READA
BA0, BA1
Bank 0
DQS (Output)
Hi-Z
DQ0 to DQ31 (Output)
Hi-Z
Q1
Q2
Q3
Q4
Q1
Q2
Q1
Q2
Q3
Q4
Note: Back to back Read with Auto-precharge (READA) command to the different bank in active state is possible. However, any new command to the same bank applied READA command can only be issued after (BL/2) x tCK+lRP .
TIMING DIAGRAM - 15: WRITE WITH AUTO-PRECHARGE (EXAMPLE @ CL = 2, BL = 4, Multiple Bank Operation)
CLK CLK
lWAL (Min.) lRP (Min.)
Command
WRITA
WRITA
PRE
WRITA
ACTV lRRD (Min.) Bank 2
ACTV
lCBD (Min.)
lCBD (Min.)
lCBD (Min.) Bank 3
BA0, BA1
Bank 0
Bank 1
Bank 2 tDQSS
Bank 0
tDQSS
tDQSS
DQS (Input)
DQ0 to DQ31 (Input)
D1
D2
D1
D2
D3
D4
D1
D2
D3
D4
Note: Back to back Write with Auto-precharge (WRITA) command to the different bank in active state is possible. However, any new command to the same bank applied WRITA command can only be issued after lWAL. 50
MB81P643287-50/-60
TIMING DIAGRAM - 16: AUTO-REFRESH ENTRY AND EXIT
CLK CLK
IRFC (Min.)
Command
REF
NOP
Any
TIMING DIAGRAM - 17: SELF-REFRESH ENTRY AND EXIT
IRFC (Min.)
CKE
tQCKEH tIS tPDEX IXSNR or ISCD *
CLK CLK
Command
NOP
SELF
Don't Care
NOP
NOP
ACTV
DQS (Output) DQ0 to DQ31 (Output)
Hi-Z
Q
Hi-Z Last Data Output
Note * :CKE must maintain High level and stable clock must be provided during the lSCD period. After Self-refresh exit, lXSNR must be satisfied for at least specified period before any command (except for read) input.
TIMING DIAGRAM - 18: MODE REGISTER SET
CLK CLK
IMRD
Command
NOP
MRS
NOP
Any
Note: MRS command must be issued after the last data is appeared on each DQ. 51
MB81P643287-50/-60
s SCITT TEST MODE
ABOUT SCITT SCITT (Static Component Interconnection Test Technology) is an XNOR circuit based test technology that is used for testing interconnection between SDRAM and SDRAM controller on the printed circuit boards. SCITT provides inexpensive board level test mode in combination with boundary-scan. The basic idea is simple, consider all output of SDRAM as output of XNOR circuit and each output pin has a unique mapping on the input of SDRAM. The ideal schematic block diagram is as shown below.
TEST Control C SDRAM Controller SDRAM CORE xAddress Bus XNOR
Boundary Scan
ASIC
Data Bus
TEST Control : CAS, CS, CKE xAddress Bus : A0 to A10, BA0 to BA2, RAS, DM0 to DM3, CLK, CLK, WE Data Bus : DQ0 to DQ31, DQS0 to DQS3
It is static and provides easy test pattern that result in a high diagnostic resolution for detecting all open/short faults.
52
MB81P643287-50/-60
SCITT TEST SEQUENCE The followings are the SCITT test sequence. SCITT Test can be executed after power-on and prior to Precharge command in"s FUNCTION DESCRIPTION POWER-UP INITIALIZATION". Once Precharge command is issued to SDRAM, it never get back to SCITT Test Mode during regular operation unless reset power supply for the purpose of a fail-safe way in get in and out of test mode. Maintain all input signals (except CLK,CLK) to be Low state (or at least CKE to be Low) and maintain CLK and CLK to be complementary state. 2. Apply VDD voltage to all VDD pins before or at the same time as VDDQ pins. 3. Apply VDD voltage to all VDDQ pins before or at the same time as VREF and VTT. 4. Apply VREF and VTT (VTT is applied to the system). 5. Maintain stable power for a minimum of 100s. 6. Enter SCITT test mode. 7. Execute SCITT test. 8. Exit from SCITT mode. It is required to follow Power On Sequence to execute read or write operation. 9. Start clock after all power supplies reached in a specified operating range and maintain stable condition for a minimum of 200s. 10. After the minimum of 200s stable power and clock, apply NOP condition and take CKE to be High state. 11. Issue Precharge All Banks (PALL) command or Precharge Single Bank (PRE) command to every banks. 12. Issue EMRS to enable DLL, DE = Low. 13. Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for lPCD*1 period is required to lock the DLL. 14. Apply minimum of two Auto-refresh command (REF).*2 15. Program the mode register by Mode Register Set command (MRS) with DR = Low.*2 The 6,7,8 steps define the SCITT mode available. It is possible to skip these steps if necessary (Refer to "s FUNCTION DESCRIPTION POWER-UP INITIALIZATION"). 1. Notes: *1. The lPCD depends on operating clock period. The lPCD is counted from "DLL Reset" at step-13 to any command input at step-15. *2. The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle.
53
MB81P643287-50/-60
COMMAND TRUTH TABLE Note *1 Control CAS CS CKE WE RAS Input A0 to A10, BA0 to BA2 X X V DM0 to DM3 X X V CLK H L X V CLK L H X V Output DQ0 to DQ31 X X V DQS0 to DQS3 X X V
SCITT mode entry HL *2 SCITT mode exit SCITT mode output enable *4
L
L L *5 H
X X V
X X V
LH *3 H *5 L L
Notes: *1. L = Logic Low, H = Logic High, V = Valid, X = either L or H *2. The SCITT mode entry command assumes the first CAS falling edge with CS = CKE = L and CLK,CLK signals are complementary after power on. *3. The SCITT mode exit command assumes the first CAS rising edge after the test mode entry. *4. Refer the test code table. *5. CS = H or CKE = L is necessary to disable outputs in SCITT mode exit.
54
MB81P643287-50/-60
TEST CODE TABLE DQ0 to DQ31 and DQS0 to DQS3 output data is static and is determined by following logic during the SCITT mode operation.
DQ0 = RAS xnor A0 DQ1 = RAS xnor A1 DQ2 = RAS xnor A2 DQ3 = RAS xnor A3 DQ4 = RAS xnor A4 DQ5 = RAS xnor A5 DQ6 = RAS xnor A6 DQ7 = RAS xnor A7 DQ8 = RAS xnor A8 DQ9 = RAS xnor A9 DQ10 = RAS xnor A10 DQ11 = RAS xnor BA1 DQ12 = RAS xnor BA0 DQ13 = RAS xnor BA2 DQ14 = RAS xnor DM0 DQ15 = RAS xnor DM1 DQ16 = RAS xnor DM2 DQ17 = RAS xnor DM3 DQ18 = RAS xnor CLK DQ19 = RAS xnor CLK DQ20 = RAS xnor WE DQ21 = A0 xnor A1 DQ22 = A0 xnor A2 DQ23 = A0 xnor A3 DQ24 = A0 xnor A4 DQ25 = A0 xnor A5 DQ26 = A0 xnor A6 DQ27 = A0 xnor A7 DQ28 = A0 xnor A8 DQ29 = A0 xnor A9 DQ30 = A0 xnor A10 DQ31 = A0 xnor BA0 DQS0 = A0 xnor BA1 DQS1 = A0 xnor BA2 DQS2 = A0 xnor DM0 DQS3 = A0 xnor DM1
* EXAMPLE OF TEST CODE TABLE
Input bus Output bus RAS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA0 BA1 BA2 DM0 DM1 DM2 DM3 CLK CLK WE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS0 DQS1 DQS2 DQS3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH L L L L L L L L L L L L L L L L L L L L L HHHHHHHHHHHHHHH L HHHHHHHHHHHHHHHHHHHHL L L L L L L L L L L L L L L HL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHH HHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHH HHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHH HHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHH HHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHH HHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHH HHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHH HHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHH HHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHH HHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHH HHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHH HHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHH HHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HH HHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL H HHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHH L L L L L L L L L L L L L L L L L L L L L HHHHHHHHHHHHHHH L HHHHHHHHHHHHHHHHHHHHL L L L L L L L L L L L L L L HL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHH HHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHH HHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHH HHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHH HHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHH HHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHH HHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHH HHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHH HHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHH HHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHH HHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHH HHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHH HHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HH HHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL H HHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH 0 = input Low, 1 = input High, L = output Low, H = output High
55
MB81P643287-50/-60
AC SPECIFICATION Parameter tTS tTH tEPD tTLZ tTHZ tTCA tTIA tTOH tETD tTIH Description Test mode entry set up time Test mode entry hold time Test mode exit to power on sequence delay time CS, CKE to output in Low-Z time CS, CKE to output in High-Z time Test mode access time from control signals (clock enable & chip select) Test mode Input access time Test mode Output Hold time Test mode entry to test delay time Test mode input hold time Min. 10 10 10 0 0 -- -- 0 10 30 Max. -- -- -- -- 20 40 20 -- -- -- Units ns ns ns ns ns ns ns ns ns ns
56
MB81P643287-50/-60
TIMING DIAGRAMS TIMING DIAGRAM - 1: POWER-UP TIMING DIAGRAM
VDD
100 s Pause Time Test Mode Entry Point
CS
CKE
CAS
*3 *1
tETD
CLK
CLK or CLK
CLK
*2
Notes: *1. CAS shall be staid either High or Low at power on. *2 . All output buffers maintains in High-Z state regardless of the state of control signals except for CAS as long as the above timing is maintained. *3. CAS must not be brought from High to Low.
57
MB81P643287-50/-60
TIMING DIAGRAM - 2 : SCITT TEST ENTRY AND EXIT *1
Next power on sequence and normal operation
VCC
Pause 100 s tTS tTH Test Mode tEPD
CAS
H
L
CS
L
PD
L
*3
tETD
CLK
CLK
or
CLK
CLK
*2
Entry
Exit
Notes: *1. If entry and exit operation have not been done correctly, CAS, CS, CKE pins will have some problems. *2. PRE or PALL commands must not be asserted. Test mode is disable by those commands. *3. Outputs must be disabled by CS = H or CKE = L before Exit. 58
MB81P643287-50/-60
TIMING DIAGRAM - 3: OUTPUT CONTROL (1)
VDD Entry CAS must not brought from High to Low CAS DQ turn to Low-Z at CS = L and CKE = H CS DQ turn to High-Z at CS = H
CKE
High-Z DQ0 to DQ31 DQS0 to DQS3 Memory device output buffer status High-Z Time (a) tTLZ Low-Z Time (b) tTHZ High-Z Time (c)
This is not bus line level
TIMING DIAGRAM - 4: OUTPUT CONTROL (2)
VDD
Entry CAS must not brought from High to Low
CAS
DQ turn to Low-Z at CS = L and CKE = H
CS
DQ turn to High-Z at CKE = L
CKE
High-Z
DQ0 to DQ31 DQS0 to DQS3
Memory device output buffer status High-Z Time (a) tTLZ Low-Z Time (b) tTHZ High-Z Time (c)
This is not bus line level
59
MB81P643287-50/-60
TIMING DIAGRAM - 5: TEST TIMING (1)
Test mode Entry Command tETD Test mode Entry Under test
CAS
CS
CKE
DQ becomes Low-Z at CS = L and CKE = H
A0
tTCA
Under Check Pins
A1
tTIA tTIA tTIA
A2
tTOH DQ0 to DQ31 DQS0 to DQS3 Valid tTOH Valid Valid
tTLZ
60
MB81P643287-50/-60
TIMING DIAGRAM - 6: TEST TIMING (2)
Test mode Entry Test mode Exit
Under test
CAS
L
CS-#1
L H Tested #1 device Changed under test devices
CS-#2
Tested #2 device
CKE
tTIH tTIH tTIH tTCA
A0
tTLZ
Under Check Pins
tTHZ
A1
tTIA tTIA tTIA tTIA tTIA
A2
tTOH tTOH Valid Valid tTOH Valid Valid
DQ0 to DQ31 DQS0 to DQS3
Valid
61
MB81P643287-50/-60
TIMING DIAGRAM - 7: TEST TIMING (3)
Test mode Entry Test mode Exit
Under test
CAS
L
CS-#1
L H Tested #1 device Changed under test devices
CS-#2
Tested #2 device
CKE
tTIH tTIH tTHZ tTIH
A0 Under Check Pins
tTCA
A1
tTIA tTIA tTIA tTLZ tTIA tTIA
A2
tTOH tTOH Valid Valid tTOH Valid Valid
DQ0 to DQ31 DQS0 to DQS3
Valid
62
MB81P643287-50/-60
s ORDERING INFORMATION
Part number MB81P643287-50FN MB81P643287-60FN Package 86-pin plastic TSOP(II) (FPT-86P-M01) Remarks
63
MB81P643287-50/-60
s PACKAGE DIMENSIONS
86-pin plastic TSOP (II) (FPT-86P-M01) *: Resin protrusion.(Each side: 0.15 (.006) Max.)
86
44
Details of "A" part
0.25(.010)
INDEX 0~8 0.45/0.75 (.018/.030)
LEAD No.
1
43
* 22.220.10(.875.004)
0.22 .009
+0.05 -0.04 +.002 -.002
11.760.20(.463.008) 1.20(.047)MAX (Mounting height) 10.160.10(.400.004) 0.145 -0.03 .006 -.001
+0.05 +.002
0.10(.004)
M
0.50(.020)TYP
0.10(.004) 21.00(.827)REF
0.100.05 (.004.002) (STAND OFF)
"A"
C
1996 FUJITSU LIMITED F86001S-1C-1
Dimensions in mm (inches).
MB81P643287-50/-60
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0010 (c) FUJITSU LIMITED Printed in Japan

▲Up To Search▲

Price & Availability of MB81P643287

	To Download MB81P643287 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .