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XC9572 In-System Programmable CPLD
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DS065 (v4.1) August 21, 2003
Product Specification
Features
* * * * * 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3V or 5V I/O capability Advanced CMOS 5V Fast FLASHTM technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages
Description
The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
Power Management
Power dissipation can be reduced in the XC9572 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC9572 device.
200 (160)
* *
* * * * * * * * * *
Typical ICC (mA)
Hig
(125) 100
rma h Perfo
nce
Low P
ower
(100)
(65)
0
50
100
DS065_01_110501
Clock Frequency (MHz)
Figure 1: Typical ICC vs. Frequency for XC9572
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DS065 (v4.1) August 21, 2003 Product Specification
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XC9572 In-System Programmable CPLD
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3 JTAG Port 1
JTAG Controller
In-System Programming Controller
36 I/O I/O I/O
Fast CONNECT II Switch Matrix
18
Function Block 1 Macrocells 1 to 18
I/O
36 18
Function Block 2 Macrocells 1 to 18
I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS
36 18
Function Block 3 Macrocells 1 to 18
36 18
Function Block 4 Macrocells 1 to 18
DS065_02_110101
Figure 2: XC9572 Architecture Function block outputs (indicated by the bold line) drive the I/O blocks directly.
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DS065 (v4.1) August 21, 2003 Product Specification
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XC9572 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TJ Description Supply voltage relative to GND Input voltage relative to GND Voltage applied to 3-state output Storage temperature (ambient) Junction temperature Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +150 Units V V V
oC oC
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol VCCINT Parameter Supply voltage for internal logic and input buffers Supply voltage for output drivers for 5V operation Commercial TA = 0oC to 70oC Industrial TA = -40oC to +85oC Commercial TA = 0oC to 70oC Industrial TA = -40oC to +85oC Min 4.75 4.5 4.75 4.5 3.0 0 2.0 0 Max 5.25 5.5 5.25 5.5 3.6 0.80 VCCINT + 0.5 VCCIO V V V V Units V
VCCIO
Supply voltage for output drivers for 3.3V operation VIL VIH VO Low-level input voltage High-level input voltage Output voltage
Quality and Reliability Characteristics
Symbol TDR NPE Data Retention Program/Erase Cycles (Endurance) Parameter Min 20 10,000 Max Units Years Cycles
DC Characteristic Over Recommended Operating Conditions
Symbol VOH VOL IIL IIH CIN ICC Parameter Output high voltage for 5V outputs Output high voltage for 3.3V outputs Output low voltage for 5V outputs Output low voltage for 3.3V outputs Input leakage current I/O high-Z leakage current I/O capacitance Operating supply current (low power mode, active) Test Conditions IOH = -4.0 mA, VCC = Min IOH = -3.2 mA, VCC = Min IOL = 24 mA, VCC = Min IOL = 10 mA, VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 2.4 65 (Typical) Max 0.5 0.4 10 10 10 Units V V V V A A pF mA
DS065 (v4.1) August 21, 2003 Product Specification
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XC9572 In-System Programmable CPLD
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AC Characteristics
XC9572-7 Symbol TPD TSU TH TCO fCNT(1) fSYSTEM TPSU TPH TPCO TOE TOD TPOE TPOD TWLH
(2)
XC9572-10 Min 6.0 0 111.1 66.7 2.0 4.0 4.5 Max 10.0 6.0 10.0 6.0 6.0 10.0 10.0 -
XC9572-15 Min 8.0 0 95.2 55.6 4.0 4.0 5.5 Max 15.0 8.0 12.0 11.0 11.0 14.0 14.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns
Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low)
Min 4.5 0 125.0 83.3 0.5 4.0 4.0
Max 7.5 4.5 8.5 5.5 5.5 9.5 9.5 -
Notes: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
VTEST
R1 Device Output R2 CL
Output Type
VCCIO 5.0V 3.3V
VTEST 5.0V 3.3V
R1 160 260
R2 120 360
CL 35 pF 35 pF
DS067_03_110101
Figure 3: AC Load Circuit
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DS065 (v4.1) August 21, 2003 Product Specification
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XC9572 In-System Programmable CPLD
Internal Timing Parameters
XC9572-7 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN Input buffer delay GCK buffer delay GSR buffer delay GTS buffer delay Output buffer delay Output buffer enable/disable delay 2.5 1.5 4.5 5.5 2.5 0 3.5 2.5 6.0 6.0 3.0 0 4.5 3.0 7.5 11.0 4.5 0 ns ns ns ns ns ns Parameter Min Max XC9572-10 Min Max XC9572-15 Min Max Units
Product Term Control Delays TPTCK TPTSR TPTTS Product term clock delay Product term set/reset delay Product term 3-state delay 3.0 2.0 4.5 3.0 2.5 3.5 2.5 3.0 5.0 ns ns ns
Internal Register and Combinatorial Delays TPDI TSUI THI TCOI TAOI TRAI TLOGI Combinatorial logic propagation delay Register setup time Register hold time Register clock to output valid time Register async. S/R to output delay Register async. S/R recover before clock Internal logic delay 1.5 3.0 7.5 0.5 0.5 6.5 2.0 10.0 2.5 3.5 10.0 1.0 0.5 7.0 2.5 11.0 3.5 4.5 10.0 3.0 0.5 8.0 3.0 11.5 ns ns ns ns ns ns ns ns
TLOGILP Internal low power logic delay
Feedback Delays
TF TLF
Fast CONNECT II feedback delay Function block local feedback delay
-
8.0 4.0
-
9.5 3.5
-
11.0 3.5
ns ns
Time Adders TPTA(1) Incremental product term allocator delay TSLEW Slew-rate limited delay 1.0 4.0 1.0 4.5 1.0 5.0 ns ns
Notes: 1. TPTA is multiplied by the span of the function as defined in the XC9500 family data sheet.
DS065 (v4.1) August 21, 2003 Product Specification
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XC9572 In-System Programmable CPLD
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XC9572 I/O Pins
Function Block Macrocell PC44 PC84 PQ100 TQ100 BScan Order Function Block Macrocell PC44 PC84 PQ100 TQ100 BScan Order
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
- 1 - - 2 3 - 4 5[1] - 6[1] - - 7[1] 8 - 9 - - 35 - - 36 37 - 38 39[1] - 40[1] - - 42[3] 43 - 44 -
4 1 6 7 2 3 11 5 9[1] 13 10[1] 18 20 12[1] 14 23 15 24 63 69 67 68 70 71 76[2] 72 74[1] 75 77[1] 79 80 81[3] 83 82 84 -
18 15 20 22 16 17 27 19 24[1] 30 25[1] 35 38 29[1] 31 41 32 42 89 96 93 95 97 98 5[2] 99 1[1] 3 6[1] 8 10 11[3] 13 12 14 94
16 13 18 20 14 15 25 17 22[1] 28 23[1] 33 36 27[1] 29 39 30 40 87 94 91 93 95 96 3[2] 97 99[1] 1 4[1] 6 8 9[3] 11 10 12 92
213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
- 11 - - 12 - - 13 14 - 18 - - 19 20 - 22 - - 24 - - 25 - - 26 27 - 28 - - 29 33 - 34 -
25 17 31 32 19 34 35 21 26 40 33 41 43 36 37 45 39 - 46 44 51 52 47 54 55 48 50 57 53 58 61 56 65 62 66 -
43 34 51 52 37 55 56 39 44 62 54 63 65 57 58 67 60 61 68 66 73 74 69 78 79 70 72 83 76 84 87 80 91 88 92 81
41 32 49 50 35 53 54 37 42 60 52 61 63 55 56 65 58 59 66 64 71 72 67 76 77 68 70 81 74 82 85 78 89 86 90 79
105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0
Notes: 1. Global control piN. 2. Global control pin GTS1 for PC84, PQ100, and TQ100. 3. Global control pin GTS1 for PC44.
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DS065 (v4.1) August 21, 2003 Product Specification
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XC9572 In-System Programmable CPLD
XC9572 Global, JTAG and Power Pins
Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5V VCCIO 3.3V/5V GND PC44 5 6 7 42 40 39 17 15 30 16 21,41 32 10,23,31 PC84 9 10 12 76 77 74 30 28 59 29 38,73,78 22,64 8,16,27,42, 49,60 No Connects PQ100 24 25 29 5 6 1 50 47 85 49 7,59,100 28,40,53,90 2,23,33,46,64,71, 77,86 4,9,21,26,36,45,48, 75, 82 TQ100 22 23 27 3 4 99 48 45 83 47 5,57,98 26,38,51,88 100,21,31,44,62,69, 75, 84 2,7,19,24,34,43,46, 73, 80
DS065 (v4.1) August 21, 2003 Product Specification
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XC9572 In-System Programmable CPLD
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Device Part Marking and Ordering Combination Information
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Device Type Package Speed Operating Range
XC95xxx TQ144 7C
This line not related to device part number
1
Sample package with part marking.
Device Ordering and Part Marking Number XC9572-7PC44C XC9572-7PC84C XC9572-7PQ100C XC9572-7TQ100C XC9572-10PC44C XC9572-10PC84C XC9572-10PQ100C XC9572-10TQ100C XC9572-10PC44I XC9572-10PC84I XC9572-10PQ100I XC9572-10TQ100I XC9572-15PC44C XC9572-15PC84C XC9572-15PQ100C XC9572-15TQ100C XC9572-15PC44I XC9572-15PC84I XC9572-15PQ100I XC9572-15TQ100I
Speed (pin-to-pin delay) 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns
Pkg. Symbol PC44 PC84 PQ100 TQ100 PC44 PC84 PQ100 TQ100 PC44 PC84 PQ100 TQ100 PC44 PC84 PQ100 TQ100 PC44 PC84 PQ100 TQ100
No. of Pins 44-pin 84-pin 100-pin 100-pin 44-pin 84-pin 100-pin 100-pin 44-pin 84-pin 100-pin 100-pin 44-pin 84-pin 100-pin 100-pin 44-pin 84-pin 100-pin 100-pin
Package Type Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC) Plastic Quad Flat Pack (PQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC) Plastic Quad Flat Pack (PQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC) Plastic Quad Flat Pack (PQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC) Plastic Quad Flat Pack (PQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC) Plastic Quad Flat Pack (PQFP) Thin Quad Flat Pack (TQFP)
Operating Range(1) C C C C C C C C I I I I C C C C I I I I
Notes: 1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = -40 to +85C
Revision History
The following table shows the revision history for this document. Date 12/04/98 06/18/03 08/21/03 Version 3.0 4.0 4.1 Revision Update AC characteristics and internal parameters. Updated format. Updated Package Device Marking Pin 1 orientation.
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DS065 (v4.1) August 21, 2003 Product Specification

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