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| CXA3202AN TX Gain Control Amplifier Description CXA3202AN is a TX gain control amplifier suitable for CDMA cellular/PCS phone. Features * Wide gain control range * Linear gain slope * Wideband operation (50 MHz to 300 MHz) * Very small package (16 Pin SSOP) * Low voltage operation * High output IP3 * Power save function included Absolute Maximum Ratings * Supply voltag VCC * * * * * * * 16 pin SSOP (Plastic) 6 V Operating temperature Topr -55 to +125 C Storage temperature Tstg -65 to +150 C Allowable Power dissipation PD 330 mW Supply voltage range -0.3 to 6 V Logic input voltage -0.3 to VCC + 0.3 V Signal input voltage -0.3 to VCC + 0.3 V Differential signal input voltage 0 to 2.5 V Operating Condition Supply voltage Applications CDMA cellular/PCS phone Structure Bipolar silicon monolithic IC VCC 2.7 to 3.8 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. --1-- E98822A8Y CXA3202AN Block Diagram IF Input CDMA IN CDMA INX OUT OUTX IF Output Gain control GCTL Supply Voltage VCC1, 2 Bias Driver Ground GND1, 2 Power Save PSV Pin Configuration CDMA IN CDMA INX NC GND1 GND2 NC NC PSV 1 2 3 4 5 6 7 8 16 15 14 13 12 GCTL NC VCC1 VCC2 GND1 11 GND2 10 9 OUT OUTX --2-- CXA3202AN Pin Description Pin No. Symbol Pin voltage TYP (V) Equivalent circuit VCC1 Description 1 CDMA IN 1.1 1 2 200 40k 40k Differential input pins for CDMA transmit IF signal. 2 CDMA INX 1.1 200 GND1 3 6 7 15 4 12 5 11 NC No connection. GND1 GND2 0 0 VCC1 Ground Ground 8 PSV -- 8 135k Power save function pin. High: Active Low: Power save GND VCC2 510 510 12.25k 9 OUTX -- 12.25k 9 10 Differential output pins for transmit IF signal. Open collector output. 10 OUT -- GND2 13 14 VCC2 VCC1 3.0 3.0 --3-- Positive power supply for output stage. Positive power supply. CXA3202AN Pin No. Symbol Pin voltage TYP (V) Equivalent circuit Description VCC1 8k 8k 200 16 GCTL -- 16 Gain control pin. 6k 6k GND --4-- CXA3202AN Electrical Characteristics DC Characteristics Parameter Current consumption 1 Current consumption 2 Input current pin 8H Input current pin 8L Input current pin 16H Input current pin 16L PSV high voltage PSV low voltage Symbol ICC1 ICC2 IpsvH IpsvL IgctlH IgctlL VpsH VpsL Conditions Vpsv=3.0 V, Vgctl=1.5 V, Pin 13, 14 Vpsv=0 V, Vgctl=1.5 V, Pin 13, 14 Vpsv=3.0 V Vpsv=0 V Vgctl=3.0 V Vgctl=0.5 V Pin 8 Pin 8 Min. 10 5 -15 1 -1 2.5 0.5 (VCC=3.0 V, Ta=27 C) Typ. 15.7 18 Max. 21.5 40 1 Unit mA A V AC Characteristics Parameter Operating frequency range Gain 2.3 Gain 1.5 Gain 1.0 Gain 0.7 CDMA Gain slope Input level 3rd order intercept point Noise Figure Symbol Fr G2.3 G1.5 G1.0 G0.7 GCLIN IIP3 f=130.38 MHz, level=-22.5 dBm, Vgctl=2.3 V Vgctl=1.5 V Vgctl=1.0 V Vgctl= 0.7 V Gain at Vgctl=2.0 V - Gain at Vgctl=1.0 V G=15 dB 1 f1=129.38 MHz, f2=131.38 MHz Measure of 130.38 MHz G=15 dB 1 Measure of 130.38 MHz Conditions Min. 50 13 -28 -58 -75 57 -8.5 (VCC=3.0 V, Ta=27 C) Typ. Max. 300 17 -24 -54 -70 60 -4.5 21 -20 -50 -65 63 dB Unit MHz dB/V dBm NF 28 32 dB 1 Adjust GCTL voltage, and set the overall gain to 15 dB. --5-- CXA3202AN Measurement Circuit 1 CDMA INPUT 1000p 1 2k 10k 1 CDMA IN GCTL 16 A16 V16 1000p 2 2 CDMA INX NC 15 0.01 V14 3 NC VCC1 14 0.01 4 GND1 VCC2 13 A14 5 GND2 GND1 12 820n3 820n3 6 NC GND2 11 7 NC V8 A8 8 PSV OUT 10 2.4k 1 OUTPUT OUTX 9 1 TOKO, Inc. B5FL 616DS-1135 2 Coilcraft, Inc. 1008HS-102TKBC 3 Coilcraft, Inc. 1008HS-821TKBC --6-- CXA3202AN Application Circuit VCC Gain Control Voltage 1000p 1 CDMA IN TX IF INPUT 2 CDMA INX 1000p NC 15 GCTL 16 1k 0.01 100p 0.01 3 NC VCC1 14 4 GND1 VCC2 13 5 GND2 GND1 12 6 NC GND2 11 1000p 7 NC Active Sleep 8 PSV OUT 10 TX IF OUTPUT OUTX 9 1000p Must be adjusting values to result a best impedance matching between BPF filter and this IC. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. --7-- CXA3202AN Design Reference Values Single ended measurement Item Input resistance Input capacitance Output resistance Output capacitance Symbol Rin Cin Rout Cout Conditions (VCC=3.0 V, Ta=27 C) Typ. 10 0.98 6.0 0.92 Unit k pF k pF f=130.38 MHz, Vgctl=1.5 V Notes on Operation 1) This IC is a wideband amplifier with wide gain control range. The decouping capacitors between GND Pin and VCC Pin should be as close to the IC as possible. 2) The resistors connected to Pins 9 and 10 should be as close to the IC as possible. 3) This IC assumes the excellent characteristics when the differential input impedance between Pins 1 and 2 is 500 . Refer to the Measurement Circuit for the external element settings, etc. 4) Pay attention to handling this IC because its electrostatic discharge strength is weak. --8-- CXA3202AN Sensitivity 40 VCC = 3.0V 20 0 10 15 IIP3 VCC = 3.0V Power gain [dB] 5 -20 -40 -60 -80 -100 0 0.5 1 1.5 2 2.5 3 3.5 Vgctl [V] IIP3 [dBm] 0 -5 T = -40C T = 27C T = 85C T = -40C T = 27C T = 85C -10 -15 -60 -40 -20 0 20 40 Power gain [dB] Noise Figure 100 90 80 VCC = 3.0V 4 6 Gain Error from Room Temp VCC = 3.0V Noise figure [dB] 70 60 50 40 30 20 -80 Gain error [dB] T = -40C T = 27C T = 85C -60 -40 -20 0 20 2 0 -2 T = -40C T = 85C -4 -6 -80 -60 -40 -20 0 20 40 Power gain [dB] Power gain [dB] --9-- CXA3202AN Package Outline Unit : mm 16PIN SSOP (PLASTIC) 5.0 0.1 + 0.2 1.25 - 0.1 0.1 16 9 A 4.4 0.1 1 8 0.65 + 0.05 0.15 - 0.02 + 0.1 0.22 - 0.05 0.13 M 0.1 0.1 0 to 10 DETAIL A NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-16P-L01 SSOP016-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.1g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). --10-- 0.5 0.2 6.4 0.2 |
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