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Low Power PLL Tuning Circuits for 3-Wire Bus
The MC44827/27B are tuning circuits for TV and VCR tuner applications. They contain on one chip all the functions required for PLL control of a VCO. The integrated circuits also contain a high frequency prescaler and thus can handle frequencies up to 1.3 GHz. The MC44827 has programmable 512/1024 reference divider while the MC44827B has a fixed reference divider of 1024. The MC44827/27B offer the same features as MC44817/17B but has improved sensitivity performance and reduced power dissipation. The low frequency preamplifier has been removed and the operational amplifier pull-up resistor has been increased to 60 k. The MC44827/27B are controlled via a 3-wire bus. The MC44827/27B have the same functions as the MC44828 which is I2C bus controlled. The MC44827/27B and the MC44828 can be exchanged to allow conversion between 3-wire bus and I2C bus control. The MC44827/27B are manufactured on a single silicon chip using Motorola's high density bipolar process, MOSAICTM (Motorola Oxide Self Aligned Implanted Circuits).
MC44827/27B
LOW-POWER PLL TUNING CIRCUIT
FOR 3-WIRE BUS WITH 1.3 GHz PRESCALER
SEMICONDUCTOR TECHNICAL DATA
* * * * * * * * * * * * * * *
Complete Single Chip System for MPU Control (3-Wire Bus). Data and Clock Inputs are I2C Bus Compatible Divide-by-8 Prescaler Accepts Frequencies up to 1.3 GHz 15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz 3-State Phase/Frequency Comparator Operational Amplifier for Direct Tuning Voltage Output (30 V) Four Integrated PNP Band Buffers can drive up to 40 mA (VCC1 to 14.4 V) Output Options for the Reference Frequency and the Programmable Divider Bus Protocol for 18 or 19 Bit Transmission Extra 34-Bit Protocol for Test and Further Features High Sensitivity Preamplifier Lower Power Consumption, 200 mW Typical Improved Prescaler with Higher Margins for Sensitivity and Temperature Range Lock Detector with Push-Pull Output Space-Saving TSSOP Package ESD Protected to MIL-STD-883C, Method 3015.7 (1.5 k,100 pF)
DA CL XTAL Amp In VTUN VCC2 33 V VCC1 5.0 V
16
1
DTB SUFFIX PLASTIC PACKAGE CASE 948F (TSSOP-16)
PIN CONNECTIONS
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
EN Lock VCC3 12 V B3 B2 B1 B0 Gnd
MOSAIC is a trademark of Motorola, Inc.
ORDERING INFORMATION
HF In Device MC44827DTB MC44827BDTB TA = - 20 to + 80C TSSOP-16 Operating Temperature Range Package (Top View)
(c) Motorola, Inc. 1998
Rev 1
MOTOROLA ANALOG IC DEVICE DATA
1
MC44827/27B
Figure 1. Representative Block Diagram
VTUN VCC1 5.0 V 7 13 12 11 VCC3 12 V 10 14 12 V 60 k (1) Fout Fref 9 Gnd P-On Reset 16 EN 1 DA 2 CL CL 3-Wire Bus Receiver Data RL DTF Test Logic DTB1 B3 B2 B1 Buffers Latches T4 T0 ... T2 T5 DTB2 POR 4 Shift Register 15 Bit 15 Latches A Osc Latches B 3 XTAL TDI Ref Divider 6 Latches Fout B0 Vref Operational Amplifier Phase Comp 4 Amp In 5 VCC2 33 V 6
15 Lock Fref
512/1024 B = 1024 Only
Preamp 1 8 HF In /8 Prescaler Program Divider 15 Bit Fout Latch Control
DTS, EN This device contains 3,204 active transistors.
NOTE: 1. This part may be used with an external pull-up resistor of 20 k to remain compatible with MC44817/17B designed tuners. Pin 6 is left open. The internal pull-up can also be used with an external resistor in parallel.
MAXIMUM RATINGS (TA = 25C, unless otherwise noted.)
Rating Power Supply Voltage (VCC1) Band Buffer "Off" Voltage Band Buffer "On" Current Band Buffer Pin Shorted to Ground or VCC3 (Short Circuit Duration) (Note 1) Operational Amplifier Power Supply Voltage (VCC2) Operational Amplifier Pin Shorted to Ground or VCC2 (Short Circuit Duration) Power Supply Voltage (VCC3) Storage Temperature Operating Temperature Range Band Buffer Operation (Note 2) at 50 mA each Buffer All Buffers "On" Simultaneously Operational Amplifier Output Voltage RF Input Level (80 MHz to 1.3 GHz)
NOTES: 1. At VCC3 = VCC1 to 14.4 V and TA = - 20 to + 80C one buffer "On" only. 2. At VCC3 = VCC1 to 14.4 V and TA = - 20 to + 80C. 3. ESD data available upon request.
Pin 7 10-13 10-13 10-13 6 5 14 - - 10-13 5 8
Value 6.0 14.4 50 Continuous 40 Continuous 14.4 - 65 to +150 - 20 to +80 10 VCC2 1.5
Unit V V mA - V - V C C s V Vrms
2
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
ELECTRICAL CHARACTERISTICS (Parameter Type: A-100% Tested, B-100% Correlation Tested, C-Characterized on Samples,
D-Design Parameter. VCC1 = 5.0 V; VCC2 = 33 V; VCC3 = 12 V; TA = 25C, unless otherwise noted.) Characteristic VCC1 Supply Voltage Range VCC2 Supply Voltage Range VCC3 Supply Voltage Range VCC1 Supply Current (VCC1 = 5.0 V; VCC3 = 12 V) One Buffer "On" VCC2 Supply Current (Output Open) VTUN = 15 V VCC3 Supply Current All Buffers "Off" One Buffer "On" when Open One Buffer "On" at 40 mA Band Buffer Leakage Current when "Off" at 12 V Band Buffer Saturation Voltage when "On" at 30 mA Band Buffer Saturation Voltage when "On" at 40 mA Data/Clock/Enable Current at 0 V Data/Clock/Enable Current at 5.0 V Data/Clock/Enable Input Voltage Low Data/Clock/Enable Input Voltage High Clock Frequency Range Oscillator Frequency Range Operational Amplifier Internal Reference Voltage Operational Amplifier Input Current DC Open Loop Gain Gain Bandwidth Product (CL = 1.0 nF) Vout Low, Sinking 50 A (Note 1) Vout High, Sourcing 3.0 A, VCC2 - Vout Phase Comparator 3-State Current Charge Pump High Current of Phase Comparator Charge Pump Low Current of Phase Comparator
NOTE: 1. Using the internal 60 k pull-up resistor only.
Pin 7 6 14 7 6 14
Min 4.5 25 VCC1 - - - - -
Typ 5.0 32 12 23 0.3 0.15 6.5 46.5 0.01 0.15 0.2 - - - - - 3.2 2.75 0 250 - 80 0.2 0 50 15
Max 5.5 37 14.4 30 1.0 0.3 8.0 50 1.0 0.3 0.5 0 1.0 1.5 - 100 4.05 3.5 15 - - 200 0.5 15 85 30
Unit V V V mA mA mA
Type A A A A A A
10-13 10-13 10-13 1, 2, 16 1, 2, 16 1, 2, 16 1, 2, 16 2 3 - 4 - - 5 5 4 4 4
- - - -10 0 - 3.0 - 3.15 1.8 -15 100 0.3 - - -15 30 10
A V V A A V V kHz MHz V nA - MHz mV V nA A A
A B A A A A A D D A A B C A B A A A
Figure 2. HF (Prescaler Input) Sensitivity Test Circuit
Bus Bus Controller
Figure 3. Typical Prescaler Input Sensitivity
40
16
1
2
14
RF Level (dBm)
VCC1
HF Generator HF Out Gnd 50 Cable 50 1.0 nF 3.9 k 3.9 k 3.9 k 3.9 k Counter In
NOTES: 1. Device is in test mode. B2, B3 are "On" and B0, B1 are "Off". 2. Sensitivity is level of HF generator on 50 load.
MOTOROLA ANALOG IC DEVICE DATA
CCCCCCCC CCCCCCCC CCCCCCCC
7
VCC3
20 0 Guaranteed Operating Area -20 -40 -60 0 200 400 600 800 1000 1200 1400
MC44827/27B
B0 10 B1 11
HF 8
Gnd 9
B2 12
B3 13
RF In (MHz)
3
MC44827/27B
HF INPUT SENSITIVITY AND OVERLOAD CHARACTERISTICS (VCC1 = 5.0 V, TA = 25C.) (See Figure 2.)
Frequency Range DC Bias 80-150 MHz 150-600 MHz 600-950 MHz 950-1300 MHz Pin 8 8 8 8 8 Min - 10 5.0 10 50 Typ 1.6 - - - - Max - 315 315 315 315 Unit V mVrms mVrms mVrms mVrms Type A C C C C
Figure 4. Pin Circuit Schematic
VCC1 132 k DA 1 Data input (3-wire bus) 500 96 k 1/2 VCC1 96 k VCC1 96 k 1/2 VCC1 96 k 132 k 500 16 EN Enable input (3-wire bus)
20 V
20 V
VCC1 132 k 500 CL 2 Clock input (supplied by a microprocessor via 3-wire bus) 96 k 1/2 VCC1 96 k 5.0 k
VCC1
2.0 k 15 Lock Lock detector output 20 V 100 k
20 V
XTAL 3 Crystal oscillator (3.2 MHz or 4.0 MHz)
100 5.0 V 20 V "On"/"Off"
20 V
14 VCC3 Positive supply for integrated band buffers (12 V)
13 B3
2.0 k AMP In 4 Negative input of operation amplifier and phase comparator output 20 V
10 k 20 V "On"/"Off" 60 k 20 V
12 B2
VTUN 5 Operational amplifier output which provides the tuning voltage
100 20 V 20 V 20 V "On"/"Off" 11 B1
Band buffer outputs can drive up to 30 mA (40 mA at 0 to 80C)
VCC2 6 Operational amplifier positive supply (33 V)
20 V 20 V
VCC1 7 Positive supply of the circuit (5.0 V)
5.0 V 5.0 V "On"/"Off" 18 k 2.0 k 1.2 ... 1.8 V
20 V
10 B0
HF In 8 Input to prescaler
2.0 k 9 Gnd Circuit Ground
4
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10,11,12,13 14 15 16 Symbol DA CL XTAL Amp In VTUN VCC2 VCC1 HF In Gnd B0 to B3 VCC3 Lock EN 3-wire bus data input 3-wire bus clock input Crystal oscillator (3.2 MHz or 4 MHz) Negative operational amplifier input and phase comparator output Operational amplifier output which provides the tuning voltage Operational amplifier positive supply (33 V) Positive supply of the circuit (5 V) Asymmetrical HF input Ground PNP Band buffer outputs Positive supply for integrated band buffers (12 V) Lock detector output 3-wire bus enable input Description
Data Format and Bus Receiver The circuit is controlled by a 3-wire bus via Data (DA), Clock (CL), and Enable (EN) inputs. The Data and Clock inputs may be shared with other inputs on the I2C-Bus while the Enable is a separate signal. The circuit is compatible with 18 and 19 bit data transmission and also has a mode for 34 bit transmission for test and additional features. The 3-wire bus receiver receives data for the internal shift register after the positive going edge of the EN-signal. The data is transmitted to the band buffers on the negative going edge of the clock pulse 4 (signal DTB1). 18 and 19 Bit Data Transmission The programmable divider may receive a division ratio coded by a 14 bit (18 bit transmission) or 15 bit (19 bit transmission). The data is transmitted to the programmable divider (latches A) on the negative going edge of clock pulse 19 or on the negative edge of the EN-signal if EN goes down after the 18th clock pulse (signal DTF). If the programmable divider receives a 14 bit byte, its MSB (bit N14) is internally
reset. The reset pulse is generated only if EN goes negative after the 18th clock pulse (signal RL). 34 Bit Data Transmission (For Test and Additional Features) In the test mode, the programmable divider receives a 15 bit byte and the data is transferred to latches A on the negative edge of clock pulse 19 (signal DTF). The information for test is received on clock pulses 20 to 26 and transmitted to the latches on the negative edge of pulse 34 (signal DTB2). These latches have a power-on reset. The power-on reset sets the programmable divider to a counting ratio of 256 or higher and resets the corresponding latches to the test bits T0 to T6 (signal POR). The bus receiver is not disturbed if the data format is wrong. Unused bits are ignored. If for example the Enable signal goes low after clock pulse 9, bits one to four are accepted as valid buffer information and the other bits are ignored. If more than 34 bits are received, bit 35 and the following are ignored.
Figure 5. Bus Timing Diagram
Standard Bus Protocol 18 or 19 Bit Data 1 Clock Buffers Enable 1
B3
4
5
18 19
Counting Ratio
4
5
Bus Protocol for Test and Features 19 20
N6 N5 N4 N3 N2 N1 N0 T6 T5 T4 T3 T2 T1
26 27
T0 X7 X6 X5 X4 X3
33 34
X2 X1 X0
B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7
Buffers
Counting Ratio
Test & Features
Not Used
MOTOROLA ANALOG IC DEVICE DATA
5
MC44827/27B
Definition of Permissible Bus Protocols 1. Bus Protocol for 18 Bit B3 B2 B1 B0 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 Max Counting Ratio 16363 N14 is Reset Internally 2. Bus Protocol for 19 Bit B3 B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 Max Counting Ratio 32767 B0 to B3: Control of Band Buffers N0 to N14: Programmable Divider Counting Ratio N14 = MSB; N0 = LSB Minimum Counting Ratio Always 17 B3 = First Shifted Bit N0 = Last Shifted Bit 3. Bus Protocol for Test and Further Features (34 Bit) B3 B2 B1 B0 N14...N0 Y6 T5 T4 Y3 T2 T1 T0 X7 X6...X1 X0 T0 to T2: Control the Phase Comparator (Note 1) T4: Switches Test Signals to the Buffer Outputs T5: Division Ratio of the Reference Divider B Version T5 = "X" - X0 to X7: Are Random - Y3 and Y6: Are Not Used B3 = First Shifted Bit X0 = Last Shifted Bit Definition of the Bits for Test and Features Bit T0: Defines the Charge Pump Current of the Bit T0: Phase Comparator
T0 = 0 T0 = 1 Pump Current 50 A Typical Pump Current 15 A Typical
Figure 6. Equivalent Circuit of the Integrated Band Buffers
VCC3 12 V 20 ...25 V Protection Gnd IB ISUB 30 mA (40 mA at 0 to 80C) Saturation Voltage 0.15 V Typical 0.3 V Max
"On"/"Off" Out B0...B3
NOTES: IB + ISUB = 5.5 mA Typical
IB = Base Current ISUB = Substrate Current of PNP
Bit T5: Defines the Division Ratio of the Reference Bit T5: Divider
T5 = 0 T5 = 1 Division Ratio 512 Division Ratio 1024
NOTE: The division ratio of the reference divider can only be programmed in the 34 bit bus protocol. In the standard bus protocol the division ratio is 512. (The power-up reset POR sets the division ratio to 512). On "B-version", T5 = "X". Division ratio 1024 is fixed.
OPERATING DESCRIPTION
Introduction A representative block diagram and typical system application are shown in Figures 1 and 8. A discussion of the features and function of each of the internal blocks is given. The Programmable Divider The programmable divider is a presettable down counter. When it has counted to zero it takes its required division ratio out of the latches B. Latches B are loaded from latches A by means of signal TDI which is synchronous to the programmable divider output signal. Since latches A receive the data asynchronously with the programmable divider; this double latch scheme is needed to assure correct data transfer to the counter. The division ratio definition is given by: N = 16384 x N14 + 8132 x N13 + ... + 4 x N2 + 2 x N1 + N0 Maximum Ratio 32767 (16363 in case of 18 bit bus protocol) Minimum Ratio 17 N0 ... N14 are the different bits for frequency information. At power-on the whole bus receiver is reset and the programmable divider is set to a counting ratio of N = 256 or higher. The Prescaler The divide by 8 prescaler has a preamplifier which guarantees high input sensitivity. The Phase Comparator The phase comparator is both phase and frequency sensitive and has very low output leakage current in the high impedance state. Lock Detector The lock-detector output is low in lock. The output goes immediately high when an unlock condition is detected. The output goes low again when the loop is in lock during a complete period of the reference frequency.
Bits T1 and T2: Define the Digital Function of the Phase Bits T1 and T2: Comparator
T2 0 0 1 1 T1 0 1 0 1 State 1 2 3 4 Output Function of Phase Comparator Normal Operation High Impedance (3-State) Upper Source "On", Lower Source "Off" Lower Source "On", Upper Source "Off"
NOTE: 1. The phase comparator pulls high if the input frequency is too high and it pulls low when the input frequency is too low. (Inversion by Operational Amplifier) The phase comparator generates a fixed duration offset pulse for each comparison pulse. This guarantees operation in the linear region. The offset pulse is a positive current pulse (upper source).
Bit T4: Switches the Internal Frequencies Fref and Bit T4: FBY2 to the Buffer Outputs (B2, B3)
T4 = 0 T4 = 1
NOTE:
Normal Operation Fref Switched to Buffer Output B2 FBY2 Switched to Buffer Output B3
Bits B2 and B3 have to be one in this case. Fref is the reference frequency. FBY2 is the output frequency of the programmable divider, divided by two.
6
MOTOROLA ANALOG IC DEVICE DATA
MC44827/27B
Figure 7. Equivalent Circuit of the Lock Output
VCC1 5.0 V 200 A Typical 2.0 k Lock "On"/"Off" 5.0 k 100 k 25 V Protection
The Oscillator The oscillator uses a 3.2 or a 4.0 MHz crystal tied to ground in series with a capacitor. The crystal operates in the series resonance mode. The voltage at Pin 3 has low amplitude and low harmonic distortion. Power Dissipation The typical power dissipation of the circuit is about 200 mW (VTUN = 15 V with internal pull-up of 60 k, one buffer "On" at 30 mA). It is calculated with the following formula: PD
"Off"/"On"
+
V
V
CC1 xI
xI
CC1
V ) VCC2 -kTUN 60 V sat(buffer) xI
xV
CC2
The Operational Amplifier The operational amplifier is designed for very low noise, low input bias current and high power supply rejection. The positive input is biased internally. The operational amplifier needs 28.5 V supply (VCC2) as minimum voltage for a guaranteed maximum tuning voltage of 28 V. Figure 8 shows a possible filter arrangement. The component values depend very much on the application (tuner characteristic, reference frequency, etc.).
)
CC3
CC3
)
out(buffer)
Example: (5 x 23)
- ) 32 60 15 x 32 ) (12 x 6.5) ) (0.15 x 30) + 206.5
Figure 8. Typical Tuner Application
IF UHF VHF B III 5.0 V 7 Mixer B. P. Filter 1.0 nF Fosc 8 13 B3 12 B2 11 B1 10 B0 Bus Rec Program Divider External Switching
14 12 V VCC3 2 1 16 Osc & 3 Ref Div Phase Comp 15 Lock CL DA EN
Antenna Filter
MC44827/27B
/8 Pres
12 pF 3.2/4.0 MHz
Oscillator
Gnd 9 6 5 120 k 330 p (Note 1) 33 V 18 nF 8.2 nF
Vref 4
VTUN AGC
NOTE: 1. 330 pF minimum is required for stability.
MOTOROLA ANALOG IC DEVICE DATA
7
MC44827/27B
OUTLINE DIMENSIONS
DTB SUFFIX PLASTIC PACKAGE CASE 948F-01 (TSSOP-16) ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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SECTION N-N
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MC44827/D MOTOROLA ANALOG IC DEVICE DATA

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