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LH5P8129
FEATURES * 131,072 x 8 bit organization * Access times (MAX.): 60/80/100 ns * Cycle times (MIN.): 100/130/160 ns * Single +5 V power supply * Pin compatible with 1M standard SRAM * Power consumption: Operating: 572/385/275 mW (MAX.) Standby (TTL level): 5.5 mW (MAX.) Standby (CMOS level): 1.1 mW (MAX.) * TTL compatible I/O * Available for auto-refresh and self-refresh modes * 512 refresh cycles/8 ms * Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 8 x 20 mm2 TSOP (Type I) DESCRIPTION
The LH5P8129 is a 1M bit Pseudo-Static RAM organized as 131,072 x 8 bits. It is fabricated using silicon-gate CMOS process technology. A PSRAM uses on-chip refresh circuitry with a DRAM memory cell for pseudo static operation which eliminates external clock inputs, while considering the pinout compatibility with industry standard SRAMs. The advantage is the cost savings realized with the lower cost PSRAM. The LH5P8129 PSRAM has a built-in oscillator, which makes it easy to refresh memories without external clocks.
CMOS 1M (128K x 8) CS-Control Pseudo-Static RAM
PIN CONNECTIONS
32-PIN DIP 32-PIN SOP RFSH A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CS R/W A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
5P8129-1
TOP VIEW
Figure 1. Pin Connections for DIP and SOP Packages
32-PIN TSOP (Type I) TOP VIEW
A11 A9 A8 A13 R/W CS A15 VCC RFSH A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
NOTE: Reverse bend available on request.
5P8129-2
Figure 2. Pin Connections for TSOP Package
1
LH5P8129
CMOS 1M (128K x 8) Pseudo-Static RAM
16 GND 32 VCC A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 A7 A8 A9 6 5 27 26 ROW ADDRESS BUFFER EXT/INT ADDRESS MUX ROW DECODER SENSE AMPS I/O SELECTOR DATA IN BUFFER 13 I/O0 14 I/O1 15 I/O2 17 I/O3 18 I/O4 19 I/O5 20 I/O6 DATA OUT BUFFER 21 I/O7
VBB GENERATOR
COLUMN ADDRESS BUFFER
COLUMN DECODER
A10 23 A11 25 A12 4 A13 28 A14 3 A15 31 A16 2
REFRESH ADDRESS COUNTER
MEMORY ARRAY
CE 22 CS 30
CLOCK GENERATOR
REFRESH CONTROLLER RFSH 1 OE 24 R/W 29
REFRESH TIMER
NOTE: Pin numbers apply to 32-pin DIP or SOP.
5P8129-3
Figure 3. LH5P8129 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A16 R/W OE CE
Address input Read/Write input Output Enable input Chip Enable input
CS RFSH I/O0 - I/O7
Chip Select input Refresh input Data input/output
2
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8129
TRUTH TABLE
CE CS OE R/W RFSH A0 - A16 I/O1 - I/O8 MODE
L L L L H H
H H H L X X
L X H X X X
H L H X X X
X X X X L H
VX VX VY X X X
DOUT DIN High-Z High-Z High-Z High-Z
Read Write CE only refresh CS standby Auto/Self refresh Standby
NOTES: H = High at VIN = VCC + 0.3 V to VIH (MIN.) L = Low at VIN = VIL (MAX.) to -1.0 V X = Don't care at VCC + 0.3 V to -1.0 V VX = A0-A16 address input when CE = L, then Don't Care VY = A0-A8 address input when CE = L, then Don't Care, and A9-A16 address = Don't Care at VCC + 0.3 V to -1.0 V
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Applied voltage on any pins Output short circuit current Power dissipation Operating temperature Storage temperature
VT IO PD Topr Tstg
-1.0 to +7.0 50 600 0 to +70 -65 to +150
V mA mW C C
1
NOTE: 1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage Input voltage
VCC GND VIH VIL
4.5 0 2.4 -1.0
5.0 0
5.5 0 VCC + 0.3 0.8
V V V V
CAPACITANCE (TA = 0 to +70C, f = 1 MHz, VCC = 5.0 V 10%)
PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT
A0 - A16 Input capacitance R/W, OE CE, CS RFSH Input/output capacitance I/O1 - I/O7
CIN1 CIN2 CIN3 CIN4 COUT1
8 5 5 5 10
pF pF pF pF pF
3
LH5P8129
CMOS 1M (128K x 8) Pseudo-Static RAM
DC CHARACTERISTICS (TA = 0 to +70C, VCC = 5.0 V 10%)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
LH5P8129-60 Operating current LH5P8129-80 LH5P8129-10 Standby current Self-refresh average current Input leakage current I/O leakage current Output HIGH voltage Output LOW voltage
NOTES: 1. Specified values are with outputs open. 2. I CC1 depends on the cycle time 3. CE = VIH, RFSH = VIH 4. CE = VCC - 0.2 V, RFSH = VCC - 0.2 V 5. CE = VIH, RFSH = VIL 6. CE = VCC - 0.2 V, RFSH = 0.2 V
ICC1
tRC = tRC (MIN.)
104 70 50 1 0.2 1 0.2
mA
1, 2 1, 3 1, 4 1, 5 1, 6
TTL Input CMOS Input TTL Input CMOS Input
ICC2 ICC3 ILI ILO VOH VOL 0 V VIN 6.5 V 0 V except on test pins 0 V VOUT VCC + 0.3 V Output in high-impedance state IOUT = -1 mA IOUT = 4 mA -10 -10 2.4
mA mA A A V
10 10
0.4
V
4
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8129
AC ELECTRICAL CHARACTERISTICS 1,2,3 (TA = 0 to +70C, VCC = 5.0 V 10%)
PARAMETER SYMBOL LH5P8129-60 MIN. MAX. LH5P8129-80 MIN. MAX. LH5P8129-10 MIN. MAX. UNIT NOTE
Random read, write cycle time Read modify write cycle time CE pulse width CE precharge time CS setup time CS hold time Address setup time Address hold time Read command setup time Read command hold time CE access time OE access time CE to output in Low-Z OE to output in Low-Z Output enable from end of write Chip disable to output in High-Z Output disable to output in High-Z Write enable to output in High-Z OE setup time OE hold time Write command pulse width Write command setup time Write command hold time Data setup time from write Data setup time from CE Data hold time from write Data hold time from CE Transition time (rise and fall) Refresh time interval Refresh command hold time Auto refresh cycle time Refresh delay time from CE Refresh pulse width (Auto refresh) Refresh precharge time (Auto refresh) Refresh pulse width (Self refresh) CE delay time from refresh precharge (Self refresh)
tRC tRMW tCE tP tCSS tCSH tAS tAH tRCS tRCH tCEA tOEA tCLZ tOLZ tWLZ tCHZ tOHZ tWHZ tOES tOEH tWP tWCS tWCH tDSW tDSC tDHW tDHC tT tREF tRHC tFC tRFD tFAP tFP tFAS tFRS
100 165 60 40 0 15 0 15 0 0
10,000
130 195 80 40 0 20 0 20 0 0
10,000
160 235 100 50 0 25 0 25 0 0
10,000
60 25 20 0 0 20 20 20 0 10 30 30 40 25 25 0 0 3 15 100 30 30 30 8,000 140 8,000 0 10 30 30 50 30 30 0 0 3 15 130 40 30 30 8,000 160 20 0 0
80 30 20 0 0 25 25 25 0 10 30 30 60 35 35 0 0 3 15 160 50 8,000 30 30 8,000 190
100 35
30 30 30
35 8
35 8
35 8
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns
4 4
5 5
6 6 6 6
8,000
NOTES: 1. In order to initialize the circuit, an initial pause of 100 s with CE = VIH, RFSH = VIH after power-up, followed by at least 8 dummy cycles. 2. AC characteristics are measured at t T = 5 ns. 3. AC characteristics are measured at the following condition (see figure at right). 4. Measured with a load equivalent to 2TTL + 100 pF. 5. Address is latched at the negative edge of CE. 6. Data is latched at the positive edge of R/W or at the positive edge of CE.
INPUT
2.4 V 0.8 V
2.6 V 0.6 V 2.2 V 0.8 V
OUTPUT
5P8129-4
Figure 4. AC Characteristics
5
LH5P8129
CMOS 1M (128K x 8) Pseudo-Static RAM
tRC tP VIH VIL tCSS tCSH tCE
CE
CS
VIH VIL tAS tAH
A0 - A16
VIH VIL
ADDRESS INPUT
OE
VIH VIL tRCS VIH VIL tOEA tCEA tOLZ tCLZ VOH VOL tFP tFRS VIH VIL
5P8129-5
tRCH
R/W
tOHZ
tCHZ
I/O0 - I/O7
VALID-DATA OUTPUT
tRHC
tRFD
RFSH
Figure 5. Read Cycle
6
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8129
tRC tP VIH VIL tCSS tCSH tCE
CE
CS
VIH VIL tAS tAH
A0 - A16
VIH VIL tOES VIH VIL
ADDRESS INPUT
tOEH
OE
tWCS tWCH tWP
R/W
VIH VIL tDSW tDSC VOH VOL tFP tFRS VIH VIL
5P8129-6
tDHW tDHC
I/O0 - I/O7
DATA INPUT
tRHC
tRFD
RFSH
Figure 6. Write Cycle 1 (OE = HIGH)
7
LH5P8129
CMOS 1M (128K x 8) Pseudo-Static RAM
tRC tP VIH VIL tCSS tCSH tCE
CE
CS
VIH VIL tAS tAH
A0 - A16
VIH VIL VIH VIL
ADDRESS INPUT
OE
tWCS tWCH tWP
R/W
VIH VIL tDSW tDSC VIH VIL tWHZ tDHW tDHC
DIN
VALID-DATA INPUT
tOLZ tWLZ tCHZ
I/O0 - I/O7
tCLZ V DOUT VOH OL tFP tFRS VIH VIL tRHC
tOHZ
tRFD
RFSH
5P8129-7
Figure 7. Write Cycle 2 (OE Clock)
8
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8129
tRC tP VIH VIL tCSS tCSH tCE
CE
CS
VIH VIL tAS tAH
A0 - A16 OE
VIH VIL VIH VIL
ADDRESS INPUT
tWCS tWCH tWP
R/W
VIH VIL tDSW tDSC VIH VIL tWHZ tDHW tDHC
DIN
VALID-DATA INPUT
tCHZ tWLZ
I/O0 - I/O7
tCLZ VOH VOL tFP tFRS VIH VIL tRHC
DOUT
tRFD
RFSH
5P8129-8
Figure 8. Write Cycle 3 (OE = LOW)
9
LH5P8129
CMOS 1M (128K x 8) Pseudo-Static RAM
tRMW tP VIH VIL tCSS tCSH
CE
CS
VIH VIL tAS tAH
A0 - A16
VIH VIL VIH VIL
ADDRESS INPUT
OE
tWCS tRCS tWP R/W VIH VIL tOEA tCEA VIH VIL tOLZ I/O0 - I/O7 tCLZ VOH VOL tFP tFRS VIH VIL
5P8129-9
tDSW tDSC
tDHW tDHC
DIN
DATA INPUT
tWHZ tOHZ tWLZ
tCHZ
DOUT
DATA OUTPUT
tRHC
tRFD
RFSH
Figure 9. Read-Modify-Write Cycle
10
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8129
tRC tP VIH VIL tCSS VIH VIL tAS tAH tCSH tCE
CE
CS
A0 - A8
VIH VIL tOES
ADDRESS INPUT
tOEH
OE
VIH VIL tRCS tRCH
R/W I/O0 - I/O7
VIH VIL VOH VOL tFP tFRS VIH VIL
5P8129-10
HIGH-Z
tRFD tRHC
RFSH
NOTE: A9 - A16 = Don't Care
Figure 10. CE Only Refresh
CE
VIH VIL tRFD tFP tFAP tFC tFP tFAP tFC tFP tRHC
RFSH
VIH VIL VOH VOL HIGH-Z
I/O0 - I/O7
NOTE: CS, OE, R/W, A0 -A16 = Don't Care
5P8129-11
Figure 11. Auto Refresh Cycle
11
LH5P8129
CMOS 1M (128K x 8) Pseudo-Static RAM
CE
VIH VIL tRFD tFP VIH VIL VOH VOL HIGH-Z tFAS tFRS tRHC
RFSH I/O0 - I/O7
NOTE: CS, OE, R/W, A0 - A16 = Don't Care
5P8129-12
Figure 12. Self Refresh Cycle
tRC tP tCE
CE
VIH VIL tCSS tCSH
CS
VIH VIL
5P8129-13
NOTE: OE, R/W, RFSH, A0 - A16 = Don't Care
Figure 13. CS Standby Mode
12
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8129
PACKAGE DIAGRAMS
32DIP (DIP032-P-0600)
32 17
DETAIL
13.45 [0.530] 12.95 [0.510]
1 41.30 [1.626] 40.70 [1.602]
16 0.30 [0.012] 0.20 [0.008]
0 TO 15
4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT
15.24 [0.600] TYP.
DIMENSIONS IN MM [INCHES]
32DIP
32-pin, 600-mil DIP
32SOP (SOP032-P-0525)
1.27 [0.050] TYP. 1.40 [0.055] 17
0.50 [0.020] 0.30 [0.012]
32
11.50 [0.453] 11.10 [0.437]
14.50 [0.571] 13.70 [0.539]
12.50 [0.492]
1 20.80 [0.819] 20.40 [0.803]
16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
32SOP
32-pin, 525-mil SOP
13
LH5P8129
CMOS 1M (128K x 8) Pseudo-Static RAM
32TSOP (Type I) (TSOP032-P-0820)
0.30 [0.012] 0.10 [0.004] 32 0.50 [0.020] TYP. 17
18.60 [0.732] 18.20 [0.717]
20.30 [0.799] 19.70 [0.776]
19.00 [0.748]
1 8.20 [0.323] 7.80 [0.307]
16 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000]
0.15 [0.006]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
32TSOP
32-pin, 8 x 20 mm2 TSOP (Type I)
ORDERING INFORMATION
LH5P8129 Device Type X Package - ## Speed 60 60 80 80 Access Time (ns) 10 100 Blank 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) T 32-pin, 8 x 20 mm2 TSOP (Type I) (TSOP032-P-0820) TR 32-pin, 8 x 20 mm2 TSOP (Type I) Reverse bend (TSOP032-P-0820) CMOS 1M (128K x 8) Pseudo-Static RAM Example: LH5P8129N-60 (CMOS 1M (128K x 8) Pseudo-Static RAM, 60 ns, 32-pin, 525-mil SOP)
5P8129-14
14

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