| PART |
Description |
Maker |
| LTC2400 |
24-Bit uPower No Latency ADC in SO-8
24-Bit Power No Latency Delta-SigmaADC in SO-8
|
Linear Technology Corporation
|
| 89HPES16T4AG2 |
Low latency cut-through switch architecture
|
Integrated Device Techn...
|
| LTC2410 LTC2410CGN 2410I LTC2410C LTC2410I LTC2410 |
From old datasheet system
24-Bit No Latency ADC with Differential Input and Differential Reference
24 Bit No Latency ADC
|
Linear Technology
|
| LTC2430 LTC2431 LTC2431CMS LTC2430CGN LTC2431IMS L |
20-Bit No Latency Delta-Sigma ADCs with Differential Input and Differential Reference
20-Bit No Latency Delta Sigma with Differential Input, 50/60Hz Rejection, SSOP-16
20-Bit No Latency Delta Sigma with Differential Input, 50/60Hz Rejection, MS10
|
LINER[Linear Technology]
|
| LTC242409 LTC2424CG LTC2428IGTRPBF |
4-/8-Channel 20-Bit mPower No Latency DSTM ADCs
4-/8-Channel 20-Bit µPower No Latency Delta-Sigma ADC; Package: SSOP; No of Pins: 28; Temperature Range: -40°C to 85°C 8-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
|
Linear Technology, Corp.
|
| CY7C1165V18 CY7C1163V18 CY7C1161V18 CY7C1176V18 CY |
18-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 2M X 9 QDR SRAM, 0.45 ns, PBGA165
18-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 18兆位的国防评估报告⑩- II SRAM字突发架构（2.5周期读写延迟
18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| MB86977 |
IP Packet
|
Fujitsu
|
| MB86977 MB86977PFV-G-BND |
IP PACKET FORWARDING ENGINE
|
Fujitsu Media Devices Limited
|
| RPC-UHF |
Radio Packet Controller
|
http://
|
| MT90883 MT9088IG MT90880 MT90880B MT90880B_IG MT90 |
TDM to Packet Processors
|
ZARLINK[Zarlink Semiconductor Inc]
|
| AS95L2100 |
Resilient Packet Ring Controllers?
|
ALSC
|
