PART |
Description |
Maker |
NB6L295MNG NB6L295MNTXG |
LVPECL Dual Programmable Delay ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, QCC24 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs
|
ON Semiconductor
|
UPD424400LLA-A80 UPD42S4400LLA-A80 UPD42S4400LGS-A |
2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer Clock Synthesizer with Differential SRC and CPU Outputs Clock Generator for Intel® Grantsdale Chipset x4 Fast Page Mode DRAM x4快速页面模式的DRAM
|
Vishay Intertechnology, Inc.
|
AD8129 AD8130 AD8129ARM-REEL72 AD8130ARM-REEL72 AD |
Low-Cost 200MHz Differential Receiver Amplifier IC,DIFFERENTIAL AMPLIFIER,SINGLE,SOP,8PIN,PLASTIC From old datasheet system Low-Cost High-Speed Differential Receiver and Driver Low-Cost 270 MHz Differential Receiver Amplifiers 低成70 MHz的差分接收器放大 Low-Cost 270 MHz Differential Receiver Amplifiers SPECIALTY ANALOG CIRCUIT, PDSO8
|
AD[Analog Devices] adi Analog Devices, Inc.
|
1505 1505-50B 1505-50G 1505-5B 1505-50A 1505-50C 1 |
Delay 300 /-15 ns, 5-TAP SIP delay line Td/Tr=3 Delay 100 /-5 ns, 5-TAP SIP delay line Td/Tr=3 Delay 60 /-3 ns, 5-TAP SIP delay line Td/Tr=3 Delay 30 /-2 ns, 5-TAP SIP delay line Td/Tr=3 Fixed 5-tap passive SIP delay line PASSIVE DELAY LINE, TRUE OUTPUT, PSIP7 Delay 70 /-3.5 ns, 5-TAP SIP delay line Td/Tr=3 Delay 75 /-3.5 ns, 5-TAP SIP delay line Td/Tr=3 Delay 90 /-5 ns, 5-TAP SIP delay line Td/Tr=3 Delay 40 /-2.5 ns, 5-TAP SIP delay line Td/Tr=3 Delay 50 /-3 ns, 5-TAP SIP delay line Td/Tr=3 Delay 20 /-1.5 ns, 5-TAP SIP delay line Td/Tr=3 Delay 200 /-10 ns, 5-TAP SIP delay line Td/Tr=3 Delay 5 /-1 ns, 5-TAP SIP delay line Td/Tr=3
|
DATA DELAY DEVICES INC
|
AK8122E AK8122V |
Differential Zero Delay Clock Buffer
|
Asahi Kasei Microsystems Asahi Kasei Microsystem...
|
ICS8705BYLF ICS8705BYLFT ICS8705BYT ICS8705BY ICS8 |
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
|
ICST[Integrated Circuit Systems]
|
ICS8634-01 |
Low Skew, 1-to-5, Differential-to- LVPECL Zero Delay Buffer From old datasheet system
|
ICS
|
NB6L295MMNTXG NB6L295MMNG |
2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs
|
ON Semiconductor
|
3D7010SERIES 3D7010S-80 3D7010S-90 3D7010S-400 |
300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit 整体0 - TAP在固定延迟线 MONOLITHIC 10-TAP FIXED DELAY LINE Delay 8 /-1.5 ns, monolithic 10-TAP fixed delay line Delay 9 /-1.7 ns, monolithic 10-TAP fixed delay line Delay 40 /-4 ns, monolithic 10-TAP fixed delay line
|
Interpower, Corp. Data Delay Devices Inc
|
MN95029 |
375 MHz Delay Line 2.25 MHz Bandwidth
|
API Technologies Corp
|