| PART |
Description |
Maker |
| SL6679TP1N SL6679KG MITELNETWORKSCORPORATION-SL667 |
Direct Conversion FSK Data Receiver
2-7V; direct conversion FSK data receiver. For pagers, including credit card, PCMCIA and watch pagers, low data rate receivers
|
Mitel Semiconductor
|
| HDMP-1034 HDMP-1032 |
1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(带CIMT编码译码器和变量数据速率.4 GBd 接收
1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(带CIMT编码译码器和变量数据速率.4 GBd 传送器)
1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
|
Agilent (Hewlett-Packard)
|
| 106414-1401 |
QSFP to MPO Quad Data Rate PSM4 Active Optical Cable, 40 Gbps Data Rate, 4dB Loss Budget, Cable Length 1.0m
|
Molex Electronics Ltd.
|
| 1064101200 |
QSFP to QSFP Quad Data Rate PSM4 Active Optical Cable, 40 Gbps Data Rate
|
Molex Electronics Ltd.
|
| K4D26323AA-GL |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
| HA7-2840883 FN3594 HA1-2840_883 HA1-2840883 HA7-28 |
From old datasheet system
Very High Slew Rate Wideband Operational Amplifier
Very High Slew Rate/ Wideband Operational Amplifier
Very High Slew Rate,
Wideband Operational Amplifier(高转换率、宽带运算放大器)
Very High Slew Rate, Wideband Operational Amplifier 甚高摆率，宽带运算放大器
Very High Slew Rate, Wideband Operational Amplifier OP-AMP, 6000 uV OFFSET-MAX, 500 MHz BAND WIDTH, CDIP14
|
INTERSIL[Intersil Corporation]
Intersil, Corp.
|
| EM423M3284LBA-8FE EM424M3284LBA-75FE EM424M3284LBA |
512Mb (4MBank2) Double DATA RATE SDRAM
512Mb (4MBank32) Double DATA RATE SDRAM
512Mb (4M4Bank2) Double DATA RATE SDRAM
|
Electronic Theatre Controls, Inc.
|
| GS8170DD36C-333 GS8170DD36C-250 GS8170DD36C-300 GS |
18Mb x2Lp CMOS I/O Double Data Rate SigmaRAM 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209
18Mb 1x2Lp CMOS I/O Double Data Rate SigmaRAM 35.71x2Lp的CMOS的I / O双数据速率SigmaRAM
|
GSI Technology, Inc.
|
| M13S2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M13S2561616A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| ADXRS646-EP |
High Stability, Low Noise Vibration Rejecting Yaw Rate Gyroscope Data Sheet (Rev 0, 10/2012)
|
Analog Devices
|
