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Cypress
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| Part No. |
PLDC20RA10 C20RA10
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| OCR Text |
...
13 OE
14 I/O9
15 I/O8
16 I/O7
17 I/O6
18 I/O5
19 I/O4
20 I/O3
21 I/O2
22 I/O1
23 I/O0 RA10-1
24 VCC
Cyp...Macrocell Architecture
Figure 1 illustrates the architecture of the 20RA10 macrocell. The cell dedi... |
| Description |
Reprogrammable Asynchronous CMOS Logic Device
From old datasheet system
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| File Size |
372.06K /
13 Page |
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it Online |
Download Datasheet
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Xilinx
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| Part No. |
XC9536XV DS053 XC9536XV-SERIES
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| OCR Text |
...g conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the ...macrocell p-term allocator delay Slew-rate limited delay Time Adders
3.0 3.0 Advance Information
... |
| Description |
High-performance CPLD
From old datasheet system
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| File Size |
59.60K /
8 Page |
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it Online |
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N/A
Altera Corp
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| Part No. |
EPM7032SLC44-10 EPM7128ELC84-20 EPM7128ELC84-15 EPM7128ELC84-10P EPM7128ELC84-10 EPM7064SLI44-7
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| OCR Text |
...3 6 90.9
EPM7256E
5,000 256 16 164 12 7 3 6 90.9
Altera Corporation
A-DS-M7000-6.3
1
MAX 7000 Programmable Logic Device Family...macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable pow... |
| Description |
MAX 7000 Programmable Logic Device
COMPLEX-EEPLD,128-CELL,10NS PROP DELAY,LDCC,84PIN,PLASTIC
COMPLEX-EEPLD,128-CELL,15NS PROP DELAY,LDCC,84PIN,PLASTIC
COMPLEX-EEPLD,128-CELL,20NS PROP DELAY,LDCC,84PIN,PLASTIC
COMPLEX-EEPLD,32-CELL,10NS PROP DELAY,LDCC,44PIN,PLASTIC
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| File Size |
436.37K /
62 Page |
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it Online |
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Altera
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| Part No. |
EPM7128SLC84-10
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| OCR Text |
...3 6 90.9
EPM7256E
5,000 256 16 164 12 7 3 6 90.9
Altera Corporation
DS-MAX7000-6.6
1
MAX 7000 Programmable Logic Device Family...macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable pow... |
| Description |
IC,COMPLEX-EEPLD,128-CELL,10NS PROP DELAY,LDCC,84PIN,PLASTIC
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| File Size |
473.32K /
66 Page |
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it Online |
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lattice
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| Part No. |
LC4128V-10T100I
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| OCR Text |
...s consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architectu... |
| Description |
IC,COMPLEX-EEPLD,128-CELL,10.5NS PROP DELAY,QFP,100PIN,PLASTIC
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| File Size |
264.92K /
83 Page |
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it Online |
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Lattice Semiconductor Corp
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| Part No. |
LC4256 LC4384V75T176C LC4512 LC4128 LC4064 LC4032
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| OCR Text |
...s consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architectu... |
| Description |
IC,COMPLEX-EEPLD,256-CELL,3.8NS PROP DELAY,QFP,100PIN,PLASTIC
IC,COMPLEX-EEPLD,384-CELL,10NS PROP DELAY,QFP,176PIN,PLASTIC
IC,COMPLEX-EEPLD,512-CELL,4.5NS PROP DELAY,QFP,176PIN,PLASTIC
System Programmable Super Fast High Density PLDs
IC,COMPLEX-EEPLD,64-CELL,3.2NS PROP DELAY,QFP,100PIN,PLASTIC
IC,COMPLEX-EEPLD,32-CELL,3.2NS PROP DELAY,TQFP,48PIN,PLASTIC
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| File Size |
740.67K /
91 Page |
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it Online |
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Xilinx
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| Part No. |
XC95144XL 95144XL XC95144XL-SERIES
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| OCR Text |
...g conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the ...Macrocell TQ100 TQ144 CS144 Order Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 ... |
| Description |
High Performance CPLD
From old datasheet system
Preliminary Product Specification
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| File Size |
78.77K /
9 Page |
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it Online |
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Price and Availability
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