| |
|
 |
ST Microelectronics
|
| Part No. |
STE10/100
|
| OCR Text |
...op the current transaction Data parity error detected, driven by the device receiving data Address parity error parity. Even parity computed for AD[31:0] and C/BE[3:0]; master drives PAR for address and write data phase, target drives PAR f... |
| Description |
PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V
|
| File Size |
405.66K /
66 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
ST Microelectronics
|
| Part No. |
STE10/100A
|
| OCR Text |
...op the current transaction Data parity error detected, driven by the device receiving data Address parity error parity. Even parity computed for AD[31:0] and C/BE[3:0]; master drives PAR for address and write data phase, target drives PAR f... |
| Description |
PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 3.3V
|
| File Size |
405.66K /
66 Page |
View
it Online |
Download Datasheet |
| |
|
|
Micron Technology, Inc.
|
| Part No. |
MT58L128L32D1
|
| OCR Text |
...causes all bytes to be written. parity bits are only available on the x18 and x36 versions. this device incorporates an additional pipelined enable register which delays turning off the output buffer an additional cycle when a deselect is e... |
| Description |
128K x 32锛?.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb锛?.3V杈??/杈??锛??姘寸嚎寮????惊???娑???╋??????????瀛???ī
|
| File Size |
418.97K /
24 Page |
View
it Online |
Download Datasheet |
| |
|
|
CYPRESS SEMICONDUCTOR CORP
|
| Part No. |
MT58L128L32D1F-6
|
| OCR Text |
...causes all bytes to be written. parity bits are only available on the x18 and x36 versions. this device incorporates an additional pipelined enable register which delays turning off the output buffer an additional cycle when a deselect is e... |
| Description |
128K X 32 CACHE SRAM, 3.5 ns, PBGA165
|
| File Size |
437.01K /
26 Page |
View
it Online |
Download Datasheet |
| |
|
|
CYPRESS SEMICONDUCTOR CORP
|
| Part No. |
MT58L128L32D1F-5
|
| OCR Text |
...causes all bytes to be written. parity bits are only available on the x18 and x36 versions. this device incorporates an additional pipelined enable register which delays turning off the output buffer an additional cycle when a deselect is e... |
| Description |
128K X 32 STANDARD SRAM, 2.8 ns, PBGA165
|
| File Size |
429.23K /
25 Page |
View
it Online |
Download Datasheet |
| |
|
|
IDT
|
| Part No. |
IDT79RC64474 IDT79RC64475
|
| OCR Text |
...ed, physically tagged, and word parity protected. because this cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access, further increasing performance by allowing both operations to o... |
| Description |
(IDT79RC64V474 / IDT79RC64V475) 64-Bit Microprocessor
|
| File Size |
418.88K /
25 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
