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Integrated Device Techn...
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| Part No. |
8T79S838-08NLGI 8T79S838-08NLGI8 IDT8T79S838-08I
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| OCR Text |
... nqd1, qd1 output differen tial bank d output pair. 13, 14 nqd0, qd0 output differen tial bank d output pair. 15, 26 v ee power negative power supply pins. 17, 18 nqc1, qc1 output diff erential bank c output pair. l vpecl or lvds interface ... |
| Description |
1-to-8 Differential to Universal Output Fanout Buffer
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| File Size |
401.04K /
25 Page |
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Alliance Semiconductor ...
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| Part No. |
AS4C32M16SM AS4C32M16SM-7TIN
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| OCR Text |
... row addressing 8k a [12:0] bank addressing 4 ba [1:0] column addressing 1k a [9:0]
as4c 32m16sm confidential 3 | p a g e r e v 1 . 0 , j u l y 2014 general description the 512mb sdram is a high - spe... |
| Description |
PC133-compliant
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| File Size |
2,741.77K /
73 Page |
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it Online |
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Alliance Semiconductor ...
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| Part No. |
AS4C32M16MD1 AS4C32M16MD1-5BCN
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| OCR Text |
...ver, internal operations (bank active, burst operations, etc.) are held. ras#, cas#, and we# (input pins) these pins define operating commands (read, write, etc.) depending on the co... |
| Description |
Four internal banks for concurrent operation
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| File Size |
4,183.82K /
75 Page |
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Alliance Semiconductor ...
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| Part No. |
AS4C32M16MD1A AS4C32M16MD1A-5BCN
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| OCR Text |
...amic ram. each 134,217,728 bits bank is organized as 8,192 rows by 1024 columns by 16 bits fabricated with alliance memory?s high perfo rmance cmos technology. this device uses a double data rate architecture to achieve hi gh-... |
| Description |
60 ball FBGA PACKAGE
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| File Size |
2,393.14K /
53 Page |
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Alliance Semiconductor ...
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| Part No. |
AS4C32M16D2
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| OCR Text |
...nternally configured as a quad bank dram, 4 banks x 8mb addresses x 16 i/os the device is designed to comply with ddr2 dram key features such as posted cas# with additive latency, write latency = read latency -1, off-chip driver (ocd) i... |
| Description |
512M (32M x 16 bit) DDRII Synchronous DRAM
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| File Size |
1,490.56K /
70 Page |
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Alliance Semiconductor ...
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| Part No. |
AS4C32M16D2A-25BCN
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| OCR Text |
...nternally configured as a quad bank dram, 4 banks x 8mb addresses x 16 i/os the device is designed to comply with ddr2 dram key features such as posted cas# with additive latency, write latency = read latency -1, off-chip driver (ocd... |
| Description |
Fully synchronous operation
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| File Size |
2,185.60K /
61 Page |
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it Online |
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Price and Availability
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