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pmc
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| Part No. |
1991575
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| OCR Text |
...CRC-10 CSD CSI DAC DACS DDS DS0 ds1 ATM Adaptation Layer 1 ATM Circuit Steering ATM Monitoring Audio/Visual Multimedia Service American Nati...e1 E3 E4 ESF FCT FIFO FPGA FXO FXS GFC HEC LI LIU LSB M13 MIAC MIB mod MPEG2 MPHY MSB MULDEM OAM
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| Description |
From old datasheet system
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| File Size |
488.24K /
23 Page |
 View
it Online |
Download Datasheet
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zarlink
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| Part No. |
ZL30102
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| OCR Text |
ds1/e1 and H.110
Data Sheet Features
* Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock Supports Telcordia GR-1244-CORE Stratum 4 and 4E Supports ITU-T G... |
| Description |
Stratum 4/4E Redundant System Clock Synchronizer for T1/e1 and H.110
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| File Size |
385.42K /
47 Page |
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it Online |
Download Datasheet |
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IK Semiconductor
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| Part No. |
IN7100
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| OCR Text |
...d2, 1Hz and CLOUT for CLOUT for ds1, DS2, RES, HS, MS and BLK for T1, T2, T3 and AC
PIN CONFIGURATION
BLK ds1 DS2 bc4 g3 e3 d3 c3 g2 e2 c2 g1 e1 d1 c1 CLK CLOUT AC VSS 20 21 1 40 VDD T3 T2 f3 a3 b3 1HZ f2
IN7100
ad2 b2 f1 a1 b1 T1... |
| Description |
Automotive Car Watch
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| File Size |
257.08K /
7 Page |
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it Online |
Download Datasheet |
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Lineage Power
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| Part No. |
DJA
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| OCR Text |
...te in two different modes, as a ds1 or an e1 jitter attenuator. In both modes, the DJA blocks can be provisioned to operate as a second-order phase-locked loop (PLL) always, or it can switch to act as a first-order PLL during virtual tribut... |
| Description |
Digital Jitter Attenuation (DJA) Controller(数字信号抖动衰减控制
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| File Size |
105.15K /
2 Page |
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it Online |
Download Datasheet |
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Zarlink
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| Part No. |
ZL30410
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| OCR Text |
ds1, e1, 19.44 MHz and ST-BUS Meets jitter generation requirements for STM-1, OC-3, DS3, E3, J2 (DS2), e1 and ds1 interfaces Compatible with GR-253-CORE SONET stratum 3 and G.813 SEC timing compliant clocks Provides "hit-less" reference swi... |
| Description |
Multi-service Line Card PLL
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| File Size |
329.43K /
38 Page |
View
it Online |
Download Datasheet |
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Zarlink Semiconductor
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| Part No. |
ZL30102
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| OCR Text |
ds1/e1 and H.110
Data Sheet Features
* Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock Supports Telcordia GR-1244-CORE Stratum 4 and 4E Supports ITU-T G... |
| Description |
Stratum 4/4E Redundant System Clock Synchronizer for T1/e1 and H.110
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| File Size |
457.90K /
50 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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