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NXP Semiconductors N.V.
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| Part No. |
LPC2378
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| OCR Text |
...01 6 december 2006 preliminary data sheet
lpc2378_1 ? nxp b.v. 2006. all rights reserved. preliminary data sheet rev. 01 6 december 200...driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus speci... |
| Description |
Single-chip 16-bit/32-bit microcontrollers; 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC 单芯6-bit/32-bit微控制器12的ISP /国际检察官联合会，以太网，USB 2.0，CAN10 kB闪存位的ADC / DAC
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| File Size |
203.30K /
54 Page |
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it Online |
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Ramtron
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| Part No. |
FM25L512
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| OCR Text |
... read/write cycles ? 10 year data retention ? nodelay? writes ? advanced high-reliability ferroelectric process very fast serial...driven to a valid logic level to meet i dd specifications. * si may be connected to so for a sing... |
| Description |
3V F-RAM Memory
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| File Size |
232.68K /
13 Page |
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it Online |
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Atmel, Corp.
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| Part No. |
AT17LV010A
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| OCR Text |
... 13 ncs gnd nc (a2) ncasc nc nc data nc vcc nc
at17c/lv512a/010a 2 block diagram device configuration the control signals for the configur...driven low, the configuration eeprom resets its address counter and tri-states its data pin. the ncs... |
| Description |
1M FPGA Configuration EEPROM Memory(1M 现场可编程门阵列FPGA）配置EEPROM存储 100FPGA配置存储器（100万现场可编程门阵列（FPGA）的配置的EEPROM存储器）
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| File Size |
126.62K /
13 Page |
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it Online |
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ST Microelectronics
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| Part No. |
MK50H28PLCC52 MK50H28Q25
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| OCR Text |
...protocol processing - all frame data received). local management link protocol with optional bi-directional message processing. detects and ...driven by the mk50h28 only while it is the bus master. read is valid during the entire bus transacti... |
| Description |
MULTI LOGICAL LINK FRAME RELAY CONTROLLER
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| File Size |
431.87K /
64 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1353-40AC CY7C1353-66AC
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| OCR Text |
...erations with zero wait states data is transferred on every clock ? internally self-timed output buffer control to eliminate the need to u...driven low in order to load a new address. 89 clk input-clock clock input. used to capture all sync... |
| Description |
256Kx18 Flow-Through SRAM with NoBL Architecture 256K X 18 ZBT SRAM, 14 ns, PQFP100
256Kx18 Flow-Through SRAM with NoBL Architecture 256K X 18 ZBT SRAM, 11 ns, PQFP100
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| File Size |
162.65K /
13 Page |
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it Online |
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