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Maxim
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| Part No. |
MAX9325
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| OCR Text |
...LKO VCC CLKO VBB CLK1 1 2 3 4 5 6 7
*
21 20 19
Q3 Q3 Q4 VCC Q4 Q5 Q5
H
MAX9325
15 14 13 12
MAX9325
18 17 16 15
*
5...700MHz. The differential inputs can be configured to accept a single-ended signal when the unused co... |
| Description |
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
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| File Size |
316.07K /
12 Page |
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it Online |
Download Datasheet
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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
ACE9020 ACE9020NP1T ACE9020B ACE9020KG ACE9020NP1S
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| OCR Text |
...ures * Low Power Low Voltage (3.6 to 5.0 V) Operation * Power Down Modes * Differential Signals to Minimise Cross-talk * Auxiliary Oscillato...700MHz Differential Output Capacitance External Tank Inductance f = 90MHz External Tank Inductance f... |
| Description |
Receiver and Transmitter Interface
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| File Size |
412.90K /
6 Page |
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it Online |
Download Datasheet |
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ICS
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| Part No. |
ICS85408I
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| OCR Text |
... nQ3 Q3 nQ2 Q2 nQ1 Q1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q7 nQ7 OE GND VDD VDD GND VDD CLK nCLK Q0 nQ0
CLK nCLK
ICS85408I
24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package Top View
85... |
| Description |
Low Skew, 1-to-8 Differential-to-LVDS Fanout Buffer. Industrial Temp.
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| File Size |
160.19K /
12 Page |
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it Online |
Download Datasheet |
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ICS
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| Part No. |
M2006-04
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| OCR Text |
...Power-up PLL Ratio
1 2 3 4 5 6 7 8 9
FEATURES
28 29 30 31 32 33 34 35 36
M2006-04
(Top View)
18 17 16 15 14 13 12 11 10
S...700MHz. The input reference clock is selected from DIF_CLK 0, DIF_CLK 1, or REF_CLK by selecting the... |
| Description |
VCSO Frequency Translator
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| File Size |
300.56K /
12 Page |
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it Online |
Download Datasheet |
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ICS
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| Part No. |
M2006-11 M2006-21 M2006-11-622.0800
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| OCR Text |
...C VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
OC-12/48
Table 1: Example Input / Output Frequency Combinations Using Power-up PLL Ratio
No...700MHz. The input reference clock is selected from DIF_CLK 0, DIF_CLK 1, or REF_CLK by selecting the... |
| Description |
PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
SAW PLL for Frequency Translation with Add/Drop feature and Hitless Switching option
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| File Size |
312.67K /
14 Page |
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it Online |
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Integrated Circuit System
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| Part No. |
M2006-12
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| OCR Text |
...C VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
VCSO
P0 Div
(1 or 4)
FOUT0 nFOUT0
FEC_SEL3:0 FIN_SEL1:0
P1 Div
(1 or 4)
FOUT1 nFOUT1
Figure 2: Simplified Block Diagram
M2006-12 Datasheet Rev 1.0
M2006-12 VCSO Based FEC Cl... |
| Description |
VCSO BASED FEC CLOCK PLL
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| File Size |
262.41K /
8 Page |
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it Online |
Download Datasheet |
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Price and Availability
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