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Cypress Semiconductor Corp.
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| Part No. |
CY7B9911-5JCT
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| OCR Text |
...cy (input as low as 3.75 mhz) zero input to output delay 50% duty cycle outputs outputs drive 50 terminated lines low operating cur...phase freq det
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 2 of 13 pin configurat... |
| Description |
Programmable Skew Clock Buffer
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| File Size |
311.71K /
13 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7B9911-7JC
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| OCR Text |
...y (input as low as 3.75 mhz) zero input to output delay 50% duty-cycle outputs outputs drive 50 ? terminated lines low operating...phase freq det
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 2 of 12 block diagram desc... |
| Description |
Programmable Skew Clock Buffer (PSCB)
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| File Size |
239.64K /
12 Page |
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Integrated Device Technology, Inc.
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| Part No. |
ICS548M-03LFT ICS548M-03ILFT
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| OCR Text |
...uld be used. this chip is not a zero delay buffer. many applications may be able to use the ics527 for zero delay dividers. features ? pack...phase relationship between input and out put clocks can change at power up. use the ics570 or ics52... |
| Description |
548 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO16 0.150 INCH, ROHS COMPLIANT, SOIC-16
548 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO16 0.150 INCH, SOIC-16
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| File Size |
102.59K /
6 Page |
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PERICOM SEMICONDUCTOR CORP
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| Part No. |
PI6C2402 PI6C2402-WI
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| OCR Text |
.../workstation/ pc applications ? zero input-to-output delay ? low jitter: cycle-to-cycle jitter 100ps max. ? on-chip series damping resistor ...phase-locked loop clock driver product description the pi6c2402 features a low-skew, low-jitter, pha... |
| Description |
High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown; Package: SSOP; No of Pins: 36; Temperature Range: 0°C to 70°C
6C SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
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| File Size |
137.31K /
4 Page |
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| Part No. |
CY2SSTU877BVXC-32T
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| OCR Text |
zero delay buffe r cy2sstu877 rev 1.0, november 21, 2006 page 1 of 8 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax...phase-locked loop (pll) clock buffer is designed for a v dd of 1.8v, an av dd of 1.8v and sstl18 d... |
| Description |
SSTU SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
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| File Size |
127.85K /
8 Page |
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