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  hstl Datasheet PDF File

For hstl Found Datasheets File :: 1693    Search Time::1.281ms    
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    CY7C161KV18

Cypress Semiconductor
Part No. CY7C161KV18
OCR Text ...h high-speed transceiver logic (hstl) inputs and outputs variable drive hstl output buffers expanded hstl output voltage (1.4 v?v dd ) ? supports both 1.5-v and 1.8-v i/o supply available in 165-ball fine-pitch ball grid array (fbga) pac...
Description 144-Mbit DDR II SRAM Two-Word Burst Architecture

File Size 974.58K  /  32 Page

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    BCM8011 BCM8002 BCM801104 BCM5632

BOARDCOM[Broadcom Corporation.]
ETC
Part No. BCM8011 BCM8002 BCM801104 BCM5632
OCR Text ... interface compatible to SSTL_2/hstl (1.5) Class I EIA/JEDEC specifications On-chip phase-locked loop (PLL), providing clock synthesis from 156.25 MHz clock references Optional 8B/10B encoder and 10B/8B decoder in each channel Parallel or s...
Description 4-Channel 3.125 Gigabit Ethernet CMOS Transceiver
FOUR-CHANNEL 3.125 GIGABIT ETHERNET CMOS TRANSCEIVER
FOUR CHANNEL 3.125 GIGABIT ETHERNET CMOS TRANSCEIVER

File Size 126.21K  /  2 Page

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    Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
Part No. MAX9311 MAX9313 MAX9313EHJ MAX9311ECJ MAX9311EGJ MAX9311EHJ MAX9313ECJ MAX9313EGJ
OCR Text hstl Clock and Data Drivers General Description The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at...
Description Quadruple 2-Input Positive-NAND Gates 14-CDIP -55 to 125 1:10差分LVPECL/LVECL/hstl时钟和数据驱动器
1:10 Differential LVPECL/LVECL/hstl Clock and Data Drivers 9313 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
Quadruple 2-Input Positive-NAND Gates 20-LCCC -55 to 125 9311 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
1:10 Differential LVPECL/ LVECL/hstl Clock and Data Drivers

File Size 366.43K  /  12 Page

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    MC100EP14 MC100EP14D MC100EP14DT MC100EP14DTR2

ONSEMI[ON Semiconductor]
Part No. MC100EP14 MC100EP14D MC100EP14DT MC100EP14DTR2
OCR Text hstl Clock Driver The MC100EP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ende...
Description 3.3V / 5V 1:5 Differential ECL/PECL/hstl Clock Driver 100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20

File Size 67.05K  /  8 Page

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    IS61DDB41M18A

Integrated Silicon Solution, Inc
Part No. IS61DDB41M18A
OCR Text ...d with 0.75v to 0.9v vref. ? hstl input and output interface. ? registered addresses, write and read controls, byte writes, data in, and data outputs. ? full data coherency. ? boundary scan using limi ted set of jtag 1149.1 fu...
Description 1Mx18, 512Kx36 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

File Size 499.96K  /  30 Page

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    GS8182D09BD-375M

GSI TECHNOLOGY
Part No. GS8182D09BD-375M
OCR Text ...e power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq pin for programmable output drive strength ? ieee 1149.1 jtag-compliant boundary scan ? pin-compatible with 36mb, 72mb,...
Description 2M X 9 QDR SRAM, 0.45 ns, PBGA165

File Size 335.19K  /  35 Page

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    XILINX
Part No. XC3S1500-4 XC3S200
OCR Text ... Terminated Plus GTL GTLP hstl_I hstl_III hstl_I_18 hstl_II_18 hstl_III_18 LVCMOS12 LVCMOS15 LVCMOS18 LVCMOS25 LVCMOS33 LVTTL PCI33_3 SSTL18_I SSTL2_I SSTL2_II hstl High-Speed Transceiver Logic 1.5 I III 1.8 I II III...
Description Spartan-3 Field Programmable Gate Array

File Size 1,420.09K  /  159 Page

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