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KODENSHI KOREA
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| Part No. |
KK16C554PL KK16C554TQ
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| OCR Text |
...HR (write only)
0 1 1
DLL dlm IER
Bit 6 Bit 14 0
Bit 5 Bit 13 0
Bit 4 Bit 12 0
Bit 3 Bit 11 (EDSSI) Enable modem status interrupt
Bit 2 Bit 10 (ERLSI) Enable receiver line status interrupt
Bit 1 Bit 9 (ETBEI) Enable ... |
| Description |
QUAD-UART ASYNCHRONOUS COMMUNICATIONS ELEMENT
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| File Size |
393.56K /
21 Page |
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it Online |
Download Datasheet
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Intel
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| Part No. |
82091AA
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| OCR Text |
... BUFFER REGISTER 7 1 3 DLL(A B) dlm(A B) DIVISOR LATCHES (LSB AND MSB) REGISTERS 7 1 4 IER(A B) INTERRUPT ENABLE REGISTER 7 1 5 IIR(A B) INTERRUPT IDENTIFICATION REGISTER 7 1 6 FCR(A B) FIFO CONTROL REGISTER 7 1 7 LCR(A B) LINE CONTROL REGI... |
| Description |
ADVANCED INTEGRATED PERIPHERAL (AIP)
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| File Size |
1,761.87K /
205 Page |
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it Online |
Download Datasheet |
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Intersil
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| Part No. |
82C50
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| OCR Text |
...erator divisor latches dll and dlm. baudout may be used by the receiver section by tying this output to rclk.
4 82c50a out1 34 o l output 1: this is a general purpose out put that can be programmed active (low) by settingvcr(2) (out1)... |
| Description |
Communication Element, UART, Baud Rate Generator, CMOS, 625k Baud, 10MHz
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| File Size |
273.04K /
24 Page |
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it Online |
Download Datasheet |
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Exar, Corp.
Exar Corporation
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| Part No. |
ST16C450IJ44-F ST16C450CQ48 16C450
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| OCR Text |
... (clock) control registers (dll/dlm), and a user assessable scratchpad register (spr). table 2, internal register decode a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, lcr/lsr, spr): 0 0 0 receive holding reg... |
| Description |
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP48
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) 通用异步接收/发送器（UART
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| File Size |
185.80K /
28 Page |
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it Online |
Download Datasheet |
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