...ote
Note : 1. VIH (max)=4.6V ac for pulse width 10ns acceptable. 2.VIL(min)=-1.5V ac for pulse width 10ns acceptable. 3.Any input 0V V...dc output load circuit.
Rev 1 April, 2001
3
A-Data
Capacitance
TA=25, f-=1Mhz, VDD=3.3V P...
Description
Synchronous DRAM(4M X 8 Bit X 4 Banks) Synchronous DRAM(4M X 8 Bit X 4 Banks) 同步DRAM4米8位4银行 Synchronous DRAM(4M X 8 Bit X 4 Banks) 同步DRAM米8位4银行 133 Mhz LVTTL synchronous DRAM, 4 M x 8 bit x 4 banks