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Integrated Device Technology, Inc.
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| Part No. |
IDTCSPT857DPF IDTCSPT857DPFI IDTCSPT857DPAGI
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| OCR Text |
... 48-pin tssop and tvsop, 40-pin vfqfpn, and 56- pin vfbga packages description: the cspt857d is a pll based clock driver that acts as a zer...48 32 31 30 29 1 v ddq v ddq gnd 25 26 27 28 gnd y 5 y 5 gnd y 0 y 0 y 1 y 1 gnd y 2 y 2 clk clk av ... |
| Description |
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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| File Size |
138.75K /
15 Page |
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Integrated Device Technology, Inc.
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| Part No. |
IDTCSPT857DPAG
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| OCR Text |
...ailable in 48-pin tssop, 40-pin vfqfpn, and 56-pin vfbga packages description: the cspt857d is a pll based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(clk, clk ) to 10 differential output ... |
| Description |
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER 875 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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| File Size |
144.37K /
15 Page |
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it Online |
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IDT
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| Part No. |
IDT5T9820NLI IDT5T9820NLI8
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| OCR Text |
...? lock indicator ? available in vfqfpn package idt5t9820 eeprom programmable 2.5v zero delay pll clock driver description: the idt5t9820 is ...48 47 46 45 44 43 42 3 q 1 v dd v dd trst/sel v dd 4 q 1 4 q 0 v dd q4 41 40 39 38 37 36 35 v dd q4 ... |
| Description |
EEPROM Programmable 2.5V Zero Delay PLL Clock Driver
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| File Size |
208.51K /
35 Page |
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it Online |
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IDT
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| Part No. |
IDT5T9821NLI IDT5T9821NLI8
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| OCR Text |
...? lock indicator ? available in vfqfpn package idt5t9821 eeprom programmable 2.5v zero delay pll differential clock driver description: the ...48 47 46 45 44 43 42 3 q v dd v dd trst/sel v dd 4 q 4 q v dd q4 41 40 39 38 37 36 35 v dd q4 v dd 4... |
| Description |
EEPROM Programmable 2.5V Zero Delay PLL Differential Clock Driver
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| File Size |
209.94K /
35 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT5T93GL16NLI8
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| OCR Text |
...mode ? 2.5v v dd ? available in vfqfpn package applications: ? clock distribution functional block diagram
industrial temperature range 2 ...48 47 46 45 44 43 42 41 40 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 v dd g 1 q 1 q 1 q 2 q 2 q 3 q ... |
| Description |
2.5V LVDS 1:16 Glitchless Clock Buffer TeraBuffer II
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| File Size |
116.64K /
15 Page |
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it Online |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
74SSTV16859NL
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| OCR Text |
...f, r = 0) ? available in 56 pin vfqfpn and 64 pin tssop packages the idt logo is a registered trademark of integrated device technology, inc. 51 48 49 45 35 r 1d c1 16 q 1a reset clk clk v ref d 1 to 12 other channels 32 q 1b
2 industria... |
| Description |
SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56
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| File Size |
75.52K /
6 Page |
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it Online |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
74SSTVF16859NLG8
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| OCR Text |
...f, r = 0) ? available in 56 pin vfqfpn and 64 pin tssop packages the idt logo is a registered trademark of integrated device technology, inc...48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 q 11a q 10a q 9a q 5a q 4a q 3a q 2a q 1a gnd q 13b ... |
| Description |
SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56
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| File Size |
63.09K /
7 Page |
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it Online |
Download Datasheet |
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