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				NXP Semiconductors
Part No.	TDA10025HN
OCR Text	...ta 0 adc data 0 adc input 1 rgu distributes resets to all blocks cgu distributes clocks to all blocks config commands settings for different blocks i2c-bus to dtl-mmio i2c-bus interface tda10025hn_sds all information provided in this docu...
Description	Dual cable demodulator
File Size	103.08K / 8 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	IDTCSPT855
OCR Text	...jitter (cycle-to-cycle): 50ps ? distributes one differential clock input to four differential clock outputs ? enters low power mode and 3-state outputs when input clk signal is less than 20mhz or pwrdwn is low ? operates from dual 2.5v supp...
Description	2.5V PHASE LOCKED LOOP CLOCK DRIVER
File Size	106.06K / 10 Page	View it Online	Download Datasheet

				Analog Devices
Part No.	AD9910 ADCLK846 CN-0121 AD9520
OCR Text	... the internal pll. the ad9520 distributes phase aligned 1 ghz ref clks (pecl outputs) to all four a d99 10 evaluation boards . it also provides a cmos output clock to the tektronix dg2020a data pattern generator for the ...
Description	Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers
File Size	393.03K / 3 Page	View it Online	Download Datasheet

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